drivers/clk/mvebu/ap806-system-controller.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Marvell Armada AP806 System Controller
   4  *
   5  * Copyright (C) 2016 Marvell
   6  *
   7  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   8  *
   9  */
  10
  11 #define pr_fmt(fmt) "ap806-system-controller: " fmt
  12
  13 #include "armada_ap_cp_helper.h"
  14 #include <linux/clk-provider.h>
  15 #include <linux/mfd/syscon.h>
  16 #include <linux/init.h>
  17 #include <linux/of.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regmap.h>
  20
  21 #define AP806_SAR_REG                   0x400
  22 #define AP806_SAR_CLKFREQ_MODE_MASK     0x1f
  23
  24 #define AP806_CLK_NUM                   6
  25
  26 static struct clk *ap806_clks[AP806_CLK_NUM];
  27
  28 static struct clk_onecell_data ap806_clk_data = {
  29         .clks = ap806_clks,
  30         .clk_num = AP806_CLK_NUM,
  31 };
  32
  33 static int ap806_get_sar_clocks(unsigned int freq_mode,
  34                                 unsigned int *cpuclk_freq,
  35                                 unsigned int *dclk_freq)
  36 {
  37         switch (freq_mode) {
  38         case 0x0:
  39                 *cpuclk_freq = 2000;
  40                 *dclk_freq = 600;
  41                 break;
  42         case 0x1:
  43                 *cpuclk_freq = 2000;
  44                 *dclk_freq = 525;
  45                 break;
  46         case 0x6:
  47                 *cpuclk_freq = 1800;
  48                 *dclk_freq = 600;
  49                 break;
  50         case 0x7:
  51                 *cpuclk_freq = 1800;
  52                 *dclk_freq = 525;
  53                 break;
  54         case 0x4:
  55                 *cpuclk_freq = 1600;
  56                 *dclk_freq = 400;
  57                 break;
  58         case 0xB:
  59                 *cpuclk_freq = 1600;
  60                 *dclk_freq = 450;
  61                 break;
  62         case 0xD:
  63                 *cpuclk_freq = 1600;
  64                 *dclk_freq = 525;
  65                 break;
  66         case 0x1a:
  67                 *cpuclk_freq = 1400;
  68                 *dclk_freq = 400;
  69                 break;
  70         case 0x14:
  71                 *cpuclk_freq = 1300;
  72                 *dclk_freq = 400;
  73                 break;
  74         case 0x17:
  75                 *cpuclk_freq = 1300;
  76                 *dclk_freq = 325;
  77                 break;
  78         case 0x19:
  79                 *cpuclk_freq = 1200;
  80                 *dclk_freq = 400;
  81                 break;
  82         case 0x13:
  83                 *cpuclk_freq = 1000;
  84                 *dclk_freq = 325;
  85                 break;
  86         case 0x1d:
  87                 *cpuclk_freq = 1000;
  88                 *dclk_freq = 400;
  89                 break;
  90         case 0x1c:
  91                 *cpuclk_freq = 800;
  92                 *dclk_freq = 400;
  93                 break;
  94         case 0x1b:
  95                 *cpuclk_freq = 600;
  96                 *dclk_freq = 400;
  97                 break;
  98         default:
  99                 return -EINVAL;
 100         }
 101
 102         return 0;
 103 }
 104
 105 static int ap806_syscon_common_probe(struct platform_device *pdev,
 106                                      struct device_node *syscon_node)
 107 {
 108         unsigned int freq_mode, cpuclk_freq, dclk_freq;
 109         const char *name, *fixedclk_name;
 110         struct device *dev = &pdev->dev;
 111         struct device_node *np = dev->of_node;
 112         struct regmap *regmap;
 113         u32 reg;
 114         int ret;
 115
 116         regmap = syscon_node_to_regmap(syscon_node);
 117         if (IS_ERR(regmap)) {
 118                 dev_err(dev, "cannot get regmap\n");
 119                 return PTR_ERR(regmap);
 120         }
 121
 122         ret = regmap_read(regmap, AP806_SAR_REG, &reg);
 123         if (ret) {
 124                 dev_err(dev, "cannot read from regmap\n");
 125                 return ret;
 126         }
 127
 128         freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
 129
 130         if (of_device_is_compatible(pdev->dev.of_node,
 131                                     "marvell,ap806-clock")) {
 132                 ret = ap806_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
 133         } else {
 134                 dev_err(dev, "compatible not supported\n");
 135                 return -EINVAL;
 136         }
 137
 138         if (ret) {
 139                 dev_err(dev, "invalid Sample at Reset value\n");
 140                 return ret;
 141         }
 142
 143         /* Convert to hertz */
 144         cpuclk_freq *= 1000 * 1000;
 145         dclk_freq *= 1000 * 1000;
 146
 147         /* CPU clocks depend on the Sample At Reset configuration */
 148         name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-0");
 149         ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
 150                                                 0, cpuclk_freq);
 151         if (IS_ERR(ap806_clks[0])) {
 152                 ret = PTR_ERR(ap806_clks[0]);
 153                 goto fail0;
 154         }
 155
 156         name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-1");
 157         ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
 158                                                 cpuclk_freq);
 159         if (IS_ERR(ap806_clks[1])) {
 160                 ret = PTR_ERR(ap806_clks[1]);
 161                 goto fail1;
 162         }
 163
 164         /* Fixed clock is always 1200 Mhz */
 165         fixedclk_name = ap_cp_unique_name(dev, syscon_node, "fixed");
 166         ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
 167                                                 0, 1200 * 1000 * 1000);
 168         if (IS_ERR(ap806_clks[2])) {
 169                 ret = PTR_ERR(ap806_clks[2]);
 170                 goto fail2;
 171         }
 172
 173         /* MSS Clock is fixed clock divided by 6 */
 174         name = ap_cp_unique_name(dev, syscon_node, "mss");
 175         ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
 176                                                   0, 1, 6);
 177         if (IS_ERR(ap806_clks[3])) {
 178                 ret = PTR_ERR(ap806_clks[3]);
 179                 goto fail3;
 180         }
 181
 182         /* SDIO(/eMMC) Clock is fixed clock divided by 3 */
 183         name = ap_cp_unique_name(dev, syscon_node, "sdio");
 184         ap806_clks[4] = clk_register_fixed_factor(NULL, name,
 185                                                   fixedclk_name,
 186                                                   0, 1, 3);
 187         if (IS_ERR(ap806_clks[4])) {
 188                 ret = PTR_ERR(ap806_clks[4]);
 189                 goto fail4;
 190         }
 191
 192         /* AP-DCLK(HCLK) Clock is DDR clock divided by 2 */
 193         name = ap_cp_unique_name(dev, syscon_node, "ap-dclk");
 194         ap806_clks[5] = clk_register_fixed_rate(dev, name, NULL, 0, dclk_freq);
 195         if (IS_ERR(ap806_clks[5])) {
 196                 ret = PTR_ERR(ap806_clks[5]);
 197                 goto fail5;
 198         }
 199
 200         ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
 201         if (ret)
 202                 goto fail_clk_add;
 203
 204         return 0;
 205
 206 fail_clk_add:
 207         clk_unregister_fixed_factor(ap806_clks[5]);
 208 fail5:
 209         clk_unregister_fixed_factor(ap806_clks[4]);
 210 fail4:
 211         clk_unregister_fixed_factor(ap806_clks[3]);
 212 fail3:
 213         clk_unregister_fixed_rate(ap806_clks[2]);
 214 fail2:
 215         clk_unregister_fixed_rate(ap806_clks[1]);
 216 fail1:
 217         clk_unregister_fixed_rate(ap806_clks[0]);
 218 fail0:
 219         return ret;
 220 }
 221
 222 static int ap806_syscon_legacy_probe(struct platform_device *pdev)
 223 {
 224         dev_warn(&pdev->dev, FW_WARN "Using legacy device tree binding\n");
 225         dev_warn(&pdev->dev, FW_WARN "Update your device tree:\n");
 226         dev_warn(&pdev->dev, FW_WARN
 227                  "This binding won't be supported in future kernel\n");
 228
 229         return ap806_syscon_common_probe(pdev, pdev->dev.of_node);
 230
 231 }
 232
 233 static int ap806_clock_probe(struct platform_device *pdev)
 234 {
 235         return ap806_syscon_common_probe(pdev, pdev->dev.of_node->parent);
 236 }
 237
 238 static const struct of_device_id ap806_syscon_legacy_of_match[] = {
 239         { .compatible = "marvell,ap806-system-controller", },
 240         { }
 241 };
 242
 243 static struct platform_driver ap806_syscon_legacy_driver = {
 244         .probe = ap806_syscon_legacy_probe,
 245         .driver         = {
 246                 .name   = "marvell-ap806-system-controller",
 247                 .of_match_table = ap806_syscon_legacy_of_match,
 248                 .suppress_bind_attrs = true,
 249         },
 250 };
 251 builtin_platform_driver(ap806_syscon_legacy_driver);
 252
 253 static const struct of_device_id ap806_clock_of_match[] = {
 254         { .compatible = "marvell,ap806-clock", },
 255         { }
 256 };
 257
 258 static struct platform_driver ap806_clock_driver = {
 259         .probe = ap806_clock_probe,
 260         .driver         = {
 261                 .name   = "marvell-ap806-clock",
 262                 .of_match_table = ap806_clock_of_match,
 263                 .suppress_bind_attrs = true,
 264         },
 265 };
 266 builtin_platform_driver(ap806_clock_driver);