drivers/clk/meson/meson8b.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015 Endless Mobile, Inc.
   4  * Author: Carlo Caione <carlo@endlessm.com>
   5  *
   6  * Copyright (c) 2016 BayLibre, Inc.
   7  * Michael Turquette <mturquette@baylibre.com>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/init.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/of_address.h>
  15 #include <linux/reset-controller.h>
  16 #include <linux/slab.h>
  17 #include <linux/regmap.h>
  18
  19 #include "meson8b.h"
  20 #include "clk-regmap.h"
  21 #include "clk-pll.h"
  22 #include "clk-mpll.h"
  23
  24 static DEFINE_SPINLOCK(meson_clk_lock);
  25
  26 struct meson8b_clk_reset {
  27         struct reset_controller_dev reset;
  28         struct regmap *regmap;
  29 };
  30
  31 static const struct pll_params_table sys_pll_params_table[] = {
  32         PLL_PARAMS(50, 1),
  33         PLL_PARAMS(51, 1),
  34         PLL_PARAMS(52, 1),
  35         PLL_PARAMS(53, 1),
  36         PLL_PARAMS(54, 1),
  37         PLL_PARAMS(55, 1),
  38         PLL_PARAMS(56, 1),
  39         PLL_PARAMS(57, 1),
  40         PLL_PARAMS(58, 1),
  41         PLL_PARAMS(59, 1),
  42         PLL_PARAMS(60, 1),
  43         PLL_PARAMS(61, 1),
  44         PLL_PARAMS(62, 1),
  45         PLL_PARAMS(63, 1),
  46         PLL_PARAMS(64, 1),
  47         PLL_PARAMS(65, 1),
  48         PLL_PARAMS(66, 1),
  49         PLL_PARAMS(67, 1),
  50         PLL_PARAMS(68, 1),
  51         PLL_PARAMS(84, 1),
  52         { /* sentinel */ },
  53 };
  54
  55 static struct clk_regmap meson8b_fixed_pll_dco = {
  56         .data = &(struct meson_clk_pll_data){
  57                 .en = {
  58                         .reg_off = HHI_MPLL_CNTL,
  59                         .shift   = 30,
  60                         .width   = 1,
  61                 },
  62                 .m = {
  63                         .reg_off = HHI_MPLL_CNTL,
  64                         .shift   = 0,
  65                         .width   = 9,
  66                 },
  67                 .n = {
  68                         .reg_off = HHI_MPLL_CNTL,
  69                         .shift   = 9,
  70                         .width   = 5,
  71                 },
  72                 .frac = {
  73                         .reg_off = HHI_MPLL_CNTL2,
  74                         .shift   = 0,
  75                         .width   = 12,
  76                 },
  77                 .l = {
  78                         .reg_off = HHI_MPLL_CNTL,
  79                         .shift   = 31,
  80                         .width   = 1,
  81                 },
  82                 .rst = {
  83                         .reg_off = HHI_MPLL_CNTL,
  84                         .shift   = 29,
  85                         .width   = 1,
  86                 },
  87         },
  88         .hw.init = &(struct clk_init_data){
  89                 .name = "fixed_pll_dco",
  90                 .ops = &meson_clk_pll_ro_ops,
  91                 .parent_data = &(const struct clk_parent_data) {
  92                         .fw_name = "xtal",
  93                         .name = "xtal",
  94                         .index = -1,
  95                 },
  96                 .num_parents = 1,
  97         },
  98 };
  99
 100 static struct clk_regmap meson8b_fixed_pll = {
 101         .data = &(struct clk_regmap_div_data){
 102                 .offset = HHI_MPLL_CNTL,
 103                 .shift = 16,
 104                 .width = 2,
 105                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 106         },
 107         .hw.init = &(struct clk_init_data){
 108                 .name = "fixed_pll",
 109                 .ops = &clk_regmap_divider_ro_ops,
 110                 .parent_hws = (const struct clk_hw *[]) {
 111                         &meson8b_fixed_pll_dco.hw
 112                 },
 113                 .num_parents = 1,
 114                 /*
 115                  * This clock won't ever change at runtime so
 116                  * CLK_SET_RATE_PARENT is not required
 117                  */
 118         },
 119 };
 120
 121 static struct clk_fixed_factor hdmi_pll_dco_in = {
 122         .mult = 2,
 123         .div = 1,
 124         .hw.init = &(struct clk_init_data){
 125                 .name = "hdmi_pll_dco_in",
 126                 .ops = &clk_fixed_factor_ops,
 127                 .parent_data = &(const struct clk_parent_data) {
 128                         .fw_name = "xtal",
 129                         .index = -1,
 130                 },
 131                 .num_parents = 1,
 132         },
 133 };
 134
 135 /*
 136  * Taken from the vendor driver for the 2970/2975MHz (both only differ in the
 137  * FRAC part in HHI_VID_PLL_CNTL2) where these values are identical for Meson8,
 138  * Meson8b and Meson8m2. This doubles the input (or output - it's not clear
 139  * which one but the result is the same) clock. The vendor driver additionally
 140  * has the following comment about: "optimise HPLL VCO 2.97GHz performance".
 141  */
 142 static const struct reg_sequence meson8b_hdmi_pll_init_regs[] = {
 143         { .reg = HHI_VID_PLL_CNTL2,     .def = 0x69c84000 },
 144         { .reg = HHI_VID_PLL_CNTL3,     .def = 0x8a46c023 },
 145         { .reg = HHI_VID_PLL_CNTL4,     .def = 0x4123b100 },
 146         { .reg = HHI_VID_PLL_CNTL5,     .def = 0x00012385 },
 147         { .reg = HHI_VID2_PLL_CNTL2,    .def = 0x0430a800 },
 148 };
 149
 150 static const struct pll_params_table hdmi_pll_params_table[] = {
 151         PLL_PARAMS(40, 1),
 152         PLL_PARAMS(42, 1),
 153         PLL_PARAMS(44, 1),
 154         PLL_PARAMS(45, 1),
 155         PLL_PARAMS(49, 1),
 156         PLL_PARAMS(52, 1),
 157         PLL_PARAMS(54, 1),
 158         PLL_PARAMS(56, 1),
 159         PLL_PARAMS(59, 1),
 160         PLL_PARAMS(60, 1),
 161         PLL_PARAMS(61, 1),
 162         PLL_PARAMS(62, 1),
 163         PLL_PARAMS(64, 1),
 164         PLL_PARAMS(66, 1),
 165         PLL_PARAMS(68, 1),
 166         PLL_PARAMS(71, 1),
 167         PLL_PARAMS(82, 1),
 168         { /* sentinel */ }
 169 };
 170
 171 static struct clk_regmap meson8b_hdmi_pll_dco = {
 172         .data = &(struct meson_clk_pll_data){
 173                 .en = {
 174                         .reg_off = HHI_VID_PLL_CNTL,
 175                         .shift   = 30,
 176                         .width   = 1,
 177                 },
 178                 .m = {
 179                         .reg_off = HHI_VID_PLL_CNTL,
 180                         .shift   = 0,
 181                         .width   = 9,
 182                 },
 183                 .n = {
 184                         .reg_off = HHI_VID_PLL_CNTL,
 185                         .shift   = 10,
 186                         .width   = 5,
 187                 },
 188                 .frac = {
 189                         .reg_off = HHI_VID_PLL_CNTL2,
 190                         .shift   = 0,
 191                         .width   = 12,
 192                 },
 193                 .l = {
 194                         .reg_off = HHI_VID_PLL_CNTL,
 195                         .shift   = 31,
 196                         .width   = 1,
 197                 },
 198                 .rst = {
 199                         .reg_off = HHI_VID_PLL_CNTL,
 200                         .shift   = 29,
 201                         .width   = 1,
 202                 },
 203                 .table = hdmi_pll_params_table,
 204                 .init_regs = meson8b_hdmi_pll_init_regs,
 205                 .init_count = ARRAY_SIZE(meson8b_hdmi_pll_init_regs),
 206         },
 207         .hw.init = &(struct clk_init_data){
 208                 /* sometimes also called "HPLL" or "HPLL PLL" */
 209                 .name = "hdmi_pll_dco",
 210                 .ops = &meson_clk_pll_ops,
 211                 .parent_hws = (const struct clk_hw *[]) {
 212                         &hdmi_pll_dco_in.hw
 213                 },
 214                 .num_parents = 1,
 215         },
 216 };
 217
 218 static struct clk_regmap meson8b_hdmi_pll_lvds_out = {
 219         .data = &(struct clk_regmap_div_data){
 220                 .offset = HHI_VID_PLL_CNTL,
 221                 .shift = 16,
 222                 .width = 2,
 223                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 224         },
 225         .hw.init = &(struct clk_init_data){
 226                 .name = "hdmi_pll_lvds_out",
 227                 .ops = &clk_regmap_divider_ops,
 228                 .parent_hws = (const struct clk_hw *[]) {
 229                         &meson8b_hdmi_pll_dco.hw
 230                 },
 231                 .num_parents = 1,
 232                 .flags = CLK_SET_RATE_PARENT,
 233         },
 234 };
 235
 236 static struct clk_regmap meson8b_hdmi_pll_hdmi_out = {
 237         .data = &(struct clk_regmap_div_data){
 238                 .offset = HHI_VID_PLL_CNTL,
 239                 .shift = 18,
 240                 .width = 2,
 241                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 242         },
 243         .hw.init = &(struct clk_init_data){
 244                 .name = "hdmi_pll_hdmi_out",
 245                 .ops = &clk_regmap_divider_ops,
 246                 .parent_hws = (const struct clk_hw *[]) {
 247                         &meson8b_hdmi_pll_dco.hw
 248                 },
 249                 .num_parents = 1,
 250                 .flags = CLK_SET_RATE_PARENT,
 251         },
 252 };
 253
 254 static struct clk_regmap meson8b_sys_pll_dco = {
 255         .data = &(struct meson_clk_pll_data){
 256                 .en = {
 257                         .reg_off = HHI_SYS_PLL_CNTL,
 258                         .shift   = 30,
 259                         .width   = 1,
 260                 },
 261                 .m = {
 262                         .reg_off = HHI_SYS_PLL_CNTL,
 263                         .shift   = 0,
 264                         .width   = 9,
 265                 },
 266                 .n = {
 267                         .reg_off = HHI_SYS_PLL_CNTL,
 268                         .shift   = 9,
 269                         .width   = 5,
 270                 },
 271                 .l = {
 272                         .reg_off = HHI_SYS_PLL_CNTL,
 273                         .shift   = 31,
 274                         .width   = 1,
 275                 },
 276                 .rst = {
 277                         .reg_off = HHI_SYS_PLL_CNTL,
 278                         .shift   = 29,
 279                         .width   = 1,
 280                 },
 281                 .table = sys_pll_params_table,
 282         },
 283         .hw.init = &(struct clk_init_data){
 284                 .name = "sys_pll_dco",
 285                 .ops = &meson_clk_pll_ops,
 286                 .parent_data = &(const struct clk_parent_data) {
 287                         .fw_name = "xtal",
 288                         .name = "xtal",
 289                         .index = -1,
 290                 },
 291                 .num_parents = 1,
 292         },
 293 };
 294
 295 static struct clk_regmap meson8b_sys_pll = {
 296         .data = &(struct clk_regmap_div_data){
 297                 .offset = HHI_SYS_PLL_CNTL,
 298                 .shift = 16,
 299                 .width = 2,
 300                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 301         },
 302         .hw.init = &(struct clk_init_data){
 303                 .name = "sys_pll",
 304                 .ops = &clk_regmap_divider_ops,
 305                 .parent_hws = (const struct clk_hw *[]) {
 306                         &meson8b_sys_pll_dco.hw
 307                 },
 308                 .num_parents = 1,
 309                 .flags = CLK_SET_RATE_PARENT,
 310         },
 311 };
 312
 313 static struct clk_fixed_factor meson8b_fclk_div2_div = {
 314         .mult = 1,
 315         .div = 2,
 316         .hw.init = &(struct clk_init_data){
 317                 .name = "fclk_div2_div",
 318                 .ops = &clk_fixed_factor_ops,
 319                 .parent_hws = (const struct clk_hw *[]) {
 320                         &meson8b_fixed_pll.hw
 321                 },
 322                 .num_parents = 1,
 323         },
 324 };
 325
 326 static struct clk_regmap meson8b_fclk_div2 = {
 327         .data = &(struct clk_regmap_gate_data){
 328                 .offset = HHI_MPLL_CNTL6,
 329                 .bit_idx = 27,
 330         },
 331         .hw.init = &(struct clk_init_data){
 332                 .name = "fclk_div2",
 333                 .ops = &clk_regmap_gate_ops,
 334                 .parent_hws = (const struct clk_hw *[]) {
 335                         &meson8b_fclk_div2_div.hw
 336                 },
 337                 .num_parents = 1,
 338         },
 339 };
 340
 341 static struct clk_fixed_factor meson8b_fclk_div3_div = {
 342         .mult = 1,
 343         .div = 3,
 344         .hw.init = &(struct clk_init_data){
 345                 .name = "fclk_div3_div",
 346                 .ops = &clk_fixed_factor_ops,
 347                 .parent_hws = (const struct clk_hw *[]) {
 348                         &meson8b_fixed_pll.hw
 349                 },
 350                 .num_parents = 1,
 351         },
 352 };
 353
 354 static struct clk_regmap meson8b_fclk_div3 = {
 355         .data = &(struct clk_regmap_gate_data){
 356                 .offset = HHI_MPLL_CNTL6,
 357                 .bit_idx = 28,
 358         },
 359         .hw.init = &(struct clk_init_data){
 360                 .name = "fclk_div3",
 361                 .ops = &clk_regmap_gate_ops,
 362                 .parent_hws = (const struct clk_hw *[]) {
 363                         &meson8b_fclk_div3_div.hw
 364                 },
 365                 .num_parents = 1,
 366         },
 367 };
 368
 369 static struct clk_fixed_factor meson8b_fclk_div4_div = {
 370         .mult = 1,
 371         .div = 4,
 372         .hw.init = &(struct clk_init_data){
 373                 .name = "fclk_div4_div",
 374                 .ops = &clk_fixed_factor_ops,
 375                 .parent_hws = (const struct clk_hw *[]) {
 376                         &meson8b_fixed_pll.hw
 377                 },
 378                 .num_parents = 1,
 379         },
 380 };
 381
 382 static struct clk_regmap meson8b_fclk_div4 = {
 383         .data = &(struct clk_regmap_gate_data){
 384                 .offset = HHI_MPLL_CNTL6,
 385                 .bit_idx = 29,
 386         },
 387         .hw.init = &(struct clk_init_data){
 388                 .name = "fclk_div4",
 389                 .ops = &clk_regmap_gate_ops,
 390                 .parent_hws = (const struct clk_hw *[]) {
 391                         &meson8b_fclk_div4_div.hw
 392                 },
 393                 .num_parents = 1,
 394         },
 395 };
 396
 397 static struct clk_fixed_factor meson8b_fclk_div5_div = {
 398         .mult = 1,
 399         .div = 5,
 400         .hw.init = &(struct clk_init_data){
 401                 .name = "fclk_div5_div",
 402                 .ops = &clk_fixed_factor_ops,
 403                 .parent_hws = (const struct clk_hw *[]) {
 404                         &meson8b_fixed_pll.hw
 405                 },
 406                 .num_parents = 1,
 407         },
 408 };
 409
 410 static struct clk_regmap meson8b_fclk_div5 = {
 411         .data = &(struct clk_regmap_gate_data){
 412                 .offset = HHI_MPLL_CNTL6,
 413                 .bit_idx = 30,
 414         },
 415         .hw.init = &(struct clk_init_data){
 416                 .name = "fclk_div5",
 417                 .ops = &clk_regmap_gate_ops,
 418                 .parent_hws = (const struct clk_hw *[]) {
 419                         &meson8b_fclk_div5_div.hw
 420                 },
 421                 .num_parents = 1,
 422         },
 423 };
 424
 425 static struct clk_fixed_factor meson8b_fclk_div7_div = {
 426         .mult = 1,
 427         .div = 7,
 428         .hw.init = &(struct clk_init_data){
 429                 .name = "fclk_div7_div",
 430                 .ops = &clk_fixed_factor_ops,
 431                 .parent_hws = (const struct clk_hw *[]) {
 432                         &meson8b_fixed_pll.hw
 433                 },
 434                 .num_parents = 1,
 435         },
 436 };
 437
 438 static struct clk_regmap meson8b_fclk_div7 = {
 439         .data = &(struct clk_regmap_gate_data){
 440                 .offset = HHI_MPLL_CNTL6,
 441                 .bit_idx = 31,
 442         },
 443         .hw.init = &(struct clk_init_data){
 444                 .name = "fclk_div7",
 445                 .ops = &clk_regmap_gate_ops,
 446                 .parent_hws = (const struct clk_hw *[]) {
 447                         &meson8b_fclk_div7_div.hw
 448                 },
 449                 .num_parents = 1,
 450         },
 451 };
 452
 453 static struct clk_regmap meson8b_mpll_prediv = {
 454         .data = &(struct clk_regmap_div_data){
 455                 .offset = HHI_MPLL_CNTL5,
 456                 .shift = 12,
 457                 .width = 1,
 458         },
 459         .hw.init = &(struct clk_init_data){
 460                 .name = "mpll_prediv",
 461                 .ops = &clk_regmap_divider_ro_ops,
 462                 .parent_hws = (const struct clk_hw *[]) {
 463                         &meson8b_fixed_pll.hw
 464                 },
 465                 .num_parents = 1,
 466         },
 467 };
 468
 469 static struct clk_regmap meson8b_mpll0_div = {
 470         .data = &(struct meson_clk_mpll_data){
 471                 .sdm = {
 472                         .reg_off = HHI_MPLL_CNTL7,
 473                         .shift   = 0,
 474                         .width   = 14,
 475                 },
 476                 .sdm_en = {
 477                         .reg_off = HHI_MPLL_CNTL7,
 478                         .shift   = 15,
 479                         .width   = 1,
 480                 },
 481                 .n2 = {
 482                         .reg_off = HHI_MPLL_CNTL7,
 483                         .shift   = 16,
 484                         .width   = 9,
 485                 },
 486                 .ssen = {
 487                         .reg_off = HHI_MPLL_CNTL,
 488                         .shift   = 25,
 489                         .width   = 1,
 490                 },
 491                 .lock = &meson_clk_lock,
 492         },
 493         .hw.init = &(struct clk_init_data){
 494                 .name = "mpll0_div",
 495                 .ops = &meson_clk_mpll_ops,
 496                 .parent_hws = (const struct clk_hw *[]) {
 497                         &meson8b_mpll_prediv.hw
 498                 },
 499                 .num_parents = 1,
 500         },
 501 };
 502
 503 static struct clk_regmap meson8b_mpll0 = {
 504         .data = &(struct clk_regmap_gate_data){
 505                 .offset = HHI_MPLL_CNTL7,
 506                 .bit_idx = 14,
 507         },
 508         .hw.init = &(struct clk_init_data){
 509                 .name = "mpll0",
 510                 .ops = &clk_regmap_gate_ops,
 511                 .parent_hws = (const struct clk_hw *[]) {
 512                         &meson8b_mpll0_div.hw
 513                 },
 514                 .num_parents = 1,
 515                 .flags = CLK_SET_RATE_PARENT,
 516         },
 517 };
 518
 519 static struct clk_regmap meson8b_mpll1_div = {
 520         .data = &(struct meson_clk_mpll_data){
 521                 .sdm = {
 522                         .reg_off = HHI_MPLL_CNTL8,
 523                         .shift   = 0,
 524                         .width   = 14,
 525                 },
 526                 .sdm_en = {
 527                         .reg_off = HHI_MPLL_CNTL8,
 528                         .shift   = 15,
 529                         .width   = 1,
 530                 },
 531                 .n2 = {
 532                         .reg_off = HHI_MPLL_CNTL8,
 533                         .shift   = 16,
 534                         .width   = 9,
 535                 },
 536                 .lock = &meson_clk_lock,
 537         },
 538         .hw.init = &(struct clk_init_data){
 539                 .name = "mpll1_div",
 540                 .ops = &meson_clk_mpll_ops,
 541                 .parent_hws = (const struct clk_hw *[]) {
 542                         &meson8b_mpll_prediv.hw
 543                 },
 544                 .num_parents = 1,
 545         },
 546 };
 547
 548 static struct clk_regmap meson8b_mpll1 = {
 549         .data = &(struct clk_regmap_gate_data){
 550                 .offset = HHI_MPLL_CNTL8,
 551                 .bit_idx = 14,
 552         },
 553         .hw.init = &(struct clk_init_data){
 554                 .name = "mpll1",
 555                 .ops = &clk_regmap_gate_ops,
 556                 .parent_hws = (const struct clk_hw *[]) {
 557                         &meson8b_mpll1_div.hw
 558                 },
 559                 .num_parents = 1,
 560                 .flags = CLK_SET_RATE_PARENT,
 561         },
 562 };
 563
 564 static struct clk_regmap meson8b_mpll2_div = {
 565         .data = &(struct meson_clk_mpll_data){
 566                 .sdm = {
 567                         .reg_off = HHI_MPLL_CNTL9,
 568                         .shift   = 0,
 569                         .width   = 14,
 570                 },
 571                 .sdm_en = {
 572                         .reg_off = HHI_MPLL_CNTL9,
 573                         .shift   = 15,
 574                         .width   = 1,
 575                 },
 576                 .n2 = {
 577                         .reg_off = HHI_MPLL_CNTL9,
 578                         .shift   = 16,
 579                         .width   = 9,
 580                 },
 581                 .lock = &meson_clk_lock,
 582         },
 583         .hw.init = &(struct clk_init_data){
 584                 .name = "mpll2_div",
 585                 .ops = &meson_clk_mpll_ops,
 586                 .parent_hws = (const struct clk_hw *[]) {
 587                         &meson8b_mpll_prediv.hw
 588                 },
 589                 .num_parents = 1,
 590         },
 591 };
 592
 593 static struct clk_regmap meson8b_mpll2 = {
 594         .data = &(struct clk_regmap_gate_data){
 595                 .offset = HHI_MPLL_CNTL9,
 596                 .bit_idx = 14,
 597         },
 598         .hw.init = &(struct clk_init_data){
 599                 .name = "mpll2",
 600                 .ops = &clk_regmap_gate_ops,
 601                 .parent_hws = (const struct clk_hw *[]) {
 602                         &meson8b_mpll2_div.hw
 603                 },
 604                 .num_parents = 1,
 605                 .flags = CLK_SET_RATE_PARENT,
 606         },
 607 };
 608
 609 static u32 mux_table_clk81[]    = { 6, 5, 7 };
 610 static struct clk_regmap meson8b_mpeg_clk_sel = {
 611         .data = &(struct clk_regmap_mux_data){
 612                 .offset = HHI_MPEG_CLK_CNTL,
 613                 .mask = 0x7,
 614                 .shift = 12,
 615                 .table = mux_table_clk81,
 616         },
 617         .hw.init = &(struct clk_init_data){
 618                 .name = "mpeg_clk_sel",
 619                 .ops = &clk_regmap_mux_ro_ops,
 620                 /*
 621                  * FIXME bits 14:12 selects from 8 possible parents:
 622                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
 623                  * fclk_div4, fclk_div3, fclk_div5
 624                  */
 625                 .parent_hws = (const struct clk_hw *[]) {
 626                         &meson8b_fclk_div3.hw,
 627                         &meson8b_fclk_div4.hw,
 628                         &meson8b_fclk_div5.hw,
 629                 },
 630                 .num_parents = 3,
 631         },
 632 };
 633
 634 static struct clk_regmap meson8b_mpeg_clk_div = {
 635         .data = &(struct clk_regmap_div_data){
 636                 .offset = HHI_MPEG_CLK_CNTL,
 637                 .shift = 0,
 638                 .width = 7,
 639         },
 640         .hw.init = &(struct clk_init_data){
 641                 .name = "mpeg_clk_div",
 642                 .ops = &clk_regmap_divider_ro_ops,
 643                 .parent_hws = (const struct clk_hw *[]) {
 644                         &meson8b_mpeg_clk_sel.hw
 645                 },
 646                 .num_parents = 1,
 647         },
 648 };
 649
 650 static struct clk_regmap meson8b_clk81 = {
 651         .data = &(struct clk_regmap_gate_data){
 652                 .offset = HHI_MPEG_CLK_CNTL,
 653                 .bit_idx = 7,
 654         },
 655         .hw.init = &(struct clk_init_data){
 656                 .name = "clk81",
 657                 .ops = &clk_regmap_gate_ops,
 658                 .parent_hws = (const struct clk_hw *[]) {
 659                         &meson8b_mpeg_clk_div.hw
 660                 },
 661                 .num_parents = 1,
 662                 .flags = CLK_IS_CRITICAL,
 663         },
 664 };
 665
 666 static struct clk_regmap meson8b_cpu_in_sel = {
 667         .data = &(struct clk_regmap_mux_data){
 668                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 669                 .mask = 0x1,
 670                 .shift = 0,
 671         },
 672         .hw.init = &(struct clk_init_data){
 673                 .name = "cpu_in_sel",
 674                 .ops = &clk_regmap_mux_ops,
 675                 .parent_data = (const struct clk_parent_data[]) {
 676                         { .fw_name = "xtal", .name = "xtal", .index = -1, },
 677                         { .hw = &meson8b_sys_pll.hw, },
 678                 },
 679                 .num_parents = 2,
 680                 .flags = (CLK_SET_RATE_PARENT |
 681                           CLK_SET_RATE_NO_REPARENT),
 682         },
 683 };
 684
 685 static struct clk_fixed_factor meson8b_cpu_in_div2 = {
 686         .mult = 1,
 687         .div = 2,
 688         .hw.init = &(struct clk_init_data){
 689                 .name = "cpu_in_div2",
 690                 .ops = &clk_fixed_factor_ops,
 691                 .parent_hws = (const struct clk_hw *[]) {
 692                         &meson8b_cpu_in_sel.hw
 693                 },
 694                 .num_parents = 1,
 695                 .flags = CLK_SET_RATE_PARENT,
 696         },
 697 };
 698
 699 static struct clk_fixed_factor meson8b_cpu_in_div3 = {
 700         .mult = 1,
 701         .div = 3,
 702         .hw.init = &(struct clk_init_data){
 703                 .name = "cpu_in_div3",
 704                 .ops = &clk_fixed_factor_ops,
 705                 .parent_hws = (const struct clk_hw *[]) {
 706                         &meson8b_cpu_in_sel.hw
 707                 },
 708                 .num_parents = 1,
 709                 .flags = CLK_SET_RATE_PARENT,
 710         },
 711 };
 712
 713 static const struct clk_div_table cpu_scale_table[] = {
 714         { .val = 1, .div = 4 },
 715         { .val = 2, .div = 6 },
 716         { .val = 3, .div = 8 },
 717         { .val = 4, .div = 10 },
 718         { .val = 5, .div = 12 },
 719         { .val = 6, .div = 14 },
 720         { .val = 7, .div = 16 },
 721         { .val = 8, .div = 18 },
 722         { /* sentinel */ },
 723 };
 724
 725 static struct clk_regmap meson8b_cpu_scale_div = {
 726         .data = &(struct clk_regmap_div_data){
 727                 .offset =  HHI_SYS_CPU_CLK_CNTL1,
 728                 .shift = 20,
 729                 .width = 10,
 730                 .table = cpu_scale_table,
 731                 .flags = CLK_DIVIDER_ALLOW_ZERO,
 732         },
 733         .hw.init = &(struct clk_init_data){
 734                 .name = "cpu_scale_div",
 735                 .ops = &clk_regmap_divider_ops,
 736                 .parent_hws = (const struct clk_hw *[]) {
 737                         &meson8b_cpu_in_sel.hw
 738                 },
 739                 .num_parents = 1,
 740                 .flags = CLK_SET_RATE_PARENT,
 741         },
 742 };
 743
 744 static u32 mux_table_cpu_scale_out_sel[] = { 0, 1, 3 };
 745 static struct clk_regmap meson8b_cpu_scale_out_sel = {
 746         .data = &(struct clk_regmap_mux_data){
 747                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 748                 .mask = 0x3,
 749                 .shift = 2,
 750                 .table = mux_table_cpu_scale_out_sel,
 751         },
 752         .hw.init = &(struct clk_init_data){
 753                 .name = "cpu_scale_out_sel",
 754                 .ops = &clk_regmap_mux_ops,
 755                 /*
 756                  * NOTE: We are skipping the parent with value 0x2 (which is
 757                  * meson8b_cpu_in_div3) because it results in a duty cycle of
 758                  * 33% which makes the system unstable and can result in a
 759                  * lockup of the whole system.
 760                  */
 761                 .parent_hws = (const struct clk_hw *[]) {
 762                         &meson8b_cpu_in_sel.hw,
 763                         &meson8b_cpu_in_div2.hw,
 764                         &meson8b_cpu_scale_div.hw,
 765                 },
 766                 .num_parents = 3,
 767                 .flags = CLK_SET_RATE_PARENT,
 768         },
 769 };
 770
 771 static struct clk_regmap meson8b_cpu_clk = {
 772         .data = &(struct clk_regmap_mux_data){
 773                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 774                 .mask = 0x1,
 775                 .shift = 7,
 776         },
 777         .hw.init = &(struct clk_init_data){
 778                 .name = "cpu_clk",
 779                 .ops = &clk_regmap_mux_ops,
 780                 .parent_data = (const struct clk_parent_data[]) {
 781                         { .fw_name = "xtal", .name = "xtal", .index = -1, },
 782                         { .hw = &meson8b_cpu_scale_out_sel.hw, },
 783                 },
 784                 .num_parents = 2,
 785                 .flags = (CLK_SET_RATE_PARENT |
 786                           CLK_SET_RATE_NO_REPARENT |
 787                           CLK_IS_CRITICAL),
 788         },
 789 };
 790
 791 static struct clk_regmap meson8b_nand_clk_sel = {
 792         .data = &(struct clk_regmap_mux_data){
 793                 .offset = HHI_NAND_CLK_CNTL,
 794                 .mask = 0x7,
 795                 .shift = 9,
 796                 .flags = CLK_MUX_ROUND_CLOSEST,
 797         },
 798         .hw.init = &(struct clk_init_data){
 799                 .name = "nand_clk_sel",
 800                 .ops = &clk_regmap_mux_ops,
 801                 /* FIXME all other parents are unknown: */
 802                 .parent_data = (const struct clk_parent_data[]) {
 803                         { .hw = &meson8b_fclk_div4.hw, },
 804                         { .hw = &meson8b_fclk_div3.hw, },
 805                         { .hw = &meson8b_fclk_div5.hw, },
 806                         { .hw = &meson8b_fclk_div7.hw, },
 807                         { .fw_name = "xtal", .name = "xtal", .index = -1, },
 808                 },
 809                 .num_parents = 5,
 810                 .flags = CLK_SET_RATE_PARENT,
 811         },
 812 };
 813
 814 static struct clk_regmap meson8b_nand_clk_div = {
 815         .data = &(struct clk_regmap_div_data){
 816                 .offset =  HHI_NAND_CLK_CNTL,
 817                 .shift = 0,
 818                 .width = 7,
 819                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
 820         },
 821         .hw.init = &(struct clk_init_data){
 822                 .name = "nand_clk_div",
 823                 .ops = &clk_regmap_divider_ops,
 824                 .parent_hws = (const struct clk_hw *[]) {
 825                         &meson8b_nand_clk_sel.hw
 826                 },
 827                 .num_parents = 1,
 828                 .flags = CLK_SET_RATE_PARENT,
 829         },
 830 };
 831
 832 static struct clk_regmap meson8b_nand_clk_gate = {
 833         .data = &(struct clk_regmap_gate_data){
 834                 .offset = HHI_NAND_CLK_CNTL,
 835                 .bit_idx = 8,
 836         },
 837         .hw.init = &(struct clk_init_data){
 838                 .name = "nand_clk_gate",
 839                 .ops = &clk_regmap_gate_ops,
 840                 .parent_hws = (const struct clk_hw *[]) {
 841                         &meson8b_nand_clk_div.hw
 842                 },
 843                 .num_parents = 1,
 844                 .flags = CLK_SET_RATE_PARENT,
 845         },
 846 };
 847
 848 static struct clk_fixed_factor meson8b_cpu_clk_div2 = {
 849         .mult = 1,
 850         .div = 2,
 851         .hw.init = &(struct clk_init_data){
 852                 .name = "cpu_clk_div2",
 853                 .ops = &clk_fixed_factor_ops,
 854                 .parent_hws = (const struct clk_hw *[]) {
 855                         &meson8b_cpu_clk.hw
 856                 },
 857                 .num_parents = 1,
 858         },
 859 };
 860
 861 static struct clk_fixed_factor meson8b_cpu_clk_div3 = {
 862         .mult = 1,
 863         .div = 3,
 864         .hw.init = &(struct clk_init_data){
 865                 .name = "cpu_clk_div3",
 866                 .ops = &clk_fixed_factor_ops,
 867                 .parent_hws = (const struct clk_hw *[]) {
 868                         &meson8b_cpu_clk.hw
 869                 },
 870                 .num_parents = 1,
 871         },
 872 };
 873
 874 static struct clk_fixed_factor meson8b_cpu_clk_div4 = {
 875         .mult = 1,
 876         .div = 4,
 877         .hw.init = &(struct clk_init_data){
 878                 .name = "cpu_clk_div4",
 879                 .ops = &clk_fixed_factor_ops,
 880                 .parent_hws = (const struct clk_hw *[]) {
 881                         &meson8b_cpu_clk.hw
 882                 },
 883                 .num_parents = 1,
 884         },
 885 };
 886
 887 static struct clk_fixed_factor meson8b_cpu_clk_div5 = {
 888         .mult = 1,
 889         .div = 5,
 890         .hw.init = &(struct clk_init_data){
 891                 .name = "cpu_clk_div5",
 892                 .ops = &clk_fixed_factor_ops,
 893                 .parent_hws = (const struct clk_hw *[]) {
 894                         &meson8b_cpu_clk.hw
 895                 },
 896                 .num_parents = 1,
 897         },
 898 };
 899
 900 static struct clk_fixed_factor meson8b_cpu_clk_div6 = {
 901         .mult = 1,
 902         .div = 6,
 903         .hw.init = &(struct clk_init_data){
 904                 .name = "cpu_clk_div6",
 905                 .ops = &clk_fixed_factor_ops,
 906                 .parent_hws = (const struct clk_hw *[]) {
 907                         &meson8b_cpu_clk.hw
 908                 },
 909                 .num_parents = 1,
 910         },
 911 };
 912
 913 static struct clk_fixed_factor meson8b_cpu_clk_div7 = {
 914         .mult = 1,
 915         .div = 7,
 916         .hw.init = &(struct clk_init_data){
 917                 .name = "cpu_clk_div7",
 918                 .ops = &clk_fixed_factor_ops,
 919                 .parent_hws = (const struct clk_hw *[]) {
 920                         &meson8b_cpu_clk.hw
 921                 },
 922                 .num_parents = 1,
 923         },
 924 };
 925
 926 static struct clk_fixed_factor meson8b_cpu_clk_div8 = {
 927         .mult = 1,
 928         .div = 8,
 929         .hw.init = &(struct clk_init_data){
 930                 .name = "cpu_clk_div8",
 931                 .ops = &clk_fixed_factor_ops,
 932                 .parent_hws = (const struct clk_hw *[]) {
 933                         &meson8b_cpu_clk.hw
 934                 },
 935                 .num_parents = 1,
 936         },
 937 };
 938
 939 static u32 mux_table_apb[] = { 1, 2, 3, 4, 5, 6, 7 };
 940 static struct clk_regmap meson8b_apb_clk_sel = {
 941         .data = &(struct clk_regmap_mux_data){
 942                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 943                 .mask = 0x7,
 944                 .shift = 3,
 945                 .table = mux_table_apb,
 946         },
 947         .hw.init = &(struct clk_init_data){
 948                 .name = "apb_clk_sel",
 949                 .ops = &clk_regmap_mux_ops,
 950                 .parent_hws = (const struct clk_hw *[]) {
 951                         &meson8b_cpu_clk_div2.hw,
 952                         &meson8b_cpu_clk_div3.hw,
 953                         &meson8b_cpu_clk_div4.hw,
 954                         &meson8b_cpu_clk_div5.hw,
 955                         &meson8b_cpu_clk_div6.hw,
 956                         &meson8b_cpu_clk_div7.hw,
 957                         &meson8b_cpu_clk_div8.hw,
 958                 },
 959                 .num_parents = 7,
 960         },
 961 };
 962
 963 static struct clk_regmap meson8b_apb_clk_gate = {
 964         .data = &(struct clk_regmap_gate_data){
 965                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 966                 .bit_idx = 16,
 967                 .flags = CLK_GATE_SET_TO_DISABLE,
 968         },
 969         .hw.init = &(struct clk_init_data){
 970                 .name = "apb_clk_dis",
 971                 .ops = &clk_regmap_gate_ro_ops,
 972                 .parent_hws = (const struct clk_hw *[]) {
 973                         &meson8b_apb_clk_sel.hw
 974                 },
 975                 .num_parents = 1,
 976                 .flags = CLK_SET_RATE_PARENT,
 977         },
 978 };
 979
 980 static struct clk_regmap meson8b_periph_clk_sel = {
 981         .data = &(struct clk_regmap_mux_data){
 982                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 983                 .mask = 0x7,
 984                 .shift = 6,
 985         },
 986         .hw.init = &(struct clk_init_data){
 987                 .name = "periph_clk_sel",
 988                 .ops = &clk_regmap_mux_ops,
 989                 .parent_hws = (const struct clk_hw *[]) {
 990                         &meson8b_cpu_clk_div2.hw,
 991                         &meson8b_cpu_clk_div3.hw,
 992                         &meson8b_cpu_clk_div4.hw,
 993                         &meson8b_cpu_clk_div5.hw,
 994                         &meson8b_cpu_clk_div6.hw,
 995                         &meson8b_cpu_clk_div7.hw,
 996                         &meson8b_cpu_clk_div8.hw,
 997                 },
 998                 .num_parents = 7,
 999         },
1000 };
1001
1002 static struct clk_regmap meson8b_periph_clk_gate = {
1003         .data = &(struct clk_regmap_gate_data){
1004                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1005                 .bit_idx = 17,
1006                 .flags = CLK_GATE_SET_TO_DISABLE,
1007         },
1008         .hw.init = &(struct clk_init_data){
1009                 .name = "periph_clk_dis",
1010                 .ops = &clk_regmap_gate_ro_ops,
1011                 .parent_hws = (const struct clk_hw *[]) {
1012                         &meson8b_periph_clk_sel.hw
1013                 },
1014                 .num_parents = 1,
1015                 .flags = CLK_SET_RATE_PARENT,
1016         },
1017 };
1018
1019 static u32 mux_table_axi[] = { 1, 2, 3, 4, 5, 6, 7 };
1020 static struct clk_regmap meson8b_axi_clk_sel = {
1021         .data = &(struct clk_regmap_mux_data){
1022                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1023                 .mask = 0x7,
1024                 .shift = 9,
1025                 .table = mux_table_axi,
1026         },
1027         .hw.init = &(struct clk_init_data){
1028                 .name = "axi_clk_sel",
1029                 .ops = &clk_regmap_mux_ops,
1030                 .parent_hws = (const struct clk_hw *[]) {
1031                         &meson8b_cpu_clk_div2.hw,
1032                         &meson8b_cpu_clk_div3.hw,
1033                         &meson8b_cpu_clk_div4.hw,
1034                         &meson8b_cpu_clk_div5.hw,
1035                         &meson8b_cpu_clk_div6.hw,
1036                         &meson8b_cpu_clk_div7.hw,
1037                         &meson8b_cpu_clk_div8.hw,
1038                 },
1039                 .num_parents = 7,
1040         },
1041 };
1042
1043 static struct clk_regmap meson8b_axi_clk_gate = {
1044         .data = &(struct clk_regmap_gate_data){
1045                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1046                 .bit_idx = 18,
1047                 .flags = CLK_GATE_SET_TO_DISABLE,
1048         },
1049         .hw.init = &(struct clk_init_data){
1050                 .name = "axi_clk_dis",
1051                 .ops = &clk_regmap_gate_ro_ops,
1052                 .parent_hws = (const struct clk_hw *[]) {
1053                         &meson8b_axi_clk_sel.hw
1054                 },
1055                 .num_parents = 1,
1056                 .flags = CLK_SET_RATE_PARENT,
1057         },
1058 };
1059
1060 static struct clk_regmap meson8b_l2_dram_clk_sel = {
1061         .data = &(struct clk_regmap_mux_data){
1062                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1063                 .mask = 0x7,
1064                 .shift = 12,
1065         },
1066         .hw.init = &(struct clk_init_data){
1067                 .name = "l2_dram_clk_sel",
1068                 .ops = &clk_regmap_mux_ops,
1069                 .parent_hws = (const struct clk_hw *[]) {
1070                         &meson8b_cpu_clk_div2.hw,
1071                         &meson8b_cpu_clk_div3.hw,
1072                         &meson8b_cpu_clk_div4.hw,
1073                         &meson8b_cpu_clk_div5.hw,
1074                         &meson8b_cpu_clk_div6.hw,
1075                         &meson8b_cpu_clk_div7.hw,
1076                         &meson8b_cpu_clk_div8.hw,
1077                 },
1078                 .num_parents = 7,
1079         },
1080 };
1081
1082 static struct clk_regmap meson8b_l2_dram_clk_gate = {
1083         .data = &(struct clk_regmap_gate_data){
1084                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1085                 .bit_idx = 19,
1086                 .flags = CLK_GATE_SET_TO_DISABLE,
1087         },
1088         .hw.init = &(struct clk_init_data){
1089                 .name = "l2_dram_clk_dis",
1090                 .ops = &clk_regmap_gate_ro_ops,
1091                 .parent_hws = (const struct clk_hw *[]) {
1092                         &meson8b_l2_dram_clk_sel.hw
1093                 },
1094                 .num_parents = 1,
1095                 .flags = CLK_SET_RATE_PARENT,
1096         },
1097 };
1098
1099 /* also called LVDS_CLK_EN */
1100 static struct clk_regmap meson8b_vid_pll_lvds_en = {
1101         .data = &(struct clk_regmap_gate_data){
1102                 .offset = HHI_VID_DIVIDER_CNTL,
1103                 .bit_idx = 11,
1104         },
1105         .hw.init = &(struct clk_init_data){
1106                 .name = "vid_pll_lvds_en",
1107                 .ops = &clk_regmap_gate_ops,
1108                 .parent_hws = (const struct clk_hw *[]) {
1109                         &meson8b_hdmi_pll_lvds_out.hw
1110                 },
1111                 .num_parents = 1,
1112                 .flags = CLK_SET_RATE_PARENT,
1113         },
1114 };
1115
1116 static struct clk_regmap meson8b_vid_pll_in_sel = {
1117         .data = &(struct clk_regmap_mux_data){
1118                 .offset = HHI_VID_DIVIDER_CNTL,
1119                 .mask = 0x1,
1120                 .shift = 15,
1121         },
1122         .hw.init = &(struct clk_init_data){
1123                 .name = "vid_pll_in_sel",
1124                 .ops = &clk_regmap_mux_ops,
1125                 /*
1126                  * TODO: depending on the SoC there is also a second parent:
1127                  * Meson8: unknown
1128                  * Meson8b: hdmi_pll_dco
1129                  * Meson8m2: vid2_pll
1130                  */
1131                 .parent_hws = (const struct clk_hw *[]) {
1132                         &meson8b_vid_pll_lvds_en.hw
1133                 },
1134                 .num_parents = 1,
1135                 .flags = CLK_SET_RATE_PARENT,
1136         },
1137 };
1138
1139 static struct clk_regmap meson8b_vid_pll_in_en = {
1140         .data = &(struct clk_regmap_gate_data){
1141                 .offset = HHI_VID_DIVIDER_CNTL,
1142                 .bit_idx = 16,
1143         },
1144         .hw.init = &(struct clk_init_data){
1145                 .name = "vid_pll_in_en",
1146                 .ops = &clk_regmap_gate_ops,
1147                 .parent_hws = (const struct clk_hw *[]) {
1148                         &meson8b_vid_pll_in_sel.hw
1149                 },
1150                 .num_parents = 1,
1151                 .flags = CLK_SET_RATE_PARENT,
1152         },
1153 };
1154
1155 static struct clk_regmap meson8b_vid_pll_pre_div = {
1156         .data = &(struct clk_regmap_div_data){
1157                 .offset =  HHI_VID_DIVIDER_CNTL,
1158                 .shift = 4,
1159                 .width = 3,
1160         },
1161         .hw.init = &(struct clk_init_data){
1162                 .name = "vid_pll_pre_div",
1163                 .ops = &clk_regmap_divider_ops,
1164                 .parent_hws = (const struct clk_hw *[]) {
1165                         &meson8b_vid_pll_in_en.hw
1166                 },
1167                 .num_parents = 1,
1168                 .flags = CLK_SET_RATE_PARENT,
1169         },
1170 };
1171
1172 static struct clk_regmap meson8b_vid_pll_post_div = {
1173         .data = &(struct clk_regmap_div_data){
1174                 .offset =  HHI_VID_DIVIDER_CNTL,
1175                 .shift = 12,
1176                 .width = 3,
1177         },
1178         .hw.init = &(struct clk_init_data){
1179                 .name = "vid_pll_post_div",
1180                 .ops = &clk_regmap_divider_ops,
1181                 .parent_hws = (const struct clk_hw *[]) {
1182                         &meson8b_vid_pll_pre_div.hw
1183                 },
1184                 .num_parents = 1,
1185                 .flags = CLK_SET_RATE_PARENT,
1186         },
1187 };
1188
1189 static struct clk_regmap meson8b_vid_pll = {
1190         .data = &(struct clk_regmap_mux_data){
1191                 .offset = HHI_VID_DIVIDER_CNTL,
1192                 .mask = 0x3,
1193                 .shift = 8,
1194         },
1195         .hw.init = &(struct clk_init_data){
1196                 .name = "vid_pll",
1197                 .ops = &clk_regmap_mux_ops,
1198                 /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */
1199                 .parent_hws = (const struct clk_hw *[]) {
1200                         &meson8b_vid_pll_pre_div.hw,
1201                         &meson8b_vid_pll_post_div.hw,
1202                 },
1203                 .num_parents = 2,
1204                 .flags = CLK_SET_RATE_PARENT,
1205         },
1206 };
1207
1208 static struct clk_regmap meson8b_vid_pll_final_div = {
1209         .data = &(struct clk_regmap_div_data){
1210                 .offset =  HHI_VID_CLK_DIV,
1211                 .shift = 0,
1212                 .width = 8,
1213         },
1214         .hw.init = &(struct clk_init_data){
1215                 .name = "vid_pll_final_div",
1216                 .ops = &clk_regmap_divider_ops,
1217                 .parent_hws = (const struct clk_hw *[]) {
1218                         &meson8b_vid_pll.hw
1219                 },
1220                 .num_parents = 1,
1221                 .flags = CLK_SET_RATE_PARENT,
1222         },
1223 };
1224
1225 static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = {
1226         &meson8b_vid_pll_final_div.hw,
1227         &meson8b_fclk_div4.hw,
1228         &meson8b_fclk_div3.hw,
1229         &meson8b_fclk_div5.hw,
1230         &meson8b_vid_pll_final_div.hw,
1231         &meson8b_fclk_div7.hw,
1232         &meson8b_mpll1.hw,
1233 };
1234
1235 static struct clk_regmap meson8b_vclk_in_sel = {
1236         .data = &(struct clk_regmap_mux_data){
1237                 .offset = HHI_VID_CLK_CNTL,
1238                 .mask = 0x7,
1239                 .shift = 16,
1240         },
1241         .hw.init = &(struct clk_init_data){
1242                 .name = "vclk_in_sel",
1243                 .ops = &clk_regmap_mux_ops,
1244                 .parent_hws = meson8b_vclk_mux_parent_hws,
1245                 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
1246                 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1247         },
1248 };
1249
1250 static struct clk_regmap meson8b_vclk_in_en = {
1251         .data = &(struct clk_regmap_gate_data){
1252                 .offset = HHI_VID_CLK_DIV,
1253                 .bit_idx = 16,
1254         },
1255         .hw.init = &(struct clk_init_data){
1256                 .name = "vclk_in_en",
1257                 .ops = &clk_regmap_gate_ops,
1258                 .parent_hws = (const struct clk_hw *[]) {
1259                         &meson8b_vclk_in_sel.hw
1260                 },
1261                 .num_parents = 1,
1262                 .flags = CLK_SET_RATE_PARENT,
1263         },
1264 };
1265
1266 static struct clk_regmap meson8b_vclk_en = {
1267         .data = &(struct clk_regmap_gate_data){
1268                 .offset = HHI_VID_CLK_CNTL,
1269                 .bit_idx = 19,
1270         },
1271         .hw.init = &(struct clk_init_data){
1272                 .name = "vclk_en",
1273                 .ops = &clk_regmap_gate_ops,
1274                 .parent_hws = (const struct clk_hw *[]) {
1275                         &meson8b_vclk_in_en.hw
1276                 },
1277                 .num_parents = 1,
1278                 .flags = CLK_SET_RATE_PARENT,
1279         },
1280 };
1281
1282 static struct clk_regmap meson8b_vclk_div1_gate = {
1283         .data = &(struct clk_regmap_gate_data){
1284                 .offset = HHI_VID_CLK_CNTL,
1285                 .bit_idx = 0,
1286         },
1287         .hw.init = &(struct clk_init_data){
1288                 .name = "vclk_div1_en",
1289                 .ops = &clk_regmap_gate_ops,
1290                 .parent_hws = (const struct clk_hw *[]) {
1291                         &meson8b_vclk_en.hw
1292                 },
1293                 .num_parents = 1,
1294                 .flags = CLK_SET_RATE_PARENT,
1295         },
1296 };
1297
1298 static struct clk_fixed_factor meson8b_vclk_div2_div = {
1299         .mult = 1,
1300         .div = 2,
1301         .hw.init = &(struct clk_init_data){
1302                 .name = "vclk_div2",
1303                 .ops = &clk_fixed_factor_ops,
1304                 .parent_hws = (const struct clk_hw *[]) {
1305                         &meson8b_vclk_en.hw
1306                 },
1307                 .num_parents = 1,
1308                 .flags = CLK_SET_RATE_PARENT,
1309         }
1310 };
1311
1312 static struct clk_regmap meson8b_vclk_div2_div_gate = {
1313         .data = &(struct clk_regmap_gate_data){
1314                 .offset = HHI_VID_CLK_CNTL,
1315                 .bit_idx = 1,
1316         },
1317         .hw.init = &(struct clk_init_data){
1318                 .name = "vclk_div2_en",
1319                 .ops = &clk_regmap_gate_ops,
1320                 .parent_hws = (const struct clk_hw *[]) {
1321                         &meson8b_vclk_div2_div.hw
1322                 },
1323                 .num_parents = 1,
1324                 .flags = CLK_SET_RATE_PARENT,
1325         },
1326 };
1327
1328 static struct clk_fixed_factor meson8b_vclk_div4_div = {
1329         .mult = 1,
1330         .div = 4,
1331         .hw.init = &(struct clk_init_data){
1332                 .name = "vclk_div4",
1333                 .ops = &clk_fixed_factor_ops,
1334                 .parent_hws = (const struct clk_hw *[]) {
1335                         &meson8b_vclk_en.hw
1336                 },
1337                 .num_parents = 1,
1338                 .flags = CLK_SET_RATE_PARENT,
1339         }
1340 };
1341
1342 static struct clk_regmap meson8b_vclk_div4_div_gate = {
1343         .data = &(struct clk_regmap_gate_data){
1344                 .offset = HHI_VID_CLK_CNTL,
1345                 .bit_idx = 2,
1346         },
1347         .hw.init = &(struct clk_init_data){
1348                 .name = "vclk_div4_en",
1349                 .ops = &clk_regmap_gate_ops,
1350                 .parent_hws = (const struct clk_hw *[]) {
1351                         &meson8b_vclk_div4_div.hw
1352                 },
1353                 .num_parents = 1,
1354                 .flags = CLK_SET_RATE_PARENT,
1355         },
1356 };
1357
1358 static struct clk_fixed_factor meson8b_vclk_div6_div = {
1359         .mult = 1,
1360         .div = 6,
1361         .hw.init = &(struct clk_init_data){
1362                 .name = "vclk_div6",
1363                 .ops = &clk_fixed_factor_ops,
1364                 .parent_hws = (const struct clk_hw *[]) {
1365                         &meson8b_vclk_en.hw
1366                 },
1367                 .num_parents = 1,
1368                 .flags = CLK_SET_RATE_PARENT,
1369         }
1370 };
1371
1372 static struct clk_regmap meson8b_vclk_div6_div_gate = {
1373         .data = &(struct clk_regmap_gate_data){
1374                 .offset = HHI_VID_CLK_CNTL,
1375                 .bit_idx = 3,
1376         },
1377         .hw.init = &(struct clk_init_data){
1378                 .name = "vclk_div6_en",
1379                 .ops = &clk_regmap_gate_ops,
1380                 .parent_hws = (const struct clk_hw *[]) {
1381                         &meson8b_vclk_div6_div.hw
1382                 },
1383                 .num_parents = 1,
1384                 .flags = CLK_SET_RATE_PARENT,
1385         },
1386 };
1387
1388 static struct clk_fixed_factor meson8b_vclk_div12_div = {
1389         .mult = 1,
1390         .div = 12,
1391         .hw.init = &(struct clk_init_data){
1392                 .name = "vclk_div12",
1393                 .ops = &clk_fixed_factor_ops,
1394                 .parent_hws = (const struct clk_hw *[]) {
1395                         &meson8b_vclk_en.hw
1396                 },
1397                 .num_parents = 1,
1398                 .flags = CLK_SET_RATE_PARENT,
1399         }
1400 };
1401
1402 static struct clk_regmap meson8b_vclk_div12_div_gate = {
1403         .data = &(struct clk_regmap_gate_data){
1404                 .offset = HHI_VID_CLK_CNTL,
1405                 .bit_idx = 4,
1406         },
1407         .hw.init = &(struct clk_init_data){
1408                 .name = "vclk_div12_en",
1409                 .ops = &clk_regmap_gate_ops,
1410                 .parent_hws = (const struct clk_hw *[]) {
1411                         &meson8b_vclk_div12_div.hw
1412                 },
1413                 .num_parents = 1,
1414                 .flags = CLK_SET_RATE_PARENT,
1415         },
1416 };
1417
1418 static struct clk_regmap meson8b_vclk2_in_sel = {
1419         .data = &(struct clk_regmap_mux_data){
1420                 .offset = HHI_VIID_CLK_CNTL,
1421                 .mask = 0x7,
1422                 .shift = 16,
1423         },
1424         .hw.init = &(struct clk_init_data){
1425                 .name = "vclk2_in_sel",
1426                 .ops = &clk_regmap_mux_ops,
1427                 .parent_hws = meson8b_vclk_mux_parent_hws,
1428                 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
1429                 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1430         },
1431 };
1432
1433 static struct clk_regmap meson8b_vclk2_clk_in_en = {
1434         .data = &(struct clk_regmap_gate_data){
1435                 .offset = HHI_VIID_CLK_DIV,
1436                 .bit_idx = 16,
1437         },
1438         .hw.init = &(struct clk_init_data){
1439                 .name = "vclk2_in_en",
1440                 .ops = &clk_regmap_gate_ops,
1441                 .parent_hws = (const struct clk_hw *[]) {
1442                         &meson8b_vclk2_in_sel.hw
1443                 },
1444                 .num_parents = 1,
1445                 .flags = CLK_SET_RATE_PARENT,
1446         },
1447 };
1448
1449 static struct clk_regmap meson8b_vclk2_clk_en = {
1450         .data = &(struct clk_regmap_gate_data){
1451                 .offset = HHI_VIID_CLK_DIV,
1452                 .bit_idx = 19,
1453         },
1454         .hw.init = &(struct clk_init_data){
1455                 .name = "vclk2_en",
1456                 .ops = &clk_regmap_gate_ops,
1457                 .parent_hws = (const struct clk_hw *[]) {
1458                         &meson8b_vclk2_clk_in_en.hw
1459                 },
1460                 .num_parents = 1,
1461                 .flags = CLK_SET_RATE_PARENT,
1462         },
1463 };
1464
1465 static struct clk_regmap meson8b_vclk2_div1_gate = {
1466         .data = &(struct clk_regmap_gate_data){
1467                 .offset = HHI_VIID_CLK_DIV,
1468                 .bit_idx = 0,
1469         },
1470         .hw.init = &(struct clk_init_data){
1471                 .name = "vclk2_div1_en",
1472                 .ops = &clk_regmap_gate_ops,
1473                 .parent_hws = (const struct clk_hw *[]) {
1474                         &meson8b_vclk2_clk_en.hw
1475                 },
1476                 .num_parents = 1,
1477                 .flags = CLK_SET_RATE_PARENT,
1478         },
1479 };
1480
1481 static struct clk_fixed_factor meson8b_vclk2_div2_div = {
1482         .mult = 1,
1483         .div = 2,
1484         .hw.init = &(struct clk_init_data){
1485                 .name = "vclk2_div2",
1486                 .ops = &clk_fixed_factor_ops,
1487                 .parent_hws = (const struct clk_hw *[]) {
1488                         &meson8b_vclk2_clk_en.hw
1489                 },
1490                 .num_parents = 1,
1491                 .flags = CLK_SET_RATE_PARENT,
1492         }
1493 };
1494
1495 static struct clk_regmap meson8b_vclk2_div2_div_gate = {
1496         .data = &(struct clk_regmap_gate_data){
1497                 .offset = HHI_VIID_CLK_DIV,
1498                 .bit_idx = 1,
1499         },
1500         .hw.init = &(struct clk_init_data){
1501                 .name = "vclk2_div2_en",
1502                 .ops = &clk_regmap_gate_ops,
1503                 .parent_hws = (const struct clk_hw *[]) {
1504                         &meson8b_vclk2_div2_div.hw
1505                 },
1506                 .num_parents = 1,
1507                 .flags = CLK_SET_RATE_PARENT,
1508         },
1509 };
1510
1511 static struct clk_fixed_factor meson8b_vclk2_div4_div = {
1512         .mult = 1,
1513         .div = 4,
1514         .hw.init = &(struct clk_init_data){
1515                 .name = "vclk2_div4",
1516                 .ops = &clk_fixed_factor_ops,
1517                 .parent_hws = (const struct clk_hw *[]) {
1518                         &meson8b_vclk2_clk_en.hw
1519                 },
1520                 .num_parents = 1,
1521                 .flags = CLK_SET_RATE_PARENT,
1522         }
1523 };
1524
1525 static struct clk_regmap meson8b_vclk2_div4_div_gate = {
1526         .data = &(struct clk_regmap_gate_data){
1527                 .offset = HHI_VIID_CLK_DIV,
1528                 .bit_idx = 2,
1529         },
1530         .hw.init = &(struct clk_init_data){
1531                 .name = "vclk2_div4_en",
1532                 .ops = &clk_regmap_gate_ops,
1533                 .parent_hws = (const struct clk_hw *[]) {
1534                         &meson8b_vclk2_div4_div.hw
1535                 },
1536                 .num_parents = 1,
1537                 .flags = CLK_SET_RATE_PARENT,
1538         },
1539 };
1540
1541 static struct clk_fixed_factor meson8b_vclk2_div6_div = {
1542         .mult = 1,
1543         .div = 6,
1544         .hw.init = &(struct clk_init_data){
1545                 .name = "vclk2_div6",
1546                 .ops = &clk_fixed_factor_ops,
1547                 .parent_hws = (const struct clk_hw *[]) {
1548                         &meson8b_vclk2_clk_en.hw
1549                 },
1550                 .num_parents = 1,
1551                 .flags = CLK_SET_RATE_PARENT,
1552         }
1553 };
1554
1555 static struct clk_regmap meson8b_vclk2_div6_div_gate = {
1556         .data = &(struct clk_regmap_gate_data){
1557                 .offset = HHI_VIID_CLK_DIV,
1558                 .bit_idx = 3,
1559         },
1560         .hw.init = &(struct clk_init_data){
1561                 .name = "vclk2_div6_en",
1562                 .ops = &clk_regmap_gate_ops,
1563                 .parent_hws = (const struct clk_hw *[]) {
1564                         &meson8b_vclk2_div6_div.hw
1565                 },
1566                 .num_parents = 1,
1567                 .flags = CLK_SET_RATE_PARENT,
1568         },
1569 };
1570
1571 static struct clk_fixed_factor meson8b_vclk2_div12_div = {
1572         .mult = 1,
1573         .div = 12,
1574         .hw.init = &(struct clk_init_data){
1575                 .name = "vclk2_div12",
1576                 .ops = &clk_fixed_factor_ops,
1577                 .parent_hws = (const struct clk_hw *[]) {
1578                         &meson8b_vclk2_clk_en.hw
1579                 },
1580                 .num_parents = 1,
1581                 .flags = CLK_SET_RATE_PARENT,
1582         }
1583 };
1584
1585 static struct clk_regmap meson8b_vclk2_div12_div_gate = {
1586         .data = &(struct clk_regmap_gate_data){
1587                 .offset = HHI_VIID_CLK_DIV,
1588                 .bit_idx = 4,
1589         },
1590         .hw.init = &(struct clk_init_data){
1591                 .name = "vclk2_div12_en",
1592                 .ops = &clk_regmap_gate_ops,
1593                 .parent_hws = (const struct clk_hw *[]) {
1594                         &meson8b_vclk2_div12_div.hw
1595                 },
1596                 .num_parents = 1,
1597                 .flags = CLK_SET_RATE_PARENT,
1598         },
1599 };
1600
1601 static const struct clk_hw *meson8b_vclk_enc_mux_parent_hws[] = {
1602         &meson8b_vclk_div1_gate.hw,
1603         &meson8b_vclk_div2_div_gate.hw,
1604         &meson8b_vclk_div4_div_gate.hw,
1605         &meson8b_vclk_div6_div_gate.hw,
1606         &meson8b_vclk_div12_div_gate.hw,
1607 };
1608
1609 static struct clk_regmap meson8b_cts_enct_sel = {
1610         .data = &(struct clk_regmap_mux_data){
1611                 .offset = HHI_VID_CLK_DIV,
1612                 .mask = 0xf,
1613                 .shift = 20,
1614         },
1615         .hw.init = &(struct clk_init_data){
1616                 .name = "cts_enct_sel",
1617                 .ops = &clk_regmap_mux_ops,
1618                 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1619                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1620                 .flags = CLK_SET_RATE_PARENT,
1621         },
1622 };
1623
1624 static struct clk_regmap meson8b_cts_enct = {
1625         .data = &(struct clk_regmap_gate_data){
1626                 .offset = HHI_VID_CLK_CNTL2,
1627                 .bit_idx = 1,
1628         },
1629         .hw.init = &(struct clk_init_data){
1630                 .name = "cts_enct",
1631                 .ops = &clk_regmap_gate_ops,
1632                 .parent_hws = (const struct clk_hw *[]) {
1633                         &meson8b_cts_enct_sel.hw
1634                 },
1635                 .num_parents = 1,
1636                 .flags = CLK_SET_RATE_PARENT,
1637         },
1638 };
1639
1640 static struct clk_regmap meson8b_cts_encp_sel = {
1641         .data = &(struct clk_regmap_mux_data){
1642                 .offset = HHI_VID_CLK_DIV,
1643                 .mask = 0xf,
1644                 .shift = 24,
1645         },
1646         .hw.init = &(struct clk_init_data){
1647                 .name = "cts_encp_sel",
1648                 .ops = &clk_regmap_mux_ops,
1649                 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1650                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1651                 .flags = CLK_SET_RATE_PARENT,
1652         },
1653 };
1654
1655 static struct clk_regmap meson8b_cts_encp = {
1656         .data = &(struct clk_regmap_gate_data){
1657                 .offset = HHI_VID_CLK_CNTL2,
1658                 .bit_idx = 2,
1659         },
1660         .hw.init = &(struct clk_init_data){
1661                 .name = "cts_encp",
1662                 .ops = &clk_regmap_gate_ops,
1663                 .parent_hws = (const struct clk_hw *[]) {
1664                         &meson8b_cts_encp_sel.hw
1665                 },
1666                 .num_parents = 1,
1667                 .flags = CLK_SET_RATE_PARENT,
1668         },
1669 };
1670
1671 static struct clk_regmap meson8b_cts_enci_sel = {
1672         .data = &(struct clk_regmap_mux_data){
1673                 .offset = HHI_VID_CLK_DIV,
1674                 .mask = 0xf,
1675                 .shift = 28,
1676         },
1677         .hw.init = &(struct clk_init_data){
1678                 .name = "cts_enci_sel",
1679                 .ops = &clk_regmap_mux_ops,
1680                 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1681                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1682                 .flags = CLK_SET_RATE_PARENT,
1683         },
1684 };
1685
1686 static struct clk_regmap meson8b_cts_enci = {
1687         .data = &(struct clk_regmap_gate_data){
1688                 .offset = HHI_VID_CLK_CNTL2,
1689                 .bit_idx = 0,
1690         },
1691         .hw.init = &(struct clk_init_data){
1692                 .name = "cts_enci",
1693                 .ops = &clk_regmap_gate_ops,
1694                 .parent_hws = (const struct clk_hw *[]) {
1695                         &meson8b_cts_enci_sel.hw
1696                 },
1697                 .num_parents = 1,
1698                 .flags = CLK_SET_RATE_PARENT,
1699         },
1700 };
1701
1702 static struct clk_regmap meson8b_hdmi_tx_pixel_sel = {
1703         .data = &(struct clk_regmap_mux_data){
1704                 .offset = HHI_HDMI_CLK_CNTL,
1705                 .mask = 0xf,
1706                 .shift = 16,
1707         },
1708         .hw.init = &(struct clk_init_data){
1709                 .name = "hdmi_tx_pixel_sel",
1710                 .ops = &clk_regmap_mux_ops,
1711                 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1712                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1713                 .flags = CLK_SET_RATE_PARENT,
1714         },
1715 };
1716
1717 static struct clk_regmap meson8b_hdmi_tx_pixel = {
1718         .data = &(struct clk_regmap_gate_data){
1719                 .offset = HHI_VID_CLK_CNTL2,
1720                 .bit_idx = 5,
1721         },
1722         .hw.init = &(struct clk_init_data){
1723                 .name = "hdmi_tx_pixel",
1724                 .ops = &clk_regmap_gate_ops,
1725                 .parent_hws = (const struct clk_hw *[]) {
1726                         &meson8b_hdmi_tx_pixel_sel.hw
1727                 },
1728                 .num_parents = 1,
1729                 .flags = CLK_SET_RATE_PARENT,
1730         },
1731 };
1732
1733 static const struct clk_hw *meson8b_vclk2_enc_mux_parent_hws[] = {
1734         &meson8b_vclk2_div1_gate.hw,
1735         &meson8b_vclk2_div2_div_gate.hw,
1736         &meson8b_vclk2_div4_div_gate.hw,
1737         &meson8b_vclk2_div6_div_gate.hw,
1738         &meson8b_vclk2_div12_div_gate.hw,
1739 };
1740
1741 static struct clk_regmap meson8b_cts_encl_sel = {
1742         .data = &(struct clk_regmap_mux_data){
1743                 .offset = HHI_VIID_CLK_DIV,
1744                 .mask = 0xf,
1745                 .shift = 12,
1746         },
1747         .hw.init = &(struct clk_init_data){
1748                 .name = "cts_encl_sel",
1749                 .ops = &clk_regmap_mux_ops,
1750                 .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
1751                 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
1752                 .flags = CLK_SET_RATE_PARENT,
1753         },
1754 };
1755
1756 static struct clk_regmap meson8b_cts_encl = {
1757         .data = &(struct clk_regmap_gate_data){
1758                 .offset = HHI_VID_CLK_CNTL2,
1759                 .bit_idx = 3,
1760         },
1761         .hw.init = &(struct clk_init_data){
1762                 .name = "cts_encl",
1763                 .ops = &clk_regmap_gate_ops,
1764                 .parent_hws = (const struct clk_hw *[]) {
1765                         &meson8b_cts_encl_sel.hw
1766                 },
1767                 .num_parents = 1,
1768                 .flags = CLK_SET_RATE_PARENT,
1769         },
1770 };
1771
1772 static struct clk_regmap meson8b_cts_vdac0_sel = {
1773         .data = &(struct clk_regmap_mux_data){
1774                 .offset = HHI_VIID_CLK_DIV,
1775                 .mask = 0xf,
1776                 .shift = 28,
1777         },
1778         .hw.init = &(struct clk_init_data){
1779                 .name = "cts_vdac0_sel",
1780                 .ops = &clk_regmap_mux_ops,
1781                 .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
1782                 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
1783                 .flags = CLK_SET_RATE_PARENT,
1784         },
1785 };
1786
1787 static struct clk_regmap meson8b_cts_vdac0 = {
1788         .data = &(struct clk_regmap_gate_data){
1789                 .offset = HHI_VID_CLK_CNTL2,
1790                 .bit_idx = 4,
1791         },
1792         .hw.init = &(struct clk_init_data){
1793                 .name = "cts_vdac0",
1794                 .ops = &clk_regmap_gate_ops,
1795                 .parent_hws = (const struct clk_hw *[]) {
1796                         &meson8b_cts_vdac0_sel.hw
1797                 },
1798                 .num_parents = 1,
1799                 .flags = CLK_SET_RATE_PARENT,
1800         },
1801 };
1802
1803 static struct clk_regmap meson8b_hdmi_sys_sel = {
1804         .data = &(struct clk_regmap_mux_data){
1805                 .offset = HHI_HDMI_CLK_CNTL,
1806                 .mask = 0x3,
1807                 .shift = 9,
1808                 .flags = CLK_MUX_ROUND_CLOSEST,
1809         },
1810         .hw.init = &(struct clk_init_data){
1811                 .name = "hdmi_sys_sel",
1812                 .ops = &clk_regmap_mux_ops,
1813                 /* FIXME: all other parents are unknown */
1814                 .parent_data = &(const struct clk_parent_data) {
1815                         .fw_name = "xtal",
1816                         .name = "xtal",
1817                         .index = -1,
1818                 },
1819                 .num_parents = 1,
1820                 .flags = CLK_SET_RATE_NO_REPARENT,
1821         },
1822 };
1823
1824 static struct clk_regmap meson8b_hdmi_sys_div = {
1825         .data = &(struct clk_regmap_div_data){
1826                 .offset = HHI_HDMI_CLK_CNTL,
1827                 .shift = 0,
1828                 .width = 7,
1829         },
1830         .hw.init = &(struct clk_init_data){
1831                 .name = "hdmi_sys_div",
1832                 .ops = &clk_regmap_divider_ops,
1833                 .parent_hws = (const struct clk_hw *[]) {
1834                         &meson8b_hdmi_sys_sel.hw
1835                 },
1836                 .num_parents = 1,
1837                 .flags = CLK_SET_RATE_PARENT,
1838         },
1839 };
1840
1841 static struct clk_regmap meson8b_hdmi_sys = {
1842         .data = &(struct clk_regmap_gate_data){
1843                 .offset = HHI_HDMI_CLK_CNTL,
1844                 .bit_idx = 8,
1845         },
1846         .hw.init = &(struct clk_init_data) {
1847                 .name = "hdmi_sys",
1848                 .ops = &clk_regmap_gate_ops,
1849                 .parent_hws = (const struct clk_hw *[]) {
1850                         &meson8b_hdmi_sys_div.hw
1851                 },
1852                 .num_parents = 1,
1853                 .flags = CLK_SET_RATE_PARENT,
1854         },
1855 };
1856
1857 /*
1858  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
1859  * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
1860  * actually manage this glitch-free mux because it does top-to-bottom
1861  * updates the each clock tree and switches to the "inactive" one when
1862  * CLK_SET_RATE_GATE is set.
1863  * Meson8 only has mali_0 and no glitch-free mux.
1864  */
1865 static const struct clk_parent_data meson8b_mali_0_1_parent_data[] = {
1866         { .fw_name = "xtal", .name = "xtal", .index = -1, },
1867         { .hw = &meson8b_mpll2.hw, },
1868         { .hw = &meson8b_mpll1.hw, },
1869         { .hw = &meson8b_fclk_div7.hw, },
1870         { .hw = &meson8b_fclk_div4.hw, },
1871         { .hw = &meson8b_fclk_div3.hw, },
1872         { .hw = &meson8b_fclk_div5.hw, },
1873 };
1874
1875 static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
1876
1877 static struct clk_regmap meson8b_mali_0_sel = {
1878         .data = &(struct clk_regmap_mux_data){
1879                 .offset = HHI_MALI_CLK_CNTL,
1880                 .mask = 0x7,
1881                 .shift = 9,
1882                 .table = meson8b_mali_0_1_mux_table,
1883         },
1884         .hw.init = &(struct clk_init_data){
1885                 .name = "mali_0_sel",
1886                 .ops = &clk_regmap_mux_ops,
1887                 .parent_data = meson8b_mali_0_1_parent_data,
1888                 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data),
1889                 /*
1890                  * Don't propagate rate changes up because the only changeable
1891                  * parents are mpll1 and mpll2 but we need those for audio and
1892                  * RGMII (Ethernet). We don't want to change the audio or
1893                  * Ethernet clocks when setting the GPU frequency.
1894                  */
1895                 .flags = 0,
1896         },
1897 };
1898
1899 static struct clk_regmap meson8b_mali_0_div = {
1900         .data = &(struct clk_regmap_div_data){
1901                 .offset = HHI_MALI_CLK_CNTL,
1902                 .shift = 0,
1903                 .width = 7,
1904         },
1905         .hw.init = &(struct clk_init_data){
1906                 .name = "mali_0_div",
1907                 .ops = &clk_regmap_divider_ops,
1908                 .parent_hws = (const struct clk_hw *[]) {
1909                         &meson8b_mali_0_sel.hw
1910                 },
1911                 .num_parents = 1,
1912                 .flags = CLK_SET_RATE_PARENT,
1913         },
1914 };
1915
1916 static struct clk_regmap meson8b_mali_0 = {
1917         .data = &(struct clk_regmap_gate_data){
1918                 .offset = HHI_MALI_CLK_CNTL,
1919                 .bit_idx = 8,
1920         },
1921         .hw.init = &(struct clk_init_data){
1922                 .name = "mali_0",
1923                 .ops = &clk_regmap_gate_ops,
1924                 .parent_hws = (const struct clk_hw *[]) {
1925                         &meson8b_mali_0_div.hw
1926                 },
1927                 .num_parents = 1,
1928                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1929         },
1930 };
1931
1932 static struct clk_regmap meson8b_mali_1_sel = {
1933         .data = &(struct clk_regmap_mux_data){
1934                 .offset = HHI_MALI_CLK_CNTL,
1935                 .mask = 0x7,
1936                 .shift = 25,
1937                 .table = meson8b_mali_0_1_mux_table,
1938         },
1939         .hw.init = &(struct clk_init_data){
1940                 .name = "mali_1_sel",
1941                 .ops = &clk_regmap_mux_ops,
1942                 .parent_data = meson8b_mali_0_1_parent_data,
1943                 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data),
1944                 /*
1945                  * Don't propagate rate changes up because the only changeable
1946                  * parents are mpll1 and mpll2 but we need those for audio and
1947                  * RGMII (Ethernet). We don't want to change the audio or
1948                  * Ethernet clocks when setting the GPU frequency.
1949                  */
1950                 .flags = 0,
1951         },
1952 };
1953
1954 static struct clk_regmap meson8b_mali_1_div = {
1955         .data = &(struct clk_regmap_div_data){
1956                 .offset = HHI_MALI_CLK_CNTL,
1957                 .shift = 16,
1958                 .width = 7,
1959         },
1960         .hw.init = &(struct clk_init_data){
1961                 .name = "mali_1_div",
1962                 .ops = &clk_regmap_divider_ops,
1963                 .parent_hws = (const struct clk_hw *[]) {
1964                         &meson8b_mali_1_sel.hw
1965                 },
1966                 .num_parents = 1,
1967                 .flags = CLK_SET_RATE_PARENT,
1968         },
1969 };
1970
1971 static struct clk_regmap meson8b_mali_1 = {
1972         .data = &(struct clk_regmap_gate_data){
1973                 .offset = HHI_MALI_CLK_CNTL,
1974                 .bit_idx = 24,
1975         },
1976         .hw.init = &(struct clk_init_data){
1977                 .name = "mali_1",
1978                 .ops = &clk_regmap_gate_ops,
1979                 .parent_hws = (const struct clk_hw *[]) {
1980                         &meson8b_mali_1_div.hw
1981                 },
1982                 .num_parents = 1,
1983                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1984         },
1985 };
1986
1987 static struct clk_regmap meson8b_mali = {
1988         .data = &(struct clk_regmap_mux_data){
1989                 .offset = HHI_MALI_CLK_CNTL,
1990                 .mask = 1,
1991                 .shift = 31,
1992         },
1993         .hw.init = &(struct clk_init_data){
1994                 .name = "mali",
1995                 .ops = &clk_regmap_mux_ops,
1996                 .parent_hws = (const struct clk_hw *[]) {
1997                         &meson8b_mali_0.hw,
1998                         &meson8b_mali_1.hw,
1999                 },
2000                 .num_parents = 2,
2001                 .flags = CLK_SET_RATE_PARENT,
2002         },
2003 };
2004
2005 static const struct reg_sequence meson8m2_gp_pll_init_regs[] = {
2006         { .reg = HHI_GP_PLL_CNTL2,      .def = 0x59c88000 },
2007         { .reg = HHI_GP_PLL_CNTL3,      .def = 0xca463823 },
2008         { .reg = HHI_GP_PLL_CNTL4,      .def = 0x0286a027 },
2009         { .reg = HHI_GP_PLL_CNTL5,      .def = 0x00003000 },
2010 };
2011
2012 static const struct pll_params_table meson8m2_gp_pll_params_table[] = {
2013         PLL_PARAMS(182, 3),
2014         { /* sentinel */ },
2015 };
2016
2017 static struct clk_regmap meson8m2_gp_pll_dco = {
2018         .data = &(struct meson_clk_pll_data){
2019                 .en = {
2020                         .reg_off = HHI_GP_PLL_CNTL,
2021                         .shift   = 30,
2022                         .width   = 1,
2023                 },
2024                 .m = {
2025                         .reg_off = HHI_GP_PLL_CNTL,
2026                         .shift   = 0,
2027                         .width   = 9,
2028                 },
2029                 .n = {
2030                         .reg_off = HHI_GP_PLL_CNTL,
2031                         .shift   = 9,
2032                         .width   = 5,
2033                 },
2034                 .l = {
2035                         .reg_off = HHI_GP_PLL_CNTL,
2036                         .shift   = 31,
2037                         .width   = 1,
2038                 },
2039                 .rst = {
2040                         .reg_off = HHI_GP_PLL_CNTL,
2041                         .shift   = 29,
2042                         .width   = 1,
2043                 },
2044                 .table = meson8m2_gp_pll_params_table,
2045                 .init_regs = meson8m2_gp_pll_init_regs,
2046                 .init_count = ARRAY_SIZE(meson8m2_gp_pll_init_regs),
2047         },
2048         .hw.init = &(struct clk_init_data){
2049                 .name = "gp_pll_dco",
2050                 .ops = &meson_clk_pll_ops,
2051                 .parent_data = &(const struct clk_parent_data) {
2052                         .fw_name = "xtal",
2053                         .name = "xtal",
2054                         .index = -1,
2055                 },
2056                 .num_parents = 1,
2057         },
2058 };
2059
2060 static struct clk_regmap meson8m2_gp_pll = {
2061         .data = &(struct clk_regmap_div_data){
2062                 .offset = HHI_GP_PLL_CNTL,
2063                 .shift = 16,
2064                 .width = 2,
2065                 .flags = CLK_DIVIDER_POWER_OF_TWO,
2066         },
2067         .hw.init = &(struct clk_init_data){
2068                 .name = "gp_pll",
2069                 .ops = &clk_regmap_divider_ops,
2070                 .parent_hws = (const struct clk_hw *[]) {
2071                         &meson8m2_gp_pll_dco.hw
2072                 },
2073                 .num_parents = 1,
2074                 .flags = CLK_SET_RATE_PARENT,
2075         },
2076 };
2077
2078 static const struct clk_hw *meson8b_vpu_0_1_parent_hws[] = {
2079         &meson8b_fclk_div4.hw,
2080         &meson8b_fclk_div3.hw,
2081         &meson8b_fclk_div5.hw,
2082         &meson8b_fclk_div7.hw,
2083 };
2084
2085 static const struct clk_hw *mmeson8m2_vpu_0_1_parent_hws[] = {
2086         &meson8b_fclk_div4.hw,
2087         &meson8b_fclk_div3.hw,
2088         &meson8b_fclk_div5.hw,
2089         &meson8m2_gp_pll.hw,
2090 };
2091
2092 static struct clk_regmap meson8b_vpu_0_sel = {
2093         .data = &(struct clk_regmap_mux_data){
2094                 .offset = HHI_VPU_CLK_CNTL,
2095                 .mask = 0x3,
2096                 .shift = 9,
2097         },
2098         .hw.init = &(struct clk_init_data){
2099                 .name = "vpu_0_sel",
2100                 .ops = &clk_regmap_mux_ops,
2101                 .parent_hws = meson8b_vpu_0_1_parent_hws,
2102                 .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
2103                 .flags = CLK_SET_RATE_PARENT,
2104         },
2105 };
2106
2107 static struct clk_regmap meson8m2_vpu_0_sel = {
2108         .data = &(struct clk_regmap_mux_data){
2109                 .offset = HHI_VPU_CLK_CNTL,
2110                 .mask = 0x3,
2111                 .shift = 9,
2112         },
2113         .hw.init = &(struct clk_init_data){
2114                 .name = "vpu_0_sel",
2115                 .ops = &clk_regmap_mux_ops,
2116                 .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
2117                 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
2118                 .flags = CLK_SET_RATE_PARENT,
2119         },
2120 };
2121
2122 static struct clk_regmap meson8b_vpu_0_div = {
2123         .data = &(struct clk_regmap_div_data){
2124                 .offset = HHI_VPU_CLK_CNTL,
2125                 .shift = 0,
2126                 .width = 7,
2127         },
2128         .hw.init = &(struct clk_init_data){
2129                 .name = "vpu_0_div",
2130                 .ops = &clk_regmap_divider_ops,
2131                 .parent_data = &(const struct clk_parent_data) {
2132                         /*
2133                          * Note:
2134                          * meson8b and meson8m2 have different vpu_0_sels (with
2135                          * different struct clk_hw). We fallback to the global
2136                          * naming string mechanism so vpu_0_div picks up the
2137                          * appropriate one.
2138                          */
2139                         .name = "vpu_0_sel",
2140                         .index = -1,
2141                 },
2142                 .num_parents = 1,
2143                 .flags = CLK_SET_RATE_PARENT,
2144         },
2145 };
2146
2147 static struct clk_regmap meson8b_vpu_0 = {
2148         .data = &(struct clk_regmap_gate_data){
2149                 .offset = HHI_VPU_CLK_CNTL,
2150                 .bit_idx = 8,
2151         },
2152         .hw.init = &(struct clk_init_data) {
2153                 .name = "vpu_0",
2154                 .ops = &clk_regmap_gate_ops,
2155                 .parent_hws = (const struct clk_hw *[]) {
2156                         &meson8b_vpu_0_div.hw
2157                 },
2158                 .num_parents = 1,
2159                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
2160         },
2161 };
2162
2163 static struct clk_regmap meson8b_vpu_1_sel = {
2164         .data = &(struct clk_regmap_mux_data){
2165                 .offset = HHI_VPU_CLK_CNTL,
2166                 .mask = 0x3,
2167                 .shift = 25,
2168         },
2169         .hw.init = &(struct clk_init_data){
2170                 .name = "vpu_1_sel",
2171                 .ops = &clk_regmap_mux_ops,
2172                 .parent_hws = meson8b_vpu_0_1_parent_hws,
2173                 .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
2174                 .flags = CLK_SET_RATE_PARENT,
2175         },
2176 };
2177
2178 static struct clk_regmap meson8m2_vpu_1_sel = {
2179         .data = &(struct clk_regmap_mux_data){
2180                 .offset = HHI_VPU_CLK_CNTL,
2181                 .mask = 0x3,
2182                 .shift = 25,
2183         },
2184         .hw.init = &(struct clk_init_data){
2185                 .name = "vpu_1_sel",
2186                 .ops = &clk_regmap_mux_ops,
2187                 .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
2188                 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
2189                 .flags = CLK_SET_RATE_PARENT,
2190         },
2191 };
2192
2193 static struct clk_regmap meson8b_vpu_1_div = {
2194         .data = &(struct clk_regmap_div_data){
2195                 .offset = HHI_VPU_CLK_CNTL,
2196                 .shift = 16,
2197                 .width = 7,
2198         },
2199         .hw.init = &(struct clk_init_data){
2200                 .name = "vpu_1_div",
2201                 .ops = &clk_regmap_divider_ops,
2202                 .parent_data = &(const struct clk_parent_data) {
2203                         /*
2204                          * Note:
2205                          * meson8b and meson8m2 have different vpu_1_sels (with
2206                          * different struct clk_hw). We fallback to the global
2207                          * naming string mechanism so vpu_1_div picks up the
2208                          * appropriate one.
2209                          */
2210                         .name = "vpu_1_sel",
2211                         .index = -1,
2212                 },
2213                 .num_parents = 1,
2214                 .flags = CLK_SET_RATE_PARENT,
2215         },
2216 };
2217
2218 static struct clk_regmap meson8b_vpu_1 = {
2219         .data = &(struct clk_regmap_gate_data){
2220                 .offset = HHI_VPU_CLK_CNTL,
2221                 .bit_idx = 24,
2222         },
2223         .hw.init = &(struct clk_init_data) {
2224                 .name = "vpu_1",
2225                 .ops = &clk_regmap_gate_ops,
2226                 .parent_hws = (const struct clk_hw *[]) {
2227                         &meson8b_vpu_1_div.hw
2228                 },
2229                 .num_parents = 1,
2230                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
2231         },
2232 };
2233
2234 /*
2235  * The VPU clock has two identical clock trees (vpu_0 and vpu_1)
2236  * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
2237  * actually manage this glitch-free mux because it does top-to-bottom
2238  * updates the each clock tree and switches to the "inactive" one when
2239  * CLK_SET_RATE_GATE is set.
2240  * Meson8 only has vpu_0 and no glitch-free mux.
2241  */
2242 static struct clk_regmap meson8b_vpu = {
2243         .data = &(struct clk_regmap_mux_data){
2244                 .offset = HHI_VPU_CLK_CNTL,
2245                 .mask = 1,
2246                 .shift = 31,
2247         },
2248         .hw.init = &(struct clk_init_data){
2249                 .name = "vpu",
2250                 .ops = &clk_regmap_mux_ops,
2251                 .parent_hws = (const struct clk_hw *[]) {
2252                         &meson8b_vpu_0.hw,
2253                         &meson8b_vpu_1.hw,
2254                 },
2255                 .num_parents = 2,
2256                 .flags = CLK_SET_RATE_PARENT,
2257         },
2258 };
2259
2260 static const struct clk_hw *meson8b_vdec_parent_hws[] = {
2261         &meson8b_fclk_div4.hw,
2262         &meson8b_fclk_div3.hw,
2263         &meson8b_fclk_div5.hw,
2264         &meson8b_fclk_div7.hw,
2265         &meson8b_mpll2.hw,
2266         &meson8b_mpll1.hw,
2267 };
2268
2269 static struct clk_regmap meson8b_vdec_1_sel = {
2270         .data = &(struct clk_regmap_mux_data){
2271                 .offset = HHI_VDEC_CLK_CNTL,
2272                 .mask = 0x3,
2273                 .shift = 9,
2274                 .flags = CLK_MUX_ROUND_CLOSEST,
2275         },
2276         .hw.init = &(struct clk_init_data){
2277                 .name = "vdec_1_sel",
2278                 .ops = &clk_regmap_mux_ops,
2279                 .parent_hws = meson8b_vdec_parent_hws,
2280                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2281                 .flags = CLK_SET_RATE_PARENT,
2282         },
2283 };
2284
2285 static struct clk_regmap meson8b_vdec_1_1_div = {
2286         .data = &(struct clk_regmap_div_data){
2287                 .offset = HHI_VDEC_CLK_CNTL,
2288                 .shift = 0,
2289                 .width = 7,
2290                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2291         },
2292         .hw.init = &(struct clk_init_data){
2293                 .name = "vdec_1_1_div",
2294                 .ops = &clk_regmap_divider_ops,
2295                 .parent_hws = (const struct clk_hw *[]) {
2296                         &meson8b_vdec_1_sel.hw
2297                 },
2298                 .num_parents = 1,
2299                 .flags = CLK_SET_RATE_PARENT,
2300         },
2301 };
2302
2303 static struct clk_regmap meson8b_vdec_1_1 = {
2304         .data = &(struct clk_regmap_gate_data){
2305                 .offset = HHI_VDEC_CLK_CNTL,
2306                 .bit_idx = 8,
2307         },
2308         .hw.init = &(struct clk_init_data) {
2309                 .name = "vdec_1_1",
2310                 .ops = &clk_regmap_gate_ops,
2311                 .parent_hws = (const struct clk_hw *[]) {
2312                         &meson8b_vdec_1_1_div.hw
2313                 },
2314                 .num_parents = 1,
2315                 .flags = CLK_SET_RATE_PARENT,
2316         },
2317 };
2318
2319 static struct clk_regmap meson8b_vdec_1_2_div = {
2320         .data = &(struct clk_regmap_div_data){
2321                 .offset = HHI_VDEC3_CLK_CNTL,
2322                 .shift = 0,
2323                 .width = 7,
2324                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2325         },
2326         .hw.init = &(struct clk_init_data){
2327                 .name = "vdec_1_2_div",
2328                 .ops = &clk_regmap_divider_ops,
2329                 .parent_hws = (const struct clk_hw *[]) {
2330                         &meson8b_vdec_1_sel.hw
2331                 },
2332                 .num_parents = 1,
2333                 .flags = CLK_SET_RATE_PARENT,
2334         },
2335 };
2336
2337 static struct clk_regmap meson8b_vdec_1_2 = {
2338         .data = &(struct clk_regmap_gate_data){
2339                 .offset = HHI_VDEC3_CLK_CNTL,
2340                 .bit_idx = 8,
2341         },
2342         .hw.init = &(struct clk_init_data) {
2343                 .name = "vdec_1_2",
2344                 .ops = &clk_regmap_gate_ops,
2345                 .parent_hws = (const struct clk_hw *[]) {
2346                         &meson8b_vdec_1_2_div.hw
2347                 },
2348                 .num_parents = 1,
2349                 .flags = CLK_SET_RATE_PARENT,
2350         },
2351 };
2352
2353 static struct clk_regmap meson8b_vdec_1 = {
2354         .data = &(struct clk_regmap_mux_data){
2355                 .offset = HHI_VDEC3_CLK_CNTL,
2356                 .mask = 0x1,
2357                 .shift = 15,
2358                 .flags = CLK_MUX_ROUND_CLOSEST,
2359         },
2360         .hw.init = &(struct clk_init_data){
2361                 .name = "vdec_1",
2362                 .ops = &clk_regmap_mux_ops,
2363                 .parent_hws = (const struct clk_hw *[]) {
2364                         &meson8b_vdec_1_1.hw,
2365                         &meson8b_vdec_1_2.hw,
2366                 },
2367                 .num_parents = 2,
2368                 .flags = CLK_SET_RATE_PARENT,
2369         },
2370 };
2371
2372 static struct clk_regmap meson8b_vdec_hcodec_sel = {
2373         .data = &(struct clk_regmap_mux_data){
2374                 .offset = HHI_VDEC_CLK_CNTL,
2375                 .mask = 0x3,
2376                 .shift = 25,
2377                 .flags = CLK_MUX_ROUND_CLOSEST,
2378         },
2379         .hw.init = &(struct clk_init_data){
2380                 .name = "vdec_hcodec_sel",
2381                 .ops = &clk_regmap_mux_ops,
2382                 .parent_hws = meson8b_vdec_parent_hws,
2383                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2384                 .flags = CLK_SET_RATE_PARENT,
2385         },
2386 };
2387
2388 static struct clk_regmap meson8b_vdec_hcodec_div = {
2389         .data = &(struct clk_regmap_div_data){
2390                 .offset = HHI_VDEC_CLK_CNTL,
2391                 .shift = 16,
2392                 .width = 7,
2393                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2394         },
2395         .hw.init = &(struct clk_init_data){
2396                 .name = "vdec_hcodec_div",
2397                 .ops = &clk_regmap_divider_ops,
2398                 .parent_hws = (const struct clk_hw *[]) {
2399                         &meson8b_vdec_hcodec_sel.hw
2400                 },
2401                 .num_parents = 1,
2402                 .flags = CLK_SET_RATE_PARENT,
2403         },
2404 };
2405
2406 static struct clk_regmap meson8b_vdec_hcodec = {
2407         .data = &(struct clk_regmap_gate_data){
2408                 .offset = HHI_VDEC_CLK_CNTL,
2409                 .bit_idx = 24,
2410         },
2411         .hw.init = &(struct clk_init_data) {
2412                 .name = "vdec_hcodec",
2413                 .ops = &clk_regmap_gate_ops,
2414                 .parent_hws = (const struct clk_hw *[]) {
2415                         &meson8b_vdec_hcodec_div.hw
2416                 },
2417                 .num_parents = 1,
2418                 .flags = CLK_SET_RATE_PARENT,
2419         },
2420 };
2421
2422 static struct clk_regmap meson8b_vdec_2_sel = {
2423         .data = &(struct clk_regmap_mux_data){
2424                 .offset = HHI_VDEC2_CLK_CNTL,
2425                 .mask = 0x3,
2426                 .shift = 9,
2427                 .flags = CLK_MUX_ROUND_CLOSEST,
2428         },
2429         .hw.init = &(struct clk_init_data){
2430                 .name = "vdec_2_sel",
2431                 .ops = &clk_regmap_mux_ops,
2432                 .parent_hws = meson8b_vdec_parent_hws,
2433                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2434                 .flags = CLK_SET_RATE_PARENT,
2435         },
2436 };
2437
2438 static struct clk_regmap meson8b_vdec_2_div = {
2439         .data = &(struct clk_regmap_div_data){
2440                 .offset = HHI_VDEC2_CLK_CNTL,
2441                 .shift = 0,
2442                 .width = 7,
2443                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2444         },
2445         .hw.init = &(struct clk_init_data){
2446                 .name = "vdec_2_div",
2447                 .ops = &clk_regmap_divider_ops,
2448                 .parent_hws = (const struct clk_hw *[]) {
2449                         &meson8b_vdec_2_sel.hw
2450                 },
2451                 .num_parents = 1,
2452                 .flags = CLK_SET_RATE_PARENT,
2453         },
2454 };
2455
2456 static struct clk_regmap meson8b_vdec_2 = {
2457         .data = &(struct clk_regmap_gate_data){
2458                 .offset = HHI_VDEC2_CLK_CNTL,
2459                 .bit_idx = 8,
2460         },
2461         .hw.init = &(struct clk_init_data) {
2462                 .name = "vdec_2",
2463                 .ops = &clk_regmap_gate_ops,
2464                 .parent_hws = (const struct clk_hw *[]) {
2465                         &meson8b_vdec_2_div.hw
2466                 },
2467                 .num_parents = 1,
2468                 .flags = CLK_SET_RATE_PARENT,
2469         },
2470 };
2471
2472 static struct clk_regmap meson8b_vdec_hevc_sel = {
2473         .data = &(struct clk_regmap_mux_data){
2474                 .offset = HHI_VDEC2_CLK_CNTL,
2475                 .mask = 0x3,
2476                 .shift = 25,
2477                 .flags = CLK_MUX_ROUND_CLOSEST,
2478         },
2479         .hw.init = &(struct clk_init_data){
2480                 .name = "vdec_hevc_sel",
2481                 .ops = &clk_regmap_mux_ops,
2482                 .parent_hws = meson8b_vdec_parent_hws,
2483                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2484                 .flags = CLK_SET_RATE_PARENT,
2485         },
2486 };
2487
2488 static struct clk_regmap meson8b_vdec_hevc_div = {
2489         .data = &(struct clk_regmap_div_data){
2490                 .offset = HHI_VDEC2_CLK_CNTL,
2491                 .shift = 16,
2492                 .width = 7,
2493                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2494         },
2495         .hw.init = &(struct clk_init_data){
2496                 .name = "vdec_hevc_div",
2497                 .ops = &clk_regmap_divider_ops,
2498                 .parent_hws = (const struct clk_hw *[]) {
2499                         &meson8b_vdec_hevc_sel.hw
2500                 },
2501                 .num_parents = 1,
2502                 .flags = CLK_SET_RATE_PARENT,
2503         },
2504 };
2505
2506 static struct clk_regmap meson8b_vdec_hevc_en = {
2507         .data = &(struct clk_regmap_gate_data){
2508                 .offset = HHI_VDEC2_CLK_CNTL,
2509                 .bit_idx = 24,
2510         },
2511         .hw.init = &(struct clk_init_data) {
2512                 .name = "vdec_hevc_en",
2513                 .ops = &clk_regmap_gate_ops,
2514                 .parent_hws = (const struct clk_hw *[]) {
2515                         &meson8b_vdec_hevc_div.hw
2516                 },
2517                 .num_parents = 1,
2518                 .flags = CLK_SET_RATE_PARENT,
2519         },
2520 };
2521
2522 static struct clk_regmap meson8b_vdec_hevc = {
2523         .data = &(struct clk_regmap_mux_data){
2524                 .offset = HHI_VDEC2_CLK_CNTL,
2525                 .mask = 0x1,
2526                 .shift = 31,
2527                 .flags = CLK_MUX_ROUND_CLOSEST,
2528         },
2529         .hw.init = &(struct clk_init_data){
2530                 .name = "vdec_hevc",
2531                 .ops = &clk_regmap_mux_ops,
2532                 /* TODO: The second parent is currently unknown */
2533                 .parent_hws = (const struct clk_hw *[]) {
2534                         &meson8b_vdec_hevc_en.hw
2535                 },
2536                 .num_parents = 1,
2537                 .flags = CLK_SET_RATE_PARENT,
2538         },
2539 };
2540
2541 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
2542 static const struct clk_hw *meson8b_cts_amclk_parent_hws[] = {
2543         &meson8b_mpll0.hw,
2544         &meson8b_mpll1.hw,
2545         &meson8b_mpll2.hw
2546 };
2547
2548 static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 };
2549
2550 static struct clk_regmap meson8b_cts_amclk_sel = {
2551         .data = &(struct clk_regmap_mux_data){
2552                 .offset = HHI_AUD_CLK_CNTL,
2553                 .mask = 0x3,
2554                 .shift = 9,
2555                 .table = meson8b_cts_amclk_mux_table,
2556                 .flags = CLK_MUX_ROUND_CLOSEST,
2557         },
2558         .hw.init = &(struct clk_init_data){
2559                 .name = "cts_amclk_sel",
2560                 .ops = &clk_regmap_mux_ops,
2561                 .parent_hws = meson8b_cts_amclk_parent_hws,
2562                 .num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_hws),
2563         },
2564 };
2565
2566 static struct clk_regmap meson8b_cts_amclk_div = {
2567         .data = &(struct clk_regmap_div_data) {
2568                 .offset = HHI_AUD_CLK_CNTL,
2569                 .shift = 0,
2570                 .width = 8,
2571                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2572         },
2573         .hw.init = &(struct clk_init_data){
2574                 .name = "cts_amclk_div",
2575                 .ops = &clk_regmap_divider_ops,
2576                 .parent_hws = (const struct clk_hw *[]) {
2577                         &meson8b_cts_amclk_sel.hw
2578                 },
2579                 .num_parents = 1,
2580                 .flags = CLK_SET_RATE_PARENT,
2581         },
2582 };
2583
2584 static struct clk_regmap meson8b_cts_amclk = {
2585         .data = &(struct clk_regmap_gate_data){
2586                 .offset = HHI_AUD_CLK_CNTL,
2587                 .bit_idx = 8,
2588         },
2589         .hw.init = &(struct clk_init_data){
2590                 .name = "cts_amclk",
2591                 .ops = &clk_regmap_gate_ops,
2592                 .parent_hws = (const struct clk_hw *[]) {
2593                         &meson8b_cts_amclk_div.hw
2594                 },
2595                 .num_parents = 1,
2596                 .flags = CLK_SET_RATE_PARENT,
2597         },
2598 };
2599
2600 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
2601 static const struct clk_hw *meson8b_cts_mclk_i958_parent_hws[] = {
2602         &meson8b_mpll0.hw,
2603         &meson8b_mpll1.hw,
2604         &meson8b_mpll2.hw
2605 };
2606
2607 static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 };
2608
2609 static struct clk_regmap meson8b_cts_mclk_i958_sel = {
2610         .data = &(struct clk_regmap_mux_data){
2611                 .offset = HHI_AUD_CLK_CNTL2,
2612                 .mask = 0x3,
2613                 .shift = 25,
2614                 .table = meson8b_cts_mclk_i958_mux_table,
2615                 .flags = CLK_MUX_ROUND_CLOSEST,
2616         },
2617         .hw.init = &(struct clk_init_data) {
2618                 .name = "cts_mclk_i958_sel",
2619                 .ops = &clk_regmap_mux_ops,
2620                 .parent_hws = meson8b_cts_mclk_i958_parent_hws,
2621                 .num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_hws),
2622         },
2623 };
2624
2625 static struct clk_regmap meson8b_cts_mclk_i958_div = {
2626         .data = &(struct clk_regmap_div_data){
2627                 .offset = HHI_AUD_CLK_CNTL2,
2628                 .shift = 16,
2629                 .width = 8,
2630                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2631         },
2632         .hw.init = &(struct clk_init_data) {
2633                 .name = "cts_mclk_i958_div",
2634                 .ops = &clk_regmap_divider_ops,
2635                 .parent_hws = (const struct clk_hw *[]) {
2636                         &meson8b_cts_mclk_i958_sel.hw
2637                 },
2638                 .num_parents = 1,
2639                 .flags = CLK_SET_RATE_PARENT,
2640         },
2641 };
2642
2643 static struct clk_regmap meson8b_cts_mclk_i958 = {
2644         .data = &(struct clk_regmap_gate_data){
2645                 .offset = HHI_AUD_CLK_CNTL2,
2646                 .bit_idx = 24,
2647         },
2648         .hw.init = &(struct clk_init_data){
2649                 .name = "cts_mclk_i958",
2650                 .ops = &clk_regmap_gate_ops,
2651                 .parent_hws = (const struct clk_hw *[]) {
2652                         &meson8b_cts_mclk_i958_div.hw
2653                 },
2654                 .num_parents = 1,
2655                 .flags = CLK_SET_RATE_PARENT,
2656         },
2657 };
2658
2659 static struct clk_regmap meson8b_cts_i958 = {
2660         .data = &(struct clk_regmap_mux_data){
2661                 .offset = HHI_AUD_CLK_CNTL2,
2662                 .mask = 0x1,
2663                 .shift = 27,
2664                 },
2665         .hw.init = &(struct clk_init_data){
2666                 .name = "cts_i958",
2667                 .ops = &clk_regmap_mux_ops,
2668                 .parent_hws = (const struct clk_hw *[]) {
2669                         &meson8b_cts_amclk.hw,
2670                         &meson8b_cts_mclk_i958.hw
2671                 },
2672                 .num_parents = 2,
2673                 /*
2674                  * The parent is specific to origin of the audio data. Let the
2675                  * consumer choose the appropriate parent.
2676                  */
2677                 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
2678         },
2679 };
2680
2681 #define MESON_GATE(_name, _reg, _bit) \
2682         MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw)
2683
2684 /* Everything Else (EE) domain gates */
2685
2686 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
2687 static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
2688 static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
2689 static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
2690 static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
2691 static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
2692 static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
2693 static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
2694 static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
2695 static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
2696 static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
2697 static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
2698 static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
2699 static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
2700 static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
2701 static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
2702 static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
2703 static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
2704 static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
2705
2706 static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
2707 static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
2708 static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
2709 static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
2710 static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
2711 static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
2712 static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
2713 static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
2714 static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
2715 static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
2716 static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
2717 static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
2718 static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
2719 static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
2720 static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
2721 static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
2722 static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
2723
2724 static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2725 static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2726 static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
2727 static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
2728 static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
2729 static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
2730 static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
2731 static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
2732 static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
2733 static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
2734 static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
2735 static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
2736 static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
2737
2738 static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
2739 static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
2740 static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2741 static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2742 static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
2743 static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
2744 static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
2745 static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
2746 static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
2747 static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
2748 static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
2749 static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
2750 static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
2751 static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
2752 static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
2753 static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
2754
2755 /* AIU gates */
2756 #define MESON_AIU_GLUE_GATE(_name, _reg, _bit) \
2757         MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw)
2758
2759 static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw);
2760 static MESON_AIU_GLUE_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
2761 static MESON_AIU_GLUE_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
2762 static MESON_AIU_GLUE_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
2763 static MESON_AIU_GLUE_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
2764 static MESON_AIU_GLUE_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
2765 static MESON_AIU_GLUE_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
2766 static MESON_AIU_GLUE_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
2767
2768 /* Always On (AO) domain gates */
2769
2770 static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
2771 static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
2772 static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
2773 static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
2774
2775 static struct clk_hw_onecell_data meson8_hw_onecell_data = {
2776         .hws = {
2777                 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2778                 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2779                 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2780                 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2781                 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2782                 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2783                 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2784                 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2785                 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2786                 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2787                 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2788                 [CLKID_CLK81] = &meson8b_clk81.hw,
2789                 [CLKID_DDR]                 = &meson8b_ddr.hw,
2790                 [CLKID_DOS]                 = &meson8b_dos.hw,
2791                 [CLKID_ISA]                 = &meson8b_isa.hw,
2792                 [CLKID_PL301]               = &meson8b_pl301.hw,
2793                 [CLKID_PERIPHS]             = &meson8b_periphs.hw,
2794                 [CLKID_SPICC]               = &meson8b_spicc.hw,
2795                 [CLKID_I2C]                 = &meson8b_i2c.hw,
2796                 [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
2797                 [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
2798                 [CLKID_RNG0]                = &meson8b_rng0.hw,
2799                 [CLKID_UART0]               = &meson8b_uart0.hw,
2800                 [CLKID_SDHC]                = &meson8b_sdhc.hw,
2801                 [CLKID_STREAM]              = &meson8b_stream.hw,
2802                 [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
2803                 [CLKID_SDIO]                = &meson8b_sdio.hw,
2804                 [CLKID_ABUF]                = &meson8b_abuf.hw,
2805                 [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
2806                 [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
2807                 [CLKID_SPI]                 = &meson8b_spi.hw,
2808                 [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
2809                 [CLKID_ETH]                 = &meson8b_eth.hw,
2810                 [CLKID_DEMUX]               = &meson8b_demux.hw,
2811                 [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
2812                 [CLKID_IEC958]              = &meson8b_iec958.hw,
2813                 [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
2814                 [CLKID_AMCLK]               = &meson8b_amclk.hw,
2815                 [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
2816                 [CLKID_MIXER]               = &meson8b_mixer.hw,
2817                 [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
2818                 [CLKID_ADC]                 = &meson8b_adc.hw,
2819                 [CLKID_BLKMV]               = &meson8b_blkmv.hw,
2820                 [CLKID_AIU]                 = &meson8b_aiu.hw,
2821                 [CLKID_UART1]               = &meson8b_uart1.hw,
2822                 [CLKID_G2D]                 = &meson8b_g2d.hw,
2823                 [CLKID_USB0]                = &meson8b_usb0.hw,
2824                 [CLKID_USB1]                = &meson8b_usb1.hw,
2825                 [CLKID_RESET]               = &meson8b_reset.hw,
2826                 [CLKID_NAND]                = &meson8b_nand.hw,
2827                 [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
2828                 [CLKID_USB]                 = &meson8b_usb.hw,
2829                 [CLKID_VDIN1]               = &meson8b_vdin1.hw,
2830                 [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
2831                 [CLKID_EFUSE]               = &meson8b_efuse.hw,
2832                 [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
2833                 [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
2834                 [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
2835                 [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
2836                 [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
2837                 [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
2838                 [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
2839                 [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
2840                 [CLKID_DVIN]                = &meson8b_dvin.hw,
2841                 [CLKID_UART2]               = &meson8b_uart2.hw,
2842                 [CLKID_SANA]                = &meson8b_sana.hw,
2843                 [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
2844                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
2845                 [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
2846                 [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
2847                 [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
2848                 [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
2849                 [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
2850                 [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
2851                 [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
2852                 [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
2853                 [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
2854                 [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
2855                 [CLKID_ENC480P]             = &meson8b_enc480p.hw,
2856                 [CLKID_RNG1]                = &meson8b_rng1.hw,
2857                 [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
2858                 [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
2859                 [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
2860                 [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
2861                 [CLKID_EDP]                 = &meson8b_edp.hw,
2862                 [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
2863                 [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
2864                 [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
2865                 [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
2866                 [CLKID_MPLL0]               = &meson8b_mpll0.hw,
2867                 [CLKID_MPLL1]               = &meson8b_mpll1.hw,
2868                 [CLKID_MPLL2]               = &meson8b_mpll2.hw,
2869                 [CLKID_MPLL0_DIV]           = &meson8b_mpll0_div.hw,
2870                 [CLKID_MPLL1_DIV]           = &meson8b_mpll1_div.hw,
2871                 [CLKID_MPLL2_DIV]           = &meson8b_mpll2_div.hw,
2872                 [CLKID_CPU_IN_SEL]          = &meson8b_cpu_in_sel.hw,
2873                 [CLKID_CPU_IN_DIV2]         = &meson8b_cpu_in_div2.hw,
2874                 [CLKID_CPU_IN_DIV3]         = &meson8b_cpu_in_div3.hw,
2875                 [CLKID_CPU_SCALE_DIV]       = &meson8b_cpu_scale_div.hw,
2876                 [CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
2877                 [CLKID_MPLL_PREDIV]         = &meson8b_mpll_prediv.hw,
2878                 [CLKID_FCLK_DIV2_DIV]       = &meson8b_fclk_div2_div.hw,
2879                 [CLKID_FCLK_DIV3_DIV]       = &meson8b_fclk_div3_div.hw,
2880                 [CLKID_FCLK_DIV4_DIV]       = &meson8b_fclk_div4_div.hw,
2881                 [CLKID_FCLK_DIV5_DIV]       = &meson8b_fclk_div5_div.hw,
2882                 [CLKID_FCLK_DIV7_DIV]       = &meson8b_fclk_div7_div.hw,
2883                 [CLKID_NAND_SEL]            = &meson8b_nand_clk_sel.hw,
2884                 [CLKID_NAND_DIV]            = &meson8b_nand_clk_div.hw,
2885                 [CLKID_NAND_CLK]            = &meson8b_nand_clk_gate.hw,
2886                 [CLKID_PLL_FIXED_DCO]       = &meson8b_fixed_pll_dco.hw,
2887                 [CLKID_HDMI_PLL_DCO]        = &meson8b_hdmi_pll_dco.hw,
2888                 [CLKID_PLL_SYS_DCO]         = &meson8b_sys_pll_dco.hw,
2889                 [CLKID_CPU_CLK_DIV2]        = &meson8b_cpu_clk_div2.hw,
2890                 [CLKID_CPU_CLK_DIV3]        = &meson8b_cpu_clk_div3.hw,
2891                 [CLKID_CPU_CLK_DIV4]        = &meson8b_cpu_clk_div4.hw,
2892                 [CLKID_CPU_CLK_DIV5]        = &meson8b_cpu_clk_div5.hw,
2893                 [CLKID_CPU_CLK_DIV6]        = &meson8b_cpu_clk_div6.hw,
2894                 [CLKID_CPU_CLK_DIV7]        = &meson8b_cpu_clk_div7.hw,
2895                 [CLKID_CPU_CLK_DIV8]        = &meson8b_cpu_clk_div8.hw,
2896                 [CLKID_APB_SEL]             = &meson8b_apb_clk_sel.hw,
2897                 [CLKID_APB]                 = &meson8b_apb_clk_gate.hw,
2898                 [CLKID_PERIPH_SEL]          = &meson8b_periph_clk_sel.hw,
2899                 [CLKID_PERIPH]              = &meson8b_periph_clk_gate.hw,
2900                 [CLKID_AXI_SEL]             = &meson8b_axi_clk_sel.hw,
2901                 [CLKID_AXI]                 = &meson8b_axi_clk_gate.hw,
2902                 [CLKID_L2_DRAM_SEL]         = &meson8b_l2_dram_clk_sel.hw,
2903                 [CLKID_L2_DRAM]             = &meson8b_l2_dram_clk_gate.hw,
2904                 [CLKID_HDMI_PLL_LVDS_OUT]   = &meson8b_hdmi_pll_lvds_out.hw,
2905                 [CLKID_HDMI_PLL_HDMI_OUT]   = &meson8b_hdmi_pll_hdmi_out.hw,
2906                 [CLKID_VID_PLL_IN_SEL]      = &meson8b_vid_pll_in_sel.hw,
2907                 [CLKID_VID_PLL_IN_EN]       = &meson8b_vid_pll_in_en.hw,
2908                 [CLKID_VID_PLL_PRE_DIV]     = &meson8b_vid_pll_pre_div.hw,
2909                 [CLKID_VID_PLL_POST_DIV]    = &meson8b_vid_pll_post_div.hw,
2910                 [CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,
2911                 [CLKID_VCLK_IN_SEL]         = &meson8b_vclk_in_sel.hw,
2912                 [CLKID_VCLK_IN_EN]          = &meson8b_vclk_in_en.hw,
2913                 [CLKID_VCLK_EN]             = &meson8b_vclk_en.hw,
2914                 [CLKID_VCLK_DIV1]           = &meson8b_vclk_div1_gate.hw,
2915                 [CLKID_VCLK_DIV2_DIV]       = &meson8b_vclk_div2_div.hw,
2916                 [CLKID_VCLK_DIV2]           = &meson8b_vclk_div2_div_gate.hw,
2917                 [CLKID_VCLK_DIV4_DIV]       = &meson8b_vclk_div4_div.hw,
2918                 [CLKID_VCLK_DIV4]           = &meson8b_vclk_div4_div_gate.hw,
2919                 [CLKID_VCLK_DIV6_DIV]       = &meson8b_vclk_div6_div.hw,
2920                 [CLKID_VCLK_DIV6]           = &meson8b_vclk_div6_div_gate.hw,
2921                 [CLKID_VCLK_DIV12_DIV]      = &meson8b_vclk_div12_div.hw,
2922                 [CLKID_VCLK_DIV12]          = &meson8b_vclk_div12_div_gate.hw,
2923                 [CLKID_VCLK2_IN_SEL]        = &meson8b_vclk2_in_sel.hw,
2924                 [CLKID_VCLK2_IN_EN]         = &meson8b_vclk2_clk_in_en.hw,
2925                 [CLKID_VCLK2_EN]            = &meson8b_vclk2_clk_en.hw,
2926                 [CLKID_VCLK2_DIV1]          = &meson8b_vclk2_div1_gate.hw,
2927                 [CLKID_VCLK2_DIV2_DIV]      = &meson8b_vclk2_div2_div.hw,
2928                 [CLKID_VCLK2_DIV2]          = &meson8b_vclk2_div2_div_gate.hw,
2929                 [CLKID_VCLK2_DIV4_DIV]      = &meson8b_vclk2_div4_div.hw,
2930                 [CLKID_VCLK2_DIV4]          = &meson8b_vclk2_div4_div_gate.hw,
2931                 [CLKID_VCLK2_DIV6_DIV]      = &meson8b_vclk2_div6_div.hw,
2932                 [CLKID_VCLK2_DIV6]          = &meson8b_vclk2_div6_div_gate.hw,
2933                 [CLKID_VCLK2_DIV12_DIV]     = &meson8b_vclk2_div12_div.hw,
2934                 [CLKID_VCLK2_DIV12]         = &meson8b_vclk2_div12_div_gate.hw,
2935                 [CLKID_CTS_ENCT_SEL]        = &meson8b_cts_enct_sel.hw,
2936                 [CLKID_CTS_ENCT]            = &meson8b_cts_enct.hw,
2937                 [CLKID_CTS_ENCP_SEL]        = &meson8b_cts_encp_sel.hw,
2938                 [CLKID_CTS_ENCP]            = &meson8b_cts_encp.hw,
2939                 [CLKID_CTS_ENCI_SEL]        = &meson8b_cts_enci_sel.hw,
2940                 [CLKID_CTS_ENCI]            = &meson8b_cts_enci.hw,
2941                 [CLKID_HDMI_TX_PIXEL_SEL]   = &meson8b_hdmi_tx_pixel_sel.hw,
2942                 [CLKID_HDMI_TX_PIXEL]       = &meson8b_hdmi_tx_pixel.hw,
2943                 [CLKID_CTS_ENCL_SEL]        = &meson8b_cts_encl_sel.hw,
2944                 [CLKID_CTS_ENCL]            = &meson8b_cts_encl.hw,
2945                 [CLKID_CTS_VDAC0_SEL]       = &meson8b_cts_vdac0_sel.hw,
2946                 [CLKID_CTS_VDAC0]           = &meson8b_cts_vdac0.hw,
2947                 [CLKID_HDMI_SYS_SEL]        = &meson8b_hdmi_sys_sel.hw,
2948                 [CLKID_HDMI_SYS_DIV]        = &meson8b_hdmi_sys_div.hw,
2949                 [CLKID_HDMI_SYS]            = &meson8b_hdmi_sys.hw,
2950                 [CLKID_MALI_0_SEL]          = &meson8b_mali_0_sel.hw,
2951                 [CLKID_MALI_0_DIV]          = &meson8b_mali_0_div.hw,
2952                 [CLKID_MALI]                = &meson8b_mali_0.hw,
2953                 [CLKID_VPU_0_SEL]           = &meson8b_vpu_0_sel.hw,
2954                 [CLKID_VPU_0_DIV]           = &meson8b_vpu_0_div.hw,
2955                 [CLKID_VPU]                 = &meson8b_vpu_0.hw,
2956                 [CLKID_VDEC_1_SEL]          = &meson8b_vdec_1_sel.hw,
2957                 [CLKID_VDEC_1_1_DIV]        = &meson8b_vdec_1_1_div.hw,
2958                 [CLKID_VDEC_1]              = &meson8b_vdec_1_1.hw,
2959                 [CLKID_VDEC_HCODEC_SEL]     = &meson8b_vdec_hcodec_sel.hw,
2960                 [CLKID_VDEC_HCODEC_DIV]     = &meson8b_vdec_hcodec_div.hw,
2961                 [CLKID_VDEC_HCODEC]         = &meson8b_vdec_hcodec.hw,
2962                 [CLKID_VDEC_2_SEL]          = &meson8b_vdec_2_sel.hw,
2963                 [CLKID_VDEC_2_DIV]          = &meson8b_vdec_2_div.hw,
2964                 [CLKID_VDEC_2]              = &meson8b_vdec_2.hw,
2965                 [CLKID_VDEC_HEVC_SEL]       = &meson8b_vdec_hevc_sel.hw,
2966                 [CLKID_VDEC_HEVC_DIV]       = &meson8b_vdec_hevc_div.hw,
2967                 [CLKID_VDEC_HEVC_EN]        = &meson8b_vdec_hevc_en.hw,
2968                 [CLKID_VDEC_HEVC]           = &meson8b_vdec_hevc.hw,
2969                 [CLKID_CTS_AMCLK_SEL]       = &meson8b_cts_amclk_sel.hw,
2970                 [CLKID_CTS_AMCLK_DIV]       = &meson8b_cts_amclk_div.hw,
2971                 [CLKID_CTS_AMCLK]           = &meson8b_cts_amclk.hw,
2972                 [CLKID_CTS_MCLK_I958_SEL]   = &meson8b_cts_mclk_i958_sel.hw,
2973                 [CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,
2974                 [CLKID_CTS_MCLK_I958]       = &meson8b_cts_mclk_i958.hw,
2975                 [CLKID_CTS_I958]            = &meson8b_cts_i958.hw,
2976                 [CLKID_VID_PLL_LVDS_EN]     = &meson8b_vid_pll_lvds_en.hw,
2977                 [CLKID_HDMI_PLL_DCO_IN]     = &hdmi_pll_dco_in.hw,
2978                 [CLK_NR_CLKS]               = NULL,
2979         },
2980         .num = CLK_NR_CLKS,
2981 };
2982
2983 static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
2984         .hws = {
2985                 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2986                 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2987                 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2988                 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2989                 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2990                 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2991                 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2992                 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2993                 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2994                 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2995                 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2996                 [CLKID_CLK81] = &meson8b_clk81.hw,
2997                 [CLKID_DDR]                 = &meson8b_ddr.hw,
2998                 [CLKID_DOS]                 = &meson8b_dos.hw,
2999                 [CLKID_ISA]                 = &meson8b_isa.hw,
3000                 [CLKID_PL301]               = &meson8b_pl301.hw,
3001                 [CLKID_PERIPHS]             = &meson8b_periphs.hw,
3002                 [CLKID_SPICC]               = &meson8b_spicc.hw,
3003                 [CLKID_I2C]                 = &meson8b_i2c.hw,
3004                 [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
3005                 [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
3006                 [CLKID_RNG0]                = &meson8b_rng0.hw,
3007                 [CLKID_UART0]               = &meson8b_uart0.hw,
3008                 [CLKID_SDHC]                = &meson8b_sdhc.hw,
3009                 [CLKID_STREAM]              = &meson8b_stream.hw,
3010                 [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
3011                 [CLKID_SDIO]                = &meson8b_sdio.hw,
3012                 [CLKID_ABUF]                = &meson8b_abuf.hw,
3013                 [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
3014                 [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
3015                 [CLKID_SPI]                 = &meson8b_spi.hw,
3016                 [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
3017                 [CLKID_ETH]                 = &meson8b_eth.hw,
3018                 [CLKID_DEMUX]               = &meson8b_demux.hw,
3019                 [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
3020                 [CLKID_IEC958]              = &meson8b_iec958.hw,
3021                 [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
3022                 [CLKID_AMCLK]               = &meson8b_amclk.hw,
3023                 [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
3024                 [CLKID_MIXER]               = &meson8b_mixer.hw,
3025                 [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
3026                 [CLKID_ADC]                 = &meson8b_adc.hw,
3027                 [CLKID_BLKMV]               = &meson8b_blkmv.hw,
3028                 [CLKID_AIU]                 = &meson8b_aiu.hw,
3029                 [CLKID_UART1]               = &meson8b_uart1.hw,
3030                 [CLKID_G2D]                 = &meson8b_g2d.hw,
3031                 [CLKID_USB0]                = &meson8b_usb0.hw,
3032                 [CLKID_USB1]                = &meson8b_usb1.hw,
3033                 [CLKID_RESET]               = &meson8b_reset.hw,
3034                 [CLKID_NAND]                = &meson8b_nand.hw,
3035                 [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
3036                 [CLKID_USB]                 = &meson8b_usb.hw,
3037                 [CLKID_VDIN1]               = &meson8b_vdin1.hw,
3038                 [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
3039                 [CLKID_EFUSE]               = &meson8b_efuse.hw,
3040                 [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
3041                 [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
3042                 [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
3043                 [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
3044                 [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
3045                 [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
3046                 [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
3047                 [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
3048                 [CLKID_DVIN]                = &meson8b_dvin.hw,
3049                 [CLKID_UART2]               = &meson8b_uart2.hw,
3050                 [CLKID_SANA]                = &meson8b_sana.hw,
3051                 [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
3052                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
3053                 [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
3054                 [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
3055                 [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
3056                 [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
3057                 [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
3058                 [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
3059                 [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
3060                 [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
3061                 [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
3062                 [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
3063                 [CLKID_ENC480P]             = &meson8b_enc480p.hw,
3064                 [CLKID_RNG1]                = &meson8b_rng1.hw,
3065                 [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
3066                 [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
3067                 [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
3068                 [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
3069                 [CLKID_EDP]                 = &meson8b_edp.hw,
3070                 [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
3071                 [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
3072                 [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
3073                 [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
3074                 [CLKID_MPLL0]               = &meson8b_mpll0.hw,
3075                 [CLKID_MPLL1]               = &meson8b_mpll1.hw,
3076                 [CLKID_MPLL2]               = &meson8b_mpll2.hw,
3077                 [CLKID_MPLL0_DIV]           = &meson8b_mpll0_div.hw,
3078                 [CLKID_MPLL1_DIV]           = &meson8b_mpll1_div.hw,
3079                 [CLKID_MPLL2_DIV]           = &meson8b_mpll2_div.hw,
3080                 [CLKID_CPU_IN_SEL]          = &meson8b_cpu_in_sel.hw,
3081                 [CLKID_CPU_IN_DIV2]         = &meson8b_cpu_in_div2.hw,
3082                 [CLKID_CPU_IN_DIV3]         = &meson8b_cpu_in_div3.hw,
3083                 [CLKID_CPU_SCALE_DIV]       = &meson8b_cpu_scale_div.hw,
3084                 [CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
3085                 [CLKID_MPLL_PREDIV]         = &meson8b_mpll_prediv.hw,
3086                 [CLKID_FCLK_DIV2_DIV]       = &meson8b_fclk_div2_div.hw,
3087                 [CLKID_FCLK_DIV3_DIV]       = &meson8b_fclk_div3_div.hw,
3088                 [CLKID_FCLK_DIV4_DIV]       = &meson8b_fclk_div4_div.hw,
3089                 [CLKID_FCLK_DIV5_DIV]       = &meson8b_fclk_div5_div.hw,
3090                 [CLKID_FCLK_DIV7_DIV]       = &meson8b_fclk_div7_div.hw,
3091                 [CLKID_NAND_SEL]            = &meson8b_nand_clk_sel.hw,
3092                 [CLKID_NAND_DIV]            = &meson8b_nand_clk_div.hw,
3093                 [CLKID_NAND_CLK]            = &meson8b_nand_clk_gate.hw,
3094                 [CLKID_PLL_FIXED_DCO]       = &meson8b_fixed_pll_dco.hw,
3095                 [CLKID_HDMI_PLL_DCO]        = &meson8b_hdmi_pll_dco.hw,
3096                 [CLKID_PLL_SYS_DCO]         = &meson8b_sys_pll_dco.hw,
3097                 [CLKID_CPU_CLK_DIV2]        = &meson8b_cpu_clk_div2.hw,
3098                 [CLKID_CPU_CLK_DIV3]        = &meson8b_cpu_clk_div3.hw,
3099                 [CLKID_CPU_CLK_DIV4]        = &meson8b_cpu_clk_div4.hw,
3100                 [CLKID_CPU_CLK_DIV5]        = &meson8b_cpu_clk_div5.hw,
3101                 [CLKID_CPU_CLK_DIV6]        = &meson8b_cpu_clk_div6.hw,
3102                 [CLKID_CPU_CLK_DIV7]        = &meson8b_cpu_clk_div7.hw,
3103                 [CLKID_CPU_CLK_DIV8]        = &meson8b_cpu_clk_div8.hw,
3104                 [CLKID_APB_SEL]             = &meson8b_apb_clk_sel.hw,
3105                 [CLKID_APB]                 = &meson8b_apb_clk_gate.hw,
3106                 [CLKID_PERIPH_SEL]          = &meson8b_periph_clk_sel.hw,
3107                 [CLKID_PERIPH]              = &meson8b_periph_clk_gate.hw,
3108                 [CLKID_AXI_SEL]             = &meson8b_axi_clk_sel.hw,
3109                 [CLKID_AXI]                 = &meson8b_axi_clk_gate.hw,
3110                 [CLKID_L2_DRAM_SEL]         = &meson8b_l2_dram_clk_sel.hw,
3111                 [CLKID_L2_DRAM]             = &meson8b_l2_dram_clk_gate.hw,
3112                 [CLKID_HDMI_PLL_LVDS_OUT]   = &meson8b_hdmi_pll_lvds_out.hw,
3113                 [CLKID_HDMI_PLL_HDMI_OUT]   = &meson8b_hdmi_pll_hdmi_out.hw,
3114                 [CLKID_VID_PLL_IN_SEL]      = &meson8b_vid_pll_in_sel.hw,
3115                 [CLKID_VID_PLL_IN_EN]       = &meson8b_vid_pll_in_en.hw,
3116                 [CLKID_VID_PLL_PRE_DIV]     = &meson8b_vid_pll_pre_div.hw,
3117                 [CLKID_VID_PLL_POST_DIV]    = &meson8b_vid_pll_post_div.hw,
3118                 [CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,
3119                 [CLKID_VCLK_IN_SEL]         = &meson8b_vclk_in_sel.hw,
3120                 [CLKID_VCLK_IN_EN]          = &meson8b_vclk_in_en.hw,
3121                 [CLKID_VCLK_EN]             = &meson8b_vclk_en.hw,
3122                 [CLKID_VCLK_DIV1]           = &meson8b_vclk_div1_gate.hw,
3123                 [CLKID_VCLK_DIV2_DIV]       = &meson8b_vclk_div2_div.hw,
3124                 [CLKID_VCLK_DIV2]           = &meson8b_vclk_div2_div_gate.hw,
3125                 [CLKID_VCLK_DIV4_DIV]       = &meson8b_vclk_div4_div.hw,
3126                 [CLKID_VCLK_DIV4]           = &meson8b_vclk_div4_div_gate.hw,
3127                 [CLKID_VCLK_DIV6_DIV]       = &meson8b_vclk_div6_div.hw,
3128                 [CLKID_VCLK_DIV6]           = &meson8b_vclk_div6_div_gate.hw,
3129                 [CLKID_VCLK_DIV12_DIV]      = &meson8b_vclk_div12_div.hw,
3130                 [CLKID_VCLK_DIV12]          = &meson8b_vclk_div12_div_gate.hw,
3131                 [CLKID_VCLK2_IN_SEL]        = &meson8b_vclk2_in_sel.hw,
3132                 [CLKID_VCLK2_IN_EN]         = &meson8b_vclk2_clk_in_en.hw,
3133                 [CLKID_VCLK2_EN]            = &meson8b_vclk2_clk_en.hw,
3134                 [CLKID_VCLK2_DIV1]          = &meson8b_vclk2_div1_gate.hw,
3135                 [CLKID_VCLK2_DIV2_DIV]      = &meson8b_vclk2_div2_div.hw,
3136                 [CLKID_VCLK2_DIV2]          = &meson8b_vclk2_div2_div_gate.hw,
3137                 [CLKID_VCLK2_DIV4_DIV]      = &meson8b_vclk2_div4_div.hw,
3138                 [CLKID_VCLK2_DIV4]          = &meson8b_vclk2_div4_div_gate.hw,
3139                 [CLKID_VCLK2_DIV6_DIV]      = &meson8b_vclk2_div6_div.hw,
3140                 [CLKID_VCLK2_DIV6]          = &meson8b_vclk2_div6_div_gate.hw,
3141                 [CLKID_VCLK2_DIV12_DIV]     = &meson8b_vclk2_div12_div.hw,
3142                 [CLKID_VCLK2_DIV12]         = &meson8b_vclk2_div12_div_gate.hw,
3143                 [CLKID_CTS_ENCT_SEL]        = &meson8b_cts_enct_sel.hw,
3144                 [CLKID_CTS_ENCT]            = &meson8b_cts_enct.hw,
3145                 [CLKID_CTS_ENCP_SEL]        = &meson8b_cts_encp_sel.hw,
3146                 [CLKID_CTS_ENCP]            = &meson8b_cts_encp.hw,
3147                 [CLKID_CTS_ENCI_SEL]        = &meson8b_cts_enci_sel.hw,
3148                 [CLKID_CTS_ENCI]            = &meson8b_cts_enci.hw,
3149                 [CLKID_HDMI_TX_PIXEL_SEL]   = &meson8b_hdmi_tx_pixel_sel.hw,
3150                 [CLKID_HDMI_TX_PIXEL]       = &meson8b_hdmi_tx_pixel.hw,
3151                 [CLKID_CTS_ENCL_SEL]        = &meson8b_cts_encl_sel.hw,
3152                 [CLKID_CTS_ENCL]            = &meson8b_cts_encl.hw,
3153                 [CLKID_CTS_VDAC0_SEL]       = &meson8b_cts_vdac0_sel.hw,
3154                 [CLKID_CTS_VDAC0]           = &meson8b_cts_vdac0.hw,
3155                 [CLKID_HDMI_SYS_SEL]        = &meson8b_hdmi_sys_sel.hw,
3156                 [CLKID_HDMI_SYS_DIV]        = &meson8b_hdmi_sys_div.hw,
3157                 [CLKID_HDMI_SYS]            = &meson8b_hdmi_sys.hw,
3158                 [CLKID_MALI_0_SEL]          = &meson8b_mali_0_sel.hw,
3159                 [CLKID_MALI_0_DIV]          = &meson8b_mali_0_div.hw,
3160                 [CLKID_MALI_0]              = &meson8b_mali_0.hw,
3161                 [CLKID_MALI_1_SEL]          = &meson8b_mali_1_sel.hw,
3162                 [CLKID_MALI_1_DIV]          = &meson8b_mali_1_div.hw,
3163                 [CLKID_MALI_1]              = &meson8b_mali_1.hw,
3164                 [CLKID_MALI]                = &meson8b_mali.hw,
3165                 [CLKID_VPU_0_SEL]           = &meson8b_vpu_0_sel.hw,
3166                 [CLKID_VPU_0_DIV]           = &meson8b_vpu_0_div.hw,
3167                 [CLKID_VPU_0]               = &meson8b_vpu_0.hw,
3168                 [CLKID_VPU_1_SEL]           = &meson8b_vpu_1_sel.hw,
3169                 [CLKID_VPU_1_DIV]           = &meson8b_vpu_1_div.hw,
3170                 [CLKID_VPU_1]               = &meson8b_vpu_1.hw,
3171                 [CLKID_VPU]                 = &meson8b_vpu.hw,
3172                 [CLKID_VDEC_1_SEL]          = &meson8b_vdec_1_sel.hw,
3173                 [CLKID_VDEC_1_1_DIV]        = &meson8b_vdec_1_1_div.hw,
3174                 [CLKID_VDEC_1_1]            = &meson8b_vdec_1_1.hw,
3175                 [CLKID_VDEC_1_2_DIV]        = &meson8b_vdec_1_2_div.hw,
3176                 [CLKID_VDEC_1_2]            = &meson8b_vdec_1_2.hw,
3177                 [CLKID_VDEC_1]              = &meson8b_vdec_1.hw,
3178                 [CLKID_VDEC_HCODEC_SEL]     = &meson8b_vdec_hcodec_sel.hw,
3179                 [CLKID_VDEC_HCODEC_DIV]     = &meson8b_vdec_hcodec_div.hw,
3180                 [CLKID_VDEC_HCODEC]         = &meson8b_vdec_hcodec.hw,
3181                 [CLKID_VDEC_2_SEL]          = &meson8b_vdec_2_sel.hw,
3182                 [CLKID_VDEC_2_DIV]          = &meson8b_vdec_2_div.hw,
3183                 [CLKID_VDEC_2]              = &meson8b_vdec_2.hw,
3184                 [CLKID_VDEC_HEVC_SEL]       = &meson8b_vdec_hevc_sel.hw,
3185                 [CLKID_VDEC_HEVC_DIV]       = &meson8b_vdec_hevc_div.hw,
3186                 [CLKID_VDEC_HEVC_EN]        = &meson8b_vdec_hevc_en.hw,
3187                 [CLKID_VDEC_HEVC]           = &meson8b_vdec_hevc.hw,
3188                 [CLKID_CTS_AMCLK_SEL]       = &meson8b_cts_amclk_sel.hw,
3189                 [CLKID_CTS_AMCLK_DIV]       = &meson8b_cts_amclk_div.hw,
3190                 [CLKID_CTS_AMCLK]           = &meson8b_cts_amclk.hw,
3191                 [CLKID_CTS_MCLK_I958_SEL]   = &meson8b_cts_mclk_i958_sel.hw,
3192                 [CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,
3193                 [CLKID_CTS_MCLK_I958]       = &meson8b_cts_mclk_i958.hw,
3194                 [CLKID_CTS_I958]            = &meson8b_cts_i958.hw,
3195                 [CLKID_VID_PLL_LVDS_EN]     = &meson8b_vid_pll_lvds_en.hw,
3196                 [CLKID_HDMI_PLL_DCO_IN]     = &hdmi_pll_dco_in.hw,
3197                 [CLK_NR_CLKS]               = NULL,
3198         },
3199         .num = CLK_NR_CLKS,
3200 };
3201
3202 static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
3203         .hws = {
3204                 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
3205                 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
3206                 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
3207                 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
3208                 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
3209                 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
3210                 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
3211                 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
3212                 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
3213                 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
3214                 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
3215                 [CLKID_CLK81] = &meson8b_clk81.hw,
3216                 [CLKID_DDR]                 = &meson8b_ddr.hw,
3217                 [CLKID_DOS]                 = &meson8b_dos.hw,
3218                 [CLKID_ISA]                 = &meson8b_isa.hw,
3219                 [CLKID_PL301]               = &meson8b_pl301.hw,
3220                 [CLKID_PERIPHS]             = &meson8b_periphs.hw,
3221                 [CLKID_SPICC]               = &meson8b_spicc.hw,
3222                 [CLKID_I2C]                 = &meson8b_i2c.hw,
3223                 [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
3224                 [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
3225                 [CLKID_RNG0]                = &meson8b_rng0.hw,
3226                 [CLKID_UART0]               = &meson8b_uart0.hw,
3227                 [CLKID_SDHC]                = &meson8b_sdhc.hw,
3228                 [CLKID_STREAM]              = &meson8b_stream.hw,
3229                 [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
3230                 [CLKID_SDIO]                = &meson8b_sdio.hw,
3231                 [CLKID_ABUF]                = &meson8b_abuf.hw,
3232                 [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
3233                 [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
3234                 [CLKID_SPI]                 = &meson8b_spi.hw,
3235                 [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
3236                 [CLKID_ETH]                 = &meson8b_eth.hw,
3237                 [CLKID_DEMUX]               = &meson8b_demux.hw,
3238                 [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
3239                 [CLKID_IEC958]              = &meson8b_iec958.hw,
3240                 [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
3241                 [CLKID_AMCLK]               = &meson8b_amclk.hw,
3242                 [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
3243                 [CLKID_MIXER]               = &meson8b_mixer.hw,
3244                 [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
3245                 [CLKID_ADC]                 = &meson8b_adc.hw,
3246                 [CLKID_BLKMV]               = &meson8b_blkmv.hw,
3247                 [CLKID_AIU]                 = &meson8b_aiu.hw,
3248                 [CLKID_UART1]               = &meson8b_uart1.hw,
3249                 [CLKID_G2D]                 = &meson8b_g2d.hw,
3250                 [CLKID_USB0]                = &meson8b_usb0.hw,
3251                 [CLKID_USB1]                = &meson8b_usb1.hw,
3252                 [CLKID_RESET]               = &meson8b_reset.hw,
3253                 [CLKID_NAND]                = &meson8b_nand.hw,
3254                 [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
3255                 [CLKID_USB]                 = &meson8b_usb.hw,
3256                 [CLKID_VDIN1]               = &meson8b_vdin1.hw,
3257                 [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
3258                 [CLKID_EFUSE]               = &meson8b_efuse.hw,
3259                 [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
3260                 [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
3261                 [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
3262                 [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
3263                 [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
3264                 [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
3265                 [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
3266                 [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
3267                 [CLKID_DVIN]                = &meson8b_dvin.hw,
3268                 [CLKID_UART2]               = &meson8b_uart2.hw,
3269                 [CLKID_SANA]                = &meson8b_sana.hw,
3270                 [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
3271                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
3272                 [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
3273                 [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
3274                 [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
3275                 [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
3276                 [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
3277                 [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
3278                 [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
3279                 [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
3280                 [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
3281                 [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
3282                 [CLKID_ENC480P]             = &meson8b_enc480p.hw,
3283                 [CLKID_RNG1]                = &meson8b_rng1.hw,
3284                 [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
3285                 [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
3286                 [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
3287                 [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
3288                 [CLKID_EDP]                 = &meson8b_edp.hw,
3289                 [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
3290                 [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
3291                 [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
3292                 [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
3293                 [CLKID_MPLL0]               = &meson8b_mpll0.hw,
3294                 [CLKID_MPLL1]               = &meson8b_mpll1.hw,
3295                 [CLKID_MPLL2]               = &meson8b_mpll2.hw,
3296                 [CLKID_MPLL0_DIV]           = &meson8b_mpll0_div.hw,
3297                 [CLKID_MPLL1_DIV]           = &meson8b_mpll1_div.hw,
3298                 [CLKID_MPLL2_DIV]           = &meson8b_mpll2_div.hw,
3299                 [CLKID_CPU_IN_SEL]          = &meson8b_cpu_in_sel.hw,
3300                 [CLKID_CPU_IN_DIV2]         = &meson8b_cpu_in_div2.hw,
3301                 [CLKID_CPU_IN_DIV3]         = &meson8b_cpu_in_div3.hw,
3302                 [CLKID_CPU_SCALE_DIV]       = &meson8b_cpu_scale_div.hw,
3303                 [CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
3304                 [CLKID_MPLL_PREDIV]         = &meson8b_mpll_prediv.hw,
3305                 [CLKID_FCLK_DIV2_DIV]       = &meson8b_fclk_div2_div.hw,
3306                 [CLKID_FCLK_DIV3_DIV]       = &meson8b_fclk_div3_div.hw,
3307                 [CLKID_FCLK_DIV4_DIV]       = &meson8b_fclk_div4_div.hw,
3308                 [CLKID_FCLK_DIV5_DIV]       = &meson8b_fclk_div5_div.hw,
3309                 [CLKID_FCLK_DIV7_DIV]       = &meson8b_fclk_div7_div.hw,
3310                 [CLKID_NAND_SEL]            = &meson8b_nand_clk_sel.hw,
3311                 [CLKID_NAND_DIV]            = &meson8b_nand_clk_div.hw,
3312                 [CLKID_NAND_CLK]            = &meson8b_nand_clk_gate.hw,
3313                 [CLKID_PLL_FIXED_DCO]       = &meson8b_fixed_pll_dco.hw,
3314                 [CLKID_HDMI_PLL_DCO]        = &meson8b_hdmi_pll_dco.hw,
3315                 [CLKID_PLL_SYS_DCO]         = &meson8b_sys_pll_dco.hw,
3316                 [CLKID_CPU_CLK_DIV2]        = &meson8b_cpu_clk_div2.hw,
3317                 [CLKID_CPU_CLK_DIV3]        = &meson8b_cpu_clk_div3.hw,
3318                 [CLKID_CPU_CLK_DIV4]        = &meson8b_cpu_clk_div4.hw,
3319                 [CLKID_CPU_CLK_DIV5]        = &meson8b_cpu_clk_div5.hw,
3320                 [CLKID_CPU_CLK_DIV6]        = &meson8b_cpu_clk_div6.hw,
3321                 [CLKID_CPU_CLK_DIV7]        = &meson8b_cpu_clk_div7.hw,
3322                 [CLKID_CPU_CLK_DIV8]        = &meson8b_cpu_clk_div8.hw,
3323                 [CLKID_APB_SEL]             = &meson8b_apb_clk_sel.hw,
3324                 [CLKID_APB]                 = &meson8b_apb_clk_gate.hw,
3325                 [CLKID_PERIPH_SEL]          = &meson8b_periph_clk_sel.hw,
3326                 [CLKID_PERIPH]              = &meson8b_periph_clk_gate.hw,
3327                 [CLKID_AXI_SEL]             = &meson8b_axi_clk_sel.hw,
3328                 [CLKID_AXI]                 = &meson8b_axi_clk_gate.hw,
3329                 [CLKID_L2_DRAM_SEL]         = &meson8b_l2_dram_clk_sel.hw,
3330                 [CLKID_L2_DRAM]             = &meson8b_l2_dram_clk_gate.hw,
3331                 [CLKID_HDMI_PLL_LVDS_OUT]   = &meson8b_hdmi_pll_lvds_out.hw,
3332                 [CLKID_HDMI_PLL_HDMI_OUT]   = &meson8b_hdmi_pll_hdmi_out.hw,
3333                 [CLKID_VID_PLL_IN_SEL]      = &meson8b_vid_pll_in_sel.hw,
3334                 [CLKID_VID_PLL_IN_EN]       = &meson8b_vid_pll_in_en.hw,
3335                 [CLKID_VID_PLL_PRE_DIV]     = &meson8b_vid_pll_pre_div.hw,
3336                 [CLKID_VID_PLL_POST_DIV]    = &meson8b_vid_pll_post_div.hw,
3337                 [CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,
3338                 [CLKID_VCLK_IN_SEL]         = &meson8b_vclk_in_sel.hw,
3339                 [CLKID_VCLK_IN_EN]          = &meson8b_vclk_in_en.hw,
3340                 [CLKID_VCLK_EN]             = &meson8b_vclk_en.hw,
3341                 [CLKID_VCLK_DIV1]           = &meson8b_vclk_div1_gate.hw,
3342                 [CLKID_VCLK_DIV2_DIV]       = &meson8b_vclk_div2_div.hw,
3343                 [CLKID_VCLK_DIV2]           = &meson8b_vclk_div2_div_gate.hw,
3344                 [CLKID_VCLK_DIV4_DIV]       = &meson8b_vclk_div4_div.hw,
3345                 [CLKID_VCLK_DIV4]           = &meson8b_vclk_div4_div_gate.hw,
3346                 [CLKID_VCLK_DIV6_DIV]       = &meson8b_vclk_div6_div.hw,
3347                 [CLKID_VCLK_DIV6]           = &meson8b_vclk_div6_div_gate.hw,
3348                 [CLKID_VCLK_DIV12_DIV]      = &meson8b_vclk_div12_div.hw,
3349                 [CLKID_VCLK_DIV12]          = &meson8b_vclk_div12_div_gate.hw,
3350                 [CLKID_VCLK2_IN_SEL]        = &meson8b_vclk2_in_sel.hw,
3351                 [CLKID_VCLK2_IN_EN]         = &meson8b_vclk2_clk_in_en.hw,
3352                 [CLKID_VCLK2_EN]            = &meson8b_vclk2_clk_en.hw,
3353                 [CLKID_VCLK2_DIV1]          = &meson8b_vclk2_div1_gate.hw,
3354                 [CLKID_VCLK2_DIV2_DIV]      = &meson8b_vclk2_div2_div.hw,
3355                 [CLKID_VCLK2_DIV2]          = &meson8b_vclk2_div2_div_gate.hw,
3356                 [CLKID_VCLK2_DIV4_DIV]      = &meson8b_vclk2_div4_div.hw,
3357                 [CLKID_VCLK2_DIV4]          = &meson8b_vclk2_div4_div_gate.hw,
3358                 [CLKID_VCLK2_DIV6_DIV]      = &meson8b_vclk2_div6_div.hw,
3359                 [CLKID_VCLK2_DIV6]          = &meson8b_vclk2_div6_div_gate.hw,
3360                 [CLKID_VCLK2_DIV12_DIV]     = &meson8b_vclk2_div12_div.hw,
3361                 [CLKID_VCLK2_DIV12]         = &meson8b_vclk2_div12_div_gate.hw,
3362                 [CLKID_CTS_ENCT_SEL]        = &meson8b_cts_enct_sel.hw,
3363                 [CLKID_CTS_ENCT]            = &meson8b_cts_enct.hw,
3364                 [CLKID_CTS_ENCP_SEL]        = &meson8b_cts_encp_sel.hw,
3365                 [CLKID_CTS_ENCP]            = &meson8b_cts_encp.hw,
3366                 [CLKID_CTS_ENCI_SEL]        = &meson8b_cts_enci_sel.hw,
3367                 [CLKID_CTS_ENCI]            = &meson8b_cts_enci.hw,
3368                 [CLKID_HDMI_TX_PIXEL_SEL]   = &meson8b_hdmi_tx_pixel_sel.hw,
3369                 [CLKID_HDMI_TX_PIXEL]       = &meson8b_hdmi_tx_pixel.hw,
3370                 [CLKID_CTS_ENCL_SEL]        = &meson8b_cts_encl_sel.hw,
3371                 [CLKID_CTS_ENCL]            = &meson8b_cts_encl.hw,
3372                 [CLKID_CTS_VDAC0_SEL]       = &meson8b_cts_vdac0_sel.hw,
3373                 [CLKID_CTS_VDAC0]           = &meson8b_cts_vdac0.hw,
3374                 [CLKID_HDMI_SYS_SEL]        = &meson8b_hdmi_sys_sel.hw,
3375                 [CLKID_HDMI_SYS_DIV]        = &meson8b_hdmi_sys_div.hw,
3376                 [CLKID_HDMI_SYS]            = &meson8b_hdmi_sys.hw,
3377                 [CLKID_MALI_0_SEL]          = &meson8b_mali_0_sel.hw,
3378                 [CLKID_MALI_0_DIV]          = &meson8b_mali_0_div.hw,
3379                 [CLKID_MALI_0]              = &meson8b_mali_0.hw,
3380                 [CLKID_MALI_1_SEL]          = &meson8b_mali_1_sel.hw,
3381                 [CLKID_MALI_1_DIV]          = &meson8b_mali_1_div.hw,
3382                 [CLKID_MALI_1]              = &meson8b_mali_1.hw,
3383                 [CLKID_MALI]                = &meson8b_mali.hw,
3384                 [CLKID_GP_PLL_DCO]          = &meson8m2_gp_pll_dco.hw,
3385                 [CLKID_GP_PLL]              = &meson8m2_gp_pll.hw,
3386                 [CLKID_VPU_0_SEL]           = &meson8m2_vpu_0_sel.hw,
3387                 [CLKID_VPU_0_DIV]           = &meson8b_vpu_0_div.hw,
3388                 [CLKID_VPU_0]               = &meson8b_vpu_0.hw,
3389                 [CLKID_VPU_1_SEL]           = &meson8m2_vpu_1_sel.hw,
3390                 [CLKID_VPU_1_DIV]           = &meson8b_vpu_1_div.hw,
3391                 [CLKID_VPU_1]               = &meson8b_vpu_1.hw,
3392                 [CLKID_VPU]                 = &meson8b_vpu.hw,
3393                 [CLKID_VDEC_1_SEL]          = &meson8b_vdec_1_sel.hw,
3394                 [CLKID_VDEC_1_1_DIV]        = &meson8b_vdec_1_1_div.hw,
3395                 [CLKID_VDEC_1_1]            = &meson8b_vdec_1_1.hw,
3396                 [CLKID_VDEC_1_2_DIV]        = &meson8b_vdec_1_2_div.hw,
3397                 [CLKID_VDEC_1_2]            = &meson8b_vdec_1_2.hw,
3398                 [CLKID_VDEC_1]              = &meson8b_vdec_1.hw,
3399                 [CLKID_VDEC_HCODEC_SEL]     = &meson8b_vdec_hcodec_sel.hw,
3400                 [CLKID_VDEC_HCODEC_DIV]     = &meson8b_vdec_hcodec_div.hw,
3401                 [CLKID_VDEC_HCODEC]         = &meson8b_vdec_hcodec.hw,
3402                 [CLKID_VDEC_2_SEL]          = &meson8b_vdec_2_sel.hw,
3403                 [CLKID_VDEC_2_DIV]          = &meson8b_vdec_2_div.hw,
3404                 [CLKID_VDEC_2]              = &meson8b_vdec_2.hw,
3405                 [CLKID_VDEC_HEVC_SEL]       = &meson8b_vdec_hevc_sel.hw,
3406                 [CLKID_VDEC_HEVC_DIV]       = &meson8b_vdec_hevc_div.hw,
3407                 [CLKID_VDEC_HEVC_EN]        = &meson8b_vdec_hevc_en.hw,
3408                 [CLKID_VDEC_HEVC]           = &meson8b_vdec_hevc.hw,
3409                 [CLKID_CTS_AMCLK_SEL]       = &meson8b_cts_amclk_sel.hw,
3410                 [CLKID_CTS_AMCLK_DIV]       = &meson8b_cts_amclk_div.hw,
3411                 [CLKID_CTS_AMCLK]           = &meson8b_cts_amclk.hw,
3412                 [CLKID_CTS_MCLK_I958_SEL]   = &meson8b_cts_mclk_i958_sel.hw,
3413                 [CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,
3414                 [CLKID_CTS_MCLK_I958]       = &meson8b_cts_mclk_i958.hw,
3415                 [CLKID_CTS_I958]            = &meson8b_cts_i958.hw,
3416                 [CLKID_VID_PLL_LVDS_EN]     = &meson8b_vid_pll_lvds_en.hw,
3417                 [CLKID_HDMI_PLL_DCO_IN]     = &hdmi_pll_dco_in.hw,
3418                 [CLK_NR_CLKS]               = NULL,
3419         },
3420         .num = CLK_NR_CLKS,
3421 };
3422
3423 static struct clk_regmap *const meson8b_clk_regmaps[] = {
3424         &meson8b_clk81,
3425         &meson8b_ddr,
3426         &meson8b_dos,
3427         &meson8b_isa,
3428         &meson8b_pl301,
3429         &meson8b_periphs,
3430         &meson8b_spicc,
3431         &meson8b_i2c,
3432         &meson8b_sar_adc,
3433         &meson8b_smart_card,
3434         &meson8b_rng0,
3435         &meson8b_uart0,
3436         &meson8b_sdhc,
3437         &meson8b_stream,
3438         &meson8b_async_fifo,
3439         &meson8b_sdio,
3440         &meson8b_abuf,
3441         &meson8b_hiu_iface,
3442         &meson8b_assist_misc,
3443         &meson8b_spi,
3444         &meson8b_i2s_spdif,
3445         &meson8b_eth,
3446         &meson8b_demux,
3447         &meson8b_aiu_glue,
3448         &meson8b_iec958,
3449         &meson8b_i2s_out,
3450         &meson8b_amclk,
3451         &meson8b_aififo2,
3452         &meson8b_mixer,
3453         &meson8b_mixer_iface,
3454         &meson8b_adc,
3455         &meson8b_blkmv,
3456         &meson8b_aiu,
3457         &meson8b_uart1,
3458         &meson8b_g2d,
3459         &meson8b_usb0,
3460         &meson8b_usb1,
3461         &meson8b_reset,
3462         &meson8b_nand,
3463         &meson8b_dos_parser,
3464         &meson8b_usb,
3465         &meson8b_vdin1,
3466         &meson8b_ahb_arb0,
3467         &meson8b_efuse,
3468         &meson8b_boot_rom,
3469         &meson8b_ahb_data_bus,
3470         &meson8b_ahb_ctrl_bus,
3471         &meson8b_hdmi_intr_sync,
3472         &meson8b_hdmi_pclk,
3473         &meson8b_usb1_ddr_bridge,
3474         &meson8b_usb0_ddr_bridge,
3475         &meson8b_mmc_pclk,
3476         &meson8b_dvin,
3477         &meson8b_uart2,
3478         &meson8b_sana,
3479         &meson8b_vpu_intr,
3480         &meson8b_sec_ahb_ahb3_bridge,
3481         &meson8b_clk81_a9,
3482         &meson8b_vclk2_venci0,
3483         &meson8b_vclk2_venci1,
3484         &meson8b_vclk2_vencp0,
3485         &meson8b_vclk2_vencp1,
3486         &meson8b_gclk_venci_int,
3487         &meson8b_gclk_vencp_int,
3488         &meson8b_dac_clk,
3489         &meson8b_aoclk_gate,
3490         &meson8b_iec958_gate,
3491         &meson8b_enc480p,
3492         &meson8b_rng1,
3493         &meson8b_gclk_vencl_int,
3494         &meson8b_vclk2_venclmcc,
3495         &meson8b_vclk2_vencl,
3496         &meson8b_vclk2_other,
3497         &meson8b_edp,
3498         &meson8b_ao_media_cpu,
3499         &meson8b_ao_ahb_sram,
3500         &meson8b_ao_ahb_bus,
3501         &meson8b_ao_iface,
3502         &meson8b_mpeg_clk_div,
3503         &meson8b_mpeg_clk_sel,
3504         &meson8b_mpll0,
3505         &meson8b_mpll1,
3506         &meson8b_mpll2,
3507         &meson8b_mpll0_div,
3508         &meson8b_mpll1_div,
3509         &meson8b_mpll2_div,
3510         &meson8b_fixed_pll,
3511         &meson8b_sys_pll,
3512         &meson8b_cpu_in_sel,
3513         &meson8b_cpu_scale_div,
3514         &meson8b_cpu_scale_out_sel,
3515         &meson8b_cpu_clk,
3516         &meson8b_mpll_prediv,
3517         &meson8b_fclk_div2,
3518         &meson8b_fclk_div3,
3519         &meson8b_fclk_div4,
3520         &meson8b_fclk_div5,
3521         &meson8b_fclk_div7,
3522         &meson8b_nand_clk_sel,
3523         &meson8b_nand_clk_div,
3524         &meson8b_nand_clk_gate,
3525         &meson8b_fixed_pll_dco,
3526         &meson8b_hdmi_pll_dco,
3527         &meson8b_sys_pll_dco,
3528         &meson8b_apb_clk_sel,
3529         &meson8b_apb_clk_gate,
3530         &meson8b_periph_clk_sel,
3531         &meson8b_periph_clk_gate,
3532         &meson8b_axi_clk_sel,
3533         &meson8b_axi_clk_gate,
3534         &meson8b_l2_dram_clk_sel,
3535         &meson8b_l2_dram_clk_gate,
3536         &meson8b_hdmi_pll_lvds_out,
3537         &meson8b_hdmi_pll_hdmi_out,
3538         &meson8b_vid_pll_in_sel,
3539         &meson8b_vid_pll_in_en,
3540         &meson8b_vid_pll_pre_div,
3541         &meson8b_vid_pll_post_div,
3542         &meson8b_vid_pll,
3543         &meson8b_vid_pll_final_div,
3544         &meson8b_vclk_in_sel,
3545         &meson8b_vclk_in_en,
3546         &meson8b_vclk_en,
3547         &meson8b_vclk_div1_gate,
3548         &meson8b_vclk_div2_div_gate,
3549         &meson8b_vclk_div4_div_gate,
3550         &meson8b_vclk_div6_div_gate,
3551         &meson8b_vclk_div12_div_gate,
3552         &meson8b_vclk2_in_sel,
3553         &meson8b_vclk2_clk_in_en,
3554         &meson8b_vclk2_clk_en,
3555         &meson8b_vclk2_div1_gate,
3556         &meson8b_vclk2_div2_div_gate,
3557         &meson8b_vclk2_div4_div_gate,
3558         &meson8b_vclk2_div6_div_gate,
3559         &meson8b_vclk2_div12_div_gate,
3560         &meson8b_cts_enct_sel,
3561         &meson8b_cts_enct,
3562         &meson8b_cts_encp_sel,
3563         &meson8b_cts_encp,
3564         &meson8b_cts_enci_sel,
3565         &meson8b_cts_enci,
3566         &meson8b_hdmi_tx_pixel_sel,
3567         &meson8b_hdmi_tx_pixel,
3568         &meson8b_cts_encl_sel,
3569         &meson8b_cts_encl,
3570         &meson8b_cts_vdac0_sel,
3571         &meson8b_cts_vdac0,
3572         &meson8b_hdmi_sys_sel,
3573         &meson8b_hdmi_sys_div,
3574         &meson8b_hdmi_sys,
3575         &meson8b_mali_0_sel,
3576         &meson8b_mali_0_div,
3577         &meson8b_mali_0,
3578         &meson8b_mali_1_sel,
3579         &meson8b_mali_1_div,
3580         &meson8b_mali_1,
3581         &meson8b_mali,
3582         &meson8m2_gp_pll_dco,
3583         &meson8m2_gp_pll,
3584         &meson8b_vpu_0_sel,
3585         &meson8m2_vpu_0_sel,
3586         &meson8b_vpu_0_div,
3587         &meson8b_vpu_0,
3588         &meson8b_vpu_1_sel,
3589         &meson8m2_vpu_1_sel,
3590         &meson8b_vpu_1_div,
3591         &meson8b_vpu_1,
3592         &meson8b_vpu,
3593         &meson8b_vdec_1_sel,
3594         &meson8b_vdec_1_1_div,
3595         &meson8b_vdec_1_1,
3596         &meson8b_vdec_1_2_div,
3597         &meson8b_vdec_1_2,
3598         &meson8b_vdec_1,
3599         &meson8b_vdec_hcodec_sel,
3600         &meson8b_vdec_hcodec_div,
3601         &meson8b_vdec_hcodec,
3602         &meson8b_vdec_2_sel,
3603         &meson8b_vdec_2_div,
3604         &meson8b_vdec_2,
3605         &meson8b_vdec_hevc_sel,
3606         &meson8b_vdec_hevc_div,
3607         &meson8b_vdec_hevc_en,
3608         &meson8b_vdec_hevc,
3609         &meson8b_cts_amclk,
3610         &meson8b_cts_amclk_sel,
3611         &meson8b_cts_amclk_div,
3612         &meson8b_cts_mclk_i958_sel,
3613         &meson8b_cts_mclk_i958_div,
3614         &meson8b_cts_mclk_i958,
3615         &meson8b_cts_i958,
3616         &meson8b_vid_pll_lvds_en,
3617 };
3618
3619 static const struct meson8b_clk_reset_line {
3620         u32 reg;
3621         u8 bit_idx;
3622         bool active_low;
3623 } meson8b_clk_reset_bits[] = {
3624         [CLKC_RESET_L2_CACHE_SOFT_RESET] = {
3625                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3626                 .bit_idx = 30,
3627                 .active_low = false,
3628         },
3629         [CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
3630                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3631                 .bit_idx = 29,
3632                 .active_low = false,
3633         },
3634         [CLKC_RESET_SCU_SOFT_RESET] = {
3635                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3636                 .bit_idx = 28,
3637                 .active_low = false,
3638         },
3639         [CLKC_RESET_CPU3_SOFT_RESET] = {
3640                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3641                 .bit_idx = 27,
3642                 .active_low = false,
3643         },
3644         [CLKC_RESET_CPU2_SOFT_RESET] = {
3645                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3646                 .bit_idx = 26,
3647                 .active_low = false,
3648         },
3649         [CLKC_RESET_CPU1_SOFT_RESET] = {
3650                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3651                 .bit_idx = 25,
3652                 .active_low = false,
3653         },
3654         [CLKC_RESET_CPU0_SOFT_RESET] = {
3655                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3656                 .bit_idx = 24,
3657                 .active_low = false,
3658         },
3659         [CLKC_RESET_A5_GLOBAL_RESET] = {
3660                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3661                 .bit_idx = 18,
3662                 .active_low = false,
3663         },
3664         [CLKC_RESET_A5_AXI_SOFT_RESET] = {
3665                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3666                 .bit_idx = 17,
3667                 .active_low = false,
3668         },
3669         [CLKC_RESET_A5_ABP_SOFT_RESET] = {
3670                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3671                 .bit_idx = 16,
3672                 .active_low = false,
3673         },
3674         [CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
3675                 .reg = HHI_SYS_CPU_CLK_CNTL1,
3676                 .bit_idx = 30,
3677                 .active_low = false,
3678         },
3679         [CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
3680                 .reg = HHI_VID_CLK_CNTL,
3681                 .bit_idx = 15,
3682                 .active_low = false,
3683         },
3684         [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
3685                 .reg = HHI_VID_DIVIDER_CNTL,
3686                 .bit_idx = 7,
3687                 .active_low = false,
3688         },
3689         [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
3690                 .reg = HHI_VID_DIVIDER_CNTL,
3691                 .bit_idx = 3,
3692                 .active_low = false,
3693         },
3694         [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
3695                 .reg = HHI_VID_DIVIDER_CNTL,
3696                 .bit_idx = 1,
3697                 .active_low = true,
3698         },
3699         [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
3700                 .reg = HHI_VID_DIVIDER_CNTL,
3701                 .bit_idx = 0,
3702                 .active_low = true,
3703         },
3704 };
3705
3706 static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
3707                                     unsigned long id, bool assert)
3708 {
3709         struct meson8b_clk_reset *meson8b_clk_reset =
3710                 container_of(rcdev, struct meson8b_clk_reset, reset);
3711         const struct meson8b_clk_reset_line *reset;
3712         unsigned int value = 0;
3713         unsigned long flags;
3714
3715         if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
3716                 return -EINVAL;
3717
3718         reset = &meson8b_clk_reset_bits[id];
3719
3720         if (assert != reset->active_low)
3721                 value = BIT(reset->bit_idx);
3722
3723         spin_lock_irqsave(&meson_clk_lock, flags);
3724
3725         regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
3726                            BIT(reset->bit_idx), value);
3727
3728         spin_unlock_irqrestore(&meson_clk_lock, flags);
3729
3730         return 0;
3731 }
3732
3733 static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev,
3734                                      unsigned long id)
3735 {
3736         return meson8b_clk_reset_update(rcdev, id, true);
3737 }
3738
3739 static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev,
3740                                        unsigned long id)
3741 {
3742         return meson8b_clk_reset_update(rcdev, id, false);
3743 }
3744
3745 static const struct reset_control_ops meson8b_clk_reset_ops = {
3746         .assert = meson8b_clk_reset_assert,
3747         .deassert = meson8b_clk_reset_deassert,
3748 };
3749
3750 struct meson8b_nb_data {
3751         struct notifier_block nb;
3752         struct clk_hw *cpu_clk;
3753 };
3754
3755 static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb,
3756                                        unsigned long event, void *data)
3757 {
3758         struct meson8b_nb_data *nb_data =
3759                 container_of(nb, struct meson8b_nb_data, nb);
3760         struct clk_hw *parent_clk;
3761         int ret;
3762
3763         switch (event) {
3764         case PRE_RATE_CHANGE:
3765                 /* xtal */
3766                 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0);
3767                 break;
3768
3769         case POST_RATE_CHANGE:
3770                 /* cpu_scale_out_sel */
3771                 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1);
3772                 break;
3773
3774         default:
3775                 return NOTIFY_DONE;
3776         }
3777
3778         ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk);
3779         if (ret)
3780                 return notifier_from_errno(ret);
3781
3782         udelay(100);
3783
3784         return NOTIFY_OK;
3785 }
3786
3787 static struct meson8b_nb_data meson8b_cpu_nb_data = {
3788         .nb.notifier_call = meson8b_cpu_clk_notifier_cb,
3789 };
3790
3791 static void __init meson8b_clkc_init_common(struct device_node *np,
3792                         struct clk_hw_onecell_data *clk_hw_onecell_data)
3793 {
3794         struct meson8b_clk_reset *rstc;
3795         struct device_node *parent_np;
3796         const char *notifier_clk_name;
3797         struct clk *notifier_clk;
3798         struct regmap *map;
3799         int i, ret;
3800
3801         parent_np = of_get_parent(np);
3802         map = syscon_node_to_regmap(parent_np);
3803         of_node_put(parent_np);
3804         if (IS_ERR(map)) {
3805                 pr_err("failed to get HHI regmap - Trying obsolete regs\n");
3806                 return;
3807         }
3808
3809         rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
3810         if (!rstc)
3811                 return;
3812
3813         /* Reset Controller */
3814         rstc->regmap = map;
3815         rstc->reset.ops = &meson8b_clk_reset_ops;
3816         rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits);
3817         rstc->reset.of_node = np;
3818         ret = reset_controller_register(&rstc->reset);
3819         if (ret) {
3820                 pr_err("%s: Failed to register clkc reset controller: %d\n",
3821                        __func__, ret);
3822                 return;
3823         }
3824
3825         /* Populate regmap for the regmap backed clocks */
3826         for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++)
3827                 meson8b_clk_regmaps[i]->map = map;
3828
3829         /*
3830          * register all clks and start with the first used ID (which is
3831          * CLKID_PLL_FIXED)
3832          */
3833         for (i = CLKID_PLL_FIXED; i < CLK_NR_CLKS; i++) {
3834                 /* array might be sparse */
3835                 if (!clk_hw_onecell_data->hws[i])
3836                         continue;
3837
3838                 ret = of_clk_hw_register(np, clk_hw_onecell_data->hws[i]);
3839                 if (ret)
3840                         return;
3841         }
3842
3843         meson8b_cpu_nb_data.cpu_clk = clk_hw_onecell_data->hws[CLKID_CPUCLK];
3844
3845         /*
3846          * FIXME we shouldn't program the muxes in notifier handlers. The
3847          * tricky programming sequence will be handled by the forthcoming
3848          * coordinated clock rates mechanism once that feature is released.
3849          */
3850         notifier_clk_name = clk_hw_get_name(&meson8b_cpu_scale_out_sel.hw);
3851         notifier_clk = __clk_lookup(notifier_clk_name);
3852         ret = clk_notifier_register(notifier_clk, &meson8b_cpu_nb_data.nb);
3853         if (ret) {
3854                 pr_err("%s: failed to register the CPU clock notifier\n",
3855                        __func__);
3856                 return;
3857         }
3858
3859         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
3860                                      clk_hw_onecell_data);
3861         if (ret)
3862                 pr_err("%s: failed to register clock provider\n", __func__);
3863 }
3864
3865 static void __init meson8_clkc_init(struct device_node *np)
3866 {
3867         return meson8b_clkc_init_common(np, &meson8_hw_onecell_data);
3868 }
3869
3870 static void __init meson8b_clkc_init(struct device_node *np)
3871 {
3872         return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data);
3873 }
3874
3875 static void __init meson8m2_clkc_init(struct device_node *np)
3876 {
3877         return meson8b_clkc_init_common(np, &meson8m2_hw_onecell_data);
3878 }
3879
3880 CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
3881                       meson8_clkc_init);
3882 CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
3883                       meson8b_clkc_init);
3884 CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
3885                       meson8m2_clkc_init);