drivers/clk/meson/gxbb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
   4  * (C) Copyright 2018 - BayLibre, SAS
   5  * Author: Neil Armstrong <narmstrong@baylibre.com>
   6  */
   7
   8 #include <common.h>
   9 #include <log.h>
  10 #include <asm/arch/clock-gx.h>
  11 #include <asm/io.h>
  12 #include <clk-uclass.h>
  13 #include <div64.h>
  14 #include <dm.h>
  15 #include <regmap.h>
  16 #include <syscon.h>
  17 #include <dt-bindings/clock/gxbb-clkc.h>
  18 #include "clk_meson.h"
  19 #include <linux/err.h>
  20
  21 /* This driver support only basic clock tree operations :
  22  * - Can calculate clock frequency on a limited tree
  23  * - Can Read muxes and basic dividers (0-based only)
  24  * - Can enable/disable gates with limited propagation
  25  * - Can reparent without propagation, only on muxes
  26  * - Can set rates without reparenting
  27  * This driver is adapted to what is actually supported by U-Boot
  28  */
  29
  30 /* Only the clocks ids we don't want to expose, such as the internal muxes
  31  * and dividers of composite clocks, will remain defined here.
  32  */
  33 #define CLKID_MPEG_SEL            10
  34 #define CLKID_MPEG_DIV            11
  35 #define CLKID_SAR_ADC_DIV         99
  36 #define CLKID_MALI_0_DIV          101
  37 #define CLKID_MALI_1_DIV          104
  38 #define CLKID_CTS_AMCLK_SEL       108
  39 #define CLKID_CTS_AMCLK_DIV       109
  40 #define CLKID_CTS_MCLK_I958_SEL   111
  41 #define CLKID_CTS_MCLK_I958_DIV   112
  42 #define CLKID_32K_CLK_SEL         115
  43 #define CLKID_32K_CLK_DIV         116
  44 #define CLKID_SD_EMMC_A_CLK0_SEL  117
  45 #define CLKID_SD_EMMC_A_CLK0_DIV  118
  46 #define CLKID_SD_EMMC_B_CLK0_SEL  120
  47 #define CLKID_SD_EMMC_B_CLK0_DIV  121
  48 #define CLKID_SD_EMMC_C_CLK0_SEL  123
  49 #define CLKID_SD_EMMC_C_CLK0_DIV  124
  50 #define CLKID_VPU_0_DIV           127
  51 #define CLKID_VPU_1_DIV           130
  52 #define CLKID_VAPB_0_DIV          134
  53 #define CLKID_VAPB_1_DIV          137
  54 #define CLKID_HDMI_PLL_PRE_MULT   141
  55 #define CLKID_MPLL0_DIV           142
  56 #define CLKID_MPLL1_DIV           143
  57 #define CLKID_MPLL2_DIV           144
  58 #define CLKID_MPLL_PREDIV         145
  59 #define CLKID_FCLK_DIV2_DIV       146
  60 #define CLKID_FCLK_DIV3_DIV       147
  61 #define CLKID_FCLK_DIV4_DIV       148
  62 #define CLKID_FCLK_DIV5_DIV       149
  63 #define CLKID_FCLK_DIV7_DIV       150
  64 #define CLKID_VDEC_1_SEL          151
  65 #define CLKID_VDEC_1_DIV          152
  66 #define CLKID_VDEC_HEVC_SEL       154
  67 #define CLKID_VDEC_HEVC_DIV       155
  68
  69 #define XTAL_RATE 24000000
  70
  71 struct meson_clk {
  72         struct regmap *map;
  73 };
  74
  75 static ulong meson_div_get_rate(struct clk *clk, unsigned long id);
  76 static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
  77                                 ulong current_rate);
  78 static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
  79                                   unsigned long parent_id);
  80 static ulong meson_mux_get_rate(struct clk *clk, unsigned long id);
  81 static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
  82                                       ulong rate, ulong current_rate);
  83 static ulong meson_mux_get_parent(struct clk *clk, unsigned long id);
  84 static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
  85
  86 static struct meson_gate gates[] = {
  87         /* Everything Else (EE) domain gates */
  88         MESON_GATE(CLKID_DDR, HHI_GCLK_MPEG0, 0),
  89         MESON_GATE(CLKID_DOS, HHI_GCLK_MPEG0, 1),
  90         MESON_GATE(CLKID_ISA, HHI_GCLK_MPEG0, 5),
  91         MESON_GATE(CLKID_PL301, HHI_GCLK_MPEG0, 6),
  92         MESON_GATE(CLKID_PERIPHS, HHI_GCLK_MPEG0, 7),
  93         MESON_GATE(CLKID_SPICC, HHI_GCLK_MPEG0, 8),
  94         MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
  95         MESON_GATE(CLKID_SAR_ADC, HHI_GCLK_MPEG0, 10),
  96         MESON_GATE(CLKID_SMART_CARD, HHI_GCLK_MPEG0, 11),
  97         MESON_GATE(CLKID_RNG0, HHI_GCLK_MPEG0, 12),
  98         MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
  99         MESON_GATE(CLKID_SDHC, HHI_GCLK_MPEG0, 14),
 100         MESON_GATE(CLKID_STREAM, HHI_GCLK_MPEG0, 15),
 101         MESON_GATE(CLKID_ASYNC_FIFO, HHI_GCLK_MPEG0, 16),
 102         MESON_GATE(CLKID_SDIO, HHI_GCLK_MPEG0, 17),
 103         MESON_GATE(CLKID_ABUF, HHI_GCLK_MPEG0, 18),
 104         MESON_GATE(CLKID_HIU_IFACE, HHI_GCLK_MPEG0, 19),
 105         MESON_GATE(CLKID_ASSIST_MISC, HHI_GCLK_MPEG0, 23),
 106         MESON_GATE(CLKID_SD_EMMC_A, HHI_GCLK_MPEG0, 24),
 107         MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
 108         MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
 109         MESON_GATE(CLKID_SPI, HHI_GCLK_MPEG0, 30),
 110
 111         MESON_GATE(CLKID_I2S_SPDIF, HHI_GCLK_MPEG1, 2),
 112         MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
 113         MESON_GATE(CLKID_DEMUX, HHI_GCLK_MPEG1, 4),
 114         MESON_GATE(CLKID_AIU_GLUE, HHI_GCLK_MPEG1, 6),
 115         MESON_GATE(CLKID_IEC958, HHI_GCLK_MPEG1, 7),
 116         MESON_GATE(CLKID_I2S_OUT, HHI_GCLK_MPEG1, 8),
 117         MESON_GATE(CLKID_AMCLK, HHI_GCLK_MPEG1, 9),
 118         MESON_GATE(CLKID_AIFIFO2, HHI_GCLK_MPEG1, 10),
 119         MESON_GATE(CLKID_MIXER, HHI_GCLK_MPEG1, 11),
 120         MESON_GATE(CLKID_MIXER_IFACE, HHI_GCLK_MPEG1, 12),
 121         MESON_GATE(CLKID_ADC, HHI_GCLK_MPEG1, 13),
 122         MESON_GATE(CLKID_BLKMV, HHI_GCLK_MPEG1, 14),
 123         MESON_GATE(CLKID_AIU, HHI_GCLK_MPEG1, 15),
 124         MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
 125         MESON_GATE(CLKID_G2D, HHI_GCLK_MPEG1, 20),
 126         MESON_GATE(CLKID_USB0, HHI_GCLK_MPEG1, 21),
 127         MESON_GATE(CLKID_USB1, HHI_GCLK_MPEG1, 22),
 128         MESON_GATE(CLKID_RESET, HHI_GCLK_MPEG1, 23),
 129         MESON_GATE(CLKID_NAND, HHI_GCLK_MPEG1, 24),
 130         MESON_GATE(CLKID_DOS_PARSER, HHI_GCLK_MPEG1, 25),
 131         MESON_GATE(CLKID_USB, HHI_GCLK_MPEG1, 26),
 132         MESON_GATE(CLKID_VDIN1, HHI_GCLK_MPEG1, 28),
 133         MESON_GATE(CLKID_AHB_ARB0, HHI_GCLK_MPEG1, 29),
 134         MESON_GATE(CLKID_EFUSE, HHI_GCLK_MPEG1, 30),
 135         MESON_GATE(CLKID_BOOT_ROM, HHI_GCLK_MPEG1, 31),
 136
 137         MESON_GATE(CLKID_AHB_DATA_BUS, HHI_GCLK_MPEG2, 1),
 138         MESON_GATE(CLKID_AHB_CTRL_BUS, HHI_GCLK_MPEG2, 2),
 139         MESON_GATE(CLKID_HDMI_INTR_SYNC, HHI_GCLK_MPEG2, 3),
 140         MESON_GATE(CLKID_HDMI_PCLK, HHI_GCLK_MPEG2, 4),
 141         MESON_GATE(CLKID_USB1_DDR_BRIDGE, HHI_GCLK_MPEG2, 8),
 142         MESON_GATE(CLKID_USB0_DDR_BRIDGE, HHI_GCLK_MPEG2, 9),
 143         MESON_GATE(CLKID_MMC_PCLK, HHI_GCLK_MPEG2, 11),
 144         MESON_GATE(CLKID_DVIN, HHI_GCLK_MPEG2, 12),
 145         MESON_GATE(CLKID_UART2, HHI_GCLK_MPEG2, 15),
 146         MESON_GATE(CLKID_SANA, HHI_GCLK_MPEG2, 22),
 147         MESON_GATE(CLKID_VPU_INTR, HHI_GCLK_MPEG2, 25),
 148         MESON_GATE(CLKID_SEC_AHB_AHB3_BRIDGE, HHI_GCLK_MPEG2, 26),
 149         MESON_GATE(CLKID_CLK81_A53, HHI_GCLK_MPEG2, 29),
 150
 151         MESON_GATE(CLKID_VCLK2_VENCI0, HHI_GCLK_OTHER, 1),
 152         MESON_GATE(CLKID_VCLK2_VENCI1, HHI_GCLK_OTHER, 2),
 153         MESON_GATE(CLKID_VCLK2_VENCP0, HHI_GCLK_OTHER, 3),
 154         MESON_GATE(CLKID_VCLK2_VENCP1, HHI_GCLK_OTHER, 4),
 155         MESON_GATE(CLKID_GCLK_VENCI_INT0, HHI_GCLK_OTHER, 8),
 156         MESON_GATE(CLKID_DAC_CLK, HHI_GCLK_OTHER, 10),
 157         MESON_GATE(CLKID_AOCLK_GATE, HHI_GCLK_OTHER, 14),
 158         MESON_GATE(CLKID_IEC958_GATE, HHI_GCLK_OTHER, 16),
 159         MESON_GATE(CLKID_ENC480P, HHI_GCLK_OTHER, 20),
 160         MESON_GATE(CLKID_RNG1, HHI_GCLK_OTHER, 21),
 161         MESON_GATE(CLKID_GCLK_VENCI_INT1, HHI_GCLK_OTHER, 22),
 162         MESON_GATE(CLKID_VCLK2_VENCLMCC, HHI_GCLK_OTHER, 24),
 163         MESON_GATE(CLKID_VCLK2_VENCL, HHI_GCLK_OTHER, 25),
 164         MESON_GATE(CLKID_VCLK_OTHER, HHI_GCLK_OTHER, 26),
 165         MESON_GATE(CLKID_EDP, HHI_GCLK_OTHER, 31),
 166
 167         /* Always On (AO) domain gates */
 168         MESON_GATE(CLKID_AO_MEDIA_CPU, HHI_GCLK_AO, 0),
 169         MESON_GATE(CLKID_AO_AHB_SRAM, HHI_GCLK_AO, 1),
 170         MESON_GATE(CLKID_AO_AHB_BUS, HHI_GCLK_AO, 2),
 171         MESON_GATE(CLKID_AO_IFACE, HHI_GCLK_AO, 3),
 172         MESON_GATE(CLKID_AO_I2C, HHI_GCLK_AO, 4),
 173
 174         /* PLL Gates */
 175         /* CLKID_FCLK_DIV2 is critical for the SCPI Processor */
 176         MESON_GATE(CLKID_FCLK_DIV3, HHI_MPLL_CNTL6, 28),
 177         MESON_GATE(CLKID_FCLK_DIV4, HHI_MPLL_CNTL6, 29),
 178         MESON_GATE(CLKID_FCLK_DIV5, HHI_MPLL_CNTL6, 30),
 179         MESON_GATE(CLKID_FCLK_DIV7, HHI_MPLL_CNTL6, 31),
 180         MESON_GATE(CLKID_MPLL0, HHI_MPLL_CNTL7, 14),
 181         MESON_GATE(CLKID_MPLL1, HHI_MPLL_CNTL8, 14),
 182         MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
 183         /* CLKID_CLK81 is critical for the system */
 184
 185         /* Peripheral Gates */
 186         MESON_GATE(CLKID_SAR_ADC_CLK, HHI_SAR_CLK_CNTL, 8),
 187         MESON_GATE(CLKID_SD_EMMC_A_CLK0, HHI_SD_EMMC_CLK_CNTL, 7),
 188         MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
 189         MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
 190         MESON_GATE(CLKID_VPU_0, HHI_VPU_CLK_CNTL, 8),
 191         MESON_GATE(CLKID_VPU_1, HHI_VPU_CLK_CNTL, 24),
 192         MESON_GATE(CLKID_VAPB_0, HHI_VAPBCLK_CNTL, 8),
 193         MESON_GATE(CLKID_VAPB_1, HHI_VAPBCLK_CNTL, 24),
 194         MESON_GATE(CLKID_VAPB, HHI_VAPBCLK_CNTL, 30),
 195 };
 196
 197 static int meson_set_gate_by_id(struct clk *clk, unsigned long id, bool on)
 198 {
 199         struct meson_clk *priv = dev_get_priv(clk->dev);
 200         struct meson_gate *gate;
 201
 202         debug("%s: %sabling %ld\n", __func__, on ? "en" : "dis", id);
 203
 204         /* Propagate through muxes */
 205         switch (id) {
 206         case CLKID_VPU:
 207                 return meson_set_gate_by_id(clk,
 208                                 meson_mux_get_parent(clk, CLKID_VPU), on);
 209         case CLKID_VAPB_SEL:
 210                 return meson_set_gate_by_id(clk,
 211                                 meson_mux_get_parent(clk, CLKID_VAPB_SEL), on);
 212         }
 213
 214         if (id >= ARRAY_SIZE(gates))
 215                 return -ENOENT;
 216
 217         gate = &gates[id];
 218
 219         if (gate->reg == 0)
 220                 return 0;
 221
 222         debug("%s: really %sabling %ld\n", __func__, on ? "en" : "dis", id);
 223
 224         regmap_update_bits(priv->map, gate->reg,
 225                            BIT(gate->bit), on ? BIT(gate->bit) : 0);
 226
 227         /* Propagate to next gate(s) */
 228         switch (id) {
 229         case CLKID_VAPB:
 230                 return meson_set_gate_by_id(clk, CLKID_VAPB_SEL, on);
 231         }
 232
 233         return 0;
 234 }
 235
 236 static int meson_clk_enable(struct clk *clk)
 237 {
 238         return meson_set_gate_by_id(clk, clk->id, true);
 239 }
 240
 241 static int meson_clk_disable(struct clk *clk)
 242 {
 243         return meson_set_gate_by_id(clk, clk->id, false);
 244 }
 245
 246 static struct parm meson_vpu_0_div_parm = {
 247         HHI_VPU_CLK_CNTL, 0, 7,
 248 };
 249
 250 int meson_vpu_0_div_parent = CLKID_VPU_0_SEL;
 251
 252 static struct parm meson_vpu_1_div_parm = {
 253         HHI_VPU_CLK_CNTL, 16, 7,
 254 };
 255
 256 int meson_vpu_1_div_parent = CLKID_VPU_1_SEL;
 257
 258 static struct parm meson_vapb_0_div_parm = {
 259         HHI_VAPBCLK_CNTL, 0, 7,
 260 };
 261
 262 int meson_vapb_0_div_parent = CLKID_VAPB_0_SEL;
 263
 264 static struct parm meson_vapb_1_div_parm = {
 265         HHI_VAPBCLK_CNTL, 16, 7,
 266 };
 267
 268 int meson_vapb_1_div_parent = CLKID_VAPB_1_SEL;
 269
 270 static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
 271 {
 272         struct meson_clk *priv = dev_get_priv(clk->dev);
 273         unsigned int rate, parent_rate;
 274         struct parm *parm;
 275         int parent;
 276         uint reg;
 277
 278         switch (id) {
 279         case CLKID_VPU_0_DIV:
 280                 parm = &meson_vpu_0_div_parm;
 281                 parent = meson_vpu_0_div_parent;
 282                 break;
 283         case CLKID_VPU_1_DIV:
 284                 parm = &meson_vpu_1_div_parm;
 285                 parent = meson_vpu_1_div_parent;
 286                 break;
 287         case CLKID_VAPB_0_DIV:
 288                 parm = &meson_vapb_0_div_parm;
 289                 parent = meson_vapb_0_div_parent;
 290                 break;
 291         case CLKID_VAPB_1_DIV:
 292                 parm = &meson_vapb_1_div_parm;
 293                 parent = meson_vapb_1_div_parent;
 294                 break;
 295         default:
 296                 return -ENOENT;
 297         }
 298
 299         regmap_read(priv->map, parm->reg_off, &reg);
 300         reg = PARM_GET(parm->width, parm->shift, reg);
 301
 302         debug("%s: div of %ld is %d\n", __func__, id, reg + 1);
 303
 304         parent_rate = meson_clk_get_rate_by_id(clk, parent);
 305         if (IS_ERR_VALUE(parent_rate))
 306                 return parent_rate;
 307
 308         debug("%s: parent rate of %ld is %d\n", __func__, id, parent_rate);
 309
 310         rate = parent_rate / (reg + 1);
 311
 312         debug("%s: rate of %ld is %d\n", __func__, id, rate);
 313
 314         return rate;
 315 }
 316
 317 static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
 318                                 ulong current_rate)
 319 {
 320         struct meson_clk *priv = dev_get_priv(clk->dev);
 321         unsigned int new_div = -EINVAL;
 322         unsigned long parent_rate;
 323         struct parm *parm;
 324         int parent;
 325         int ret;
 326
 327         if (current_rate == rate)
 328                 return 0;
 329
 330         debug("%s: setting rate of %ld from %ld to %ld\n",
 331               __func__, id, current_rate, rate);
 332
 333         switch (id) {
 334         case CLKID_VPU_0_DIV:
 335                 parm = &meson_vpu_0_div_parm;
 336                 parent = meson_vpu_0_div_parent;
 337                 break;
 338         case CLKID_VPU_1_DIV:
 339                 parm = &meson_vpu_1_div_parm;
 340                 parent = meson_vpu_1_div_parent;
 341                 break;
 342         case CLKID_VAPB_0_DIV:
 343                 parm = &meson_vapb_0_div_parm;
 344                 parent = meson_vapb_0_div_parent;
 345                 break;
 346         case CLKID_VAPB_1_DIV:
 347                 parm = &meson_vapb_1_div_parm;
 348                 parent = meson_vapb_1_div_parent;
 349                 break;
 350         default:
 351                 return -ENOENT;
 352         }
 353
 354         parent_rate = meson_clk_get_rate_by_id(clk, parent);
 355         if (IS_ERR_VALUE(parent_rate))
 356                 return parent_rate;
 357
 358         debug("%s: parent rate of %ld is %ld\n", __func__, id, parent_rate);
 359
 360         /* If can't divide, set parent instead */
 361         if (!parent_rate || rate > parent_rate)
 362                 return meson_clk_set_rate_by_id(clk, parent, rate,
 363                                                 current_rate);
 364
 365         new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
 366
 367         debug("%s: new div of %ld is %d\n", __func__, id, new_div);
 368
 369         /* If overflow, try to set parent rate and retry */
 370         if (!new_div || new_div > (1 << parm->width)) {
 371                 ret = meson_clk_set_rate_by_id(clk, parent, rate, current_rate);
 372                 if (IS_ERR_VALUE(ret))
 373                         return ret;
 374
 375                 parent_rate = meson_clk_get_rate_by_id(clk, parent);
 376                 if (IS_ERR_VALUE(parent_rate))
 377                         return parent_rate;
 378
 379                 new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
 380
 381                 debug("%s: new new div of %ld is %d\n", __func__, id, new_div);
 382
 383                 if (!new_div || new_div > (1 << parm->width))
 384                         return -EINVAL;
 385         }
 386
 387         debug("%s: setting div of %ld to %d\n", __func__, id, new_div);
 388
 389         regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),
 390                            (new_div - 1) << parm->shift);
 391
 392         debug("%s: new rate of %ld is %ld\n",
 393               __func__, id, meson_div_get_rate(clk, id));
 394
 395         return 0;
 396 }
 397
 398 static struct parm meson_vpu_mux_parm = {
 399         HHI_VPU_CLK_CNTL, 31, 1,
 400 };
 401
 402 int meson_vpu_mux_parents[] = {
 403         CLKID_VPU_0,
 404         CLKID_VPU_1,
 405 };
 406
 407 static struct parm meson_vpu_0_mux_parm = {
 408         HHI_VPU_CLK_CNTL, 9, 2,
 409 };
 410
 411 static struct parm meson_vpu_1_mux_parm = {
 412         HHI_VPU_CLK_CNTL, 25, 2,
 413 };
 414
 415 static int meson_vpu_0_1_mux_parents[] = {
 416         CLKID_FCLK_DIV4,
 417         CLKID_FCLK_DIV3,
 418         CLKID_FCLK_DIV5,
 419         CLKID_FCLK_DIV7,
 420 };
 421
 422 static struct parm meson_vapb_sel_mux_parm = {
 423         HHI_VAPBCLK_CNTL, 31, 1,
 424 };
 425
 426 int meson_vapb_sel_mux_parents[] = {
 427         CLKID_VAPB_0,
 428         CLKID_VAPB_1,
 429 };
 430
 431 static struct parm meson_vapb_0_mux_parm = {
 432         HHI_VAPBCLK_CNTL, 9, 2,
 433 };
 434
 435 static struct parm meson_vapb_1_mux_parm = {
 436         HHI_VAPBCLK_CNTL, 25, 2,
 437 };
 438
 439 static int meson_vapb_0_1_mux_parents[] = {
 440         CLKID_FCLK_DIV4,
 441         CLKID_FCLK_DIV3,
 442         CLKID_FCLK_DIV5,
 443         CLKID_FCLK_DIV7,
 444 };
 445
 446 static ulong meson_mux_get_parent(struct clk *clk, unsigned long id)
 447 {
 448         struct meson_clk *priv = dev_get_priv(clk->dev);
 449         struct parm *parm;
 450         int *parents;
 451         uint reg;
 452
 453         switch (id) {
 454         case CLKID_VPU:
 455                 parm = &meson_vpu_mux_parm;
 456                 parents = meson_vpu_mux_parents;
 457                 break;
 458         case CLKID_VPU_0_SEL:
 459                 parm = &meson_vpu_0_mux_parm;
 460                 parents = meson_vpu_0_1_mux_parents;
 461                 break;
 462         case CLKID_VPU_1_SEL:
 463                 parm = &meson_vpu_1_mux_parm;
 464                 parents = meson_vpu_0_1_mux_parents;
 465                 break;
 466         case CLKID_VAPB_SEL:
 467                 parm = &meson_vapb_sel_mux_parm;
 468                 parents = meson_vapb_sel_mux_parents;
 469                 break;
 470         case CLKID_VAPB_0_SEL:
 471                 parm = &meson_vapb_0_mux_parm;
 472                 parents = meson_vapb_0_1_mux_parents;
 473                 break;
 474         case CLKID_VAPB_1_SEL:
 475                 parm = &meson_vapb_1_mux_parm;
 476                 parents = meson_vapb_0_1_mux_parents;
 477                 break;
 478         default:
 479                 return -ENOENT;
 480         }
 481
 482         regmap_read(priv->map, parm->reg_off, &reg);
 483         reg = PARM_GET(parm->width, parm->shift, reg);
 484
 485         debug("%s: parent of %ld is %d (%d)\n",
 486               __func__, id, parents[reg], reg);
 487
 488         return parents[reg];
 489 }
 490
 491 static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
 492                                   unsigned long parent_id)
 493 {
 494         unsigned long cur_parent = meson_mux_get_parent(clk, id);
 495         struct meson_clk *priv = dev_get_priv(clk->dev);
 496         unsigned int new_index = -EINVAL;
 497         struct parm *parm;
 498         int *parents;
 499         int i;
 500
 501         if (IS_ERR_VALUE(cur_parent))
 502                 return cur_parent;
 503
 504         debug("%s: setting parent of %ld from %ld to %ld\n",
 505               __func__, id, cur_parent, parent_id);
 506
 507         if (cur_parent == parent_id)
 508                 return 0;
 509
 510         switch (id) {
 511         case CLKID_VPU:
 512                 parm = &meson_vpu_mux_parm;
 513                 parents = meson_vpu_mux_parents;
 514                 break;
 515         case CLKID_VPU_0_SEL:
 516                 parm = &meson_vpu_0_mux_parm;
 517                 parents = meson_vpu_0_1_mux_parents;
 518                 break;
 519         case CLKID_VPU_1_SEL:
 520                 parm = &meson_vpu_1_mux_parm;
 521                 parents = meson_vpu_0_1_mux_parents;
 522                 break;
 523         case CLKID_VAPB_SEL:
 524                 parm = &meson_vapb_sel_mux_parm;
 525                 parents = meson_vapb_sel_mux_parents;
 526                 break;
 527         case CLKID_VAPB_0_SEL:
 528                 parm = &meson_vapb_0_mux_parm;
 529                 parents = meson_vapb_0_1_mux_parents;
 530                 break;
 531         case CLKID_VAPB_1_SEL:
 532                 parm = &meson_vapb_1_mux_parm;
 533                 parents = meson_vapb_0_1_mux_parents;
 534                 break;
 535         default:
 536                 /* Not a mux */
 537                 return -ENOENT;
 538         }
 539
 540         for (i = 0 ; i < (1 << parm->width) ; ++i) {
 541                 if (parents[i] == parent_id)
 542                         new_index = i;
 543         }
 544
 545         if (IS_ERR_VALUE(new_index))
 546                 return new_index;
 547
 548         debug("%s: new index of %ld is %d\n", __func__, id, new_index);
 549
 550         regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),
 551                            new_index << parm->shift);
 552
 553         debug("%s: new parent of %ld is %ld\n",
 554               __func__, id, meson_mux_get_parent(clk, id));
 555
 556         return 0;
 557 }
 558
 559 static ulong meson_mux_get_rate(struct clk *clk, unsigned long id)
 560 {
 561         int parent = meson_mux_get_parent(clk, id);
 562
 563         if (IS_ERR_VALUE(parent))
 564                 return parent;
 565
 566         return meson_clk_get_rate_by_id(clk, parent);
 567 }
 568
 569 static unsigned long meson_clk81_get_rate(struct clk *clk)
 570 {
 571         struct meson_clk *priv = dev_get_priv(clk->dev);
 572         unsigned long parent_rate;
 573         uint reg;
 574         int parents[] = {
 575                 -1,
 576                 -1,
 577                 CLKID_FCLK_DIV7,
 578                 CLKID_MPLL1,
 579                 CLKID_MPLL2,
 580                 CLKID_FCLK_DIV4,
 581                 CLKID_FCLK_DIV3,
 582                 CLKID_FCLK_DIV5
 583         };
 584
 585         /* mux */
 586         regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
 587         reg = (reg >> 12) & 7;
 588
 589         switch (reg) {
 590         case 0:
 591                 parent_rate = XTAL_RATE;
 592                 break;
 593         case 1:
 594                 return -ENOENT;
 595         default:
 596                 parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
 597         }
 598
 599         /* divider */
 600         regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
 601         reg = reg & ((1 << 7) - 1);
 602
 603         /* clk81 divider is zero based */
 604         return parent_rate / (reg + 1);
 605 }
 606
 607 static long mpll_rate_from_params(unsigned long parent_rate,
 608                                   unsigned long sdm,
 609                                   unsigned long n2)
 610 {
 611         unsigned long divisor = (SDM_DEN * n2) + sdm;
 612
 613         if (n2 < N2_MIN)
 614                 return -EINVAL;
 615
 616         return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
 617 }
 618
 619 static struct parm meson_mpll0_parm[3] = {
 620         {HHI_MPLL_CNTL7, 0, 14}, /* psdm */
 621         {HHI_MPLL_CNTL7, 16, 9}, /* pn2 */
 622 };
 623
 624 static struct parm meson_mpll1_parm[3] = {
 625         {HHI_MPLL_CNTL8, 0, 14}, /* psdm */
 626         {HHI_MPLL_CNTL8, 16, 9}, /* pn2 */
 627 };
 628
 629 static struct parm meson_mpll2_parm[3] = {
 630         {HHI_MPLL_CNTL9, 0, 14}, /* psdm */
 631         {HHI_MPLL_CNTL9, 16, 9}, /* pn2 */
 632 };
 633
 634 /*
 635  * MultiPhase Locked Loops are outputs from a PLL with additional frequency
 636  * scaling capabilities. MPLL rates are calculated as:
 637  *
 638  * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
 639  */
 640 static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
 641 {
 642         struct meson_clk *priv = dev_get_priv(clk->dev);
 643         struct parm *psdm, *pn2;
 644         unsigned long sdm, n2;
 645         unsigned long parent_rate;
 646         uint reg;
 647
 648         switch (id) {
 649         case CLKID_MPLL0:
 650                 psdm = &meson_mpll0_parm[0];
 651                 pn2 = &meson_mpll0_parm[1];
 652                 break;
 653         case CLKID_MPLL1:
 654                 psdm = &meson_mpll1_parm[0];
 655                 pn2 = &meson_mpll1_parm[1];
 656                 break;
 657         case CLKID_MPLL2:
 658                 psdm = &meson_mpll2_parm[0];
 659                 pn2 = &meson_mpll2_parm[1];
 660                 break;
 661         default:
 662                 return -ENOENT;
 663         }
 664
 665         parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
 666         if (IS_ERR_VALUE(parent_rate))
 667                 return parent_rate;
 668
 669         regmap_read(priv->map, psdm->reg_off, &reg);
 670         sdm = PARM_GET(psdm->width, psdm->shift, reg);
 671
 672         regmap_read(priv->map, pn2->reg_off, &reg);
 673         n2 = PARM_GET(pn2->width, pn2->shift, reg);
 674
 675         return mpll_rate_from_params(parent_rate, sdm, n2);
 676 }
 677
 678 static struct parm meson_fixed_pll_parm[3] = {
 679         {HHI_MPLL_CNTL, 0, 9}, /* pm */
 680         {HHI_MPLL_CNTL, 9, 5}, /* pn */
 681         {HHI_MPLL_CNTL, 16, 2}, /* pod */
 682 };
 683
 684 static struct parm meson_sys_pll_parm[3] = {
 685         {HHI_SYS_PLL_CNTL, 0, 9}, /* pm */
 686         {HHI_SYS_PLL_CNTL, 9, 5}, /* pn */
 687         {HHI_SYS_PLL_CNTL, 10, 2}, /* pod */
 688 };
 689
 690 static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
 691 {
 692         struct meson_clk *priv = dev_get_priv(clk->dev);
 693         struct parm *pm, *pn, *pod;
 694         unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
 695         u16 n, m, od;
 696         uint reg;
 697
 698         switch (id) {
 699         case CLKID_FIXED_PLL:
 700                 pm = &meson_fixed_pll_parm[0];
 701                 pn = &meson_fixed_pll_parm[1];
 702                 pod = &meson_fixed_pll_parm[2];
 703                 break;
 704         case CLKID_SYS_PLL:
 705                 pm = &meson_sys_pll_parm[0];
 706                 pn = &meson_sys_pll_parm[1];
 707                 pod = &meson_sys_pll_parm[2];
 708                 break;
 709         default:
 710                 return -ENOENT;
 711         }
 712
 713         regmap_read(priv->map, pn->reg_off, &reg);
 714         n = PARM_GET(pn->width, pn->shift, reg);
 715
 716         regmap_read(priv->map, pm->reg_off, &reg);
 717         m = PARM_GET(pm->width, pm->shift, reg);
 718
 719         regmap_read(priv->map, pod->reg_off, &reg);
 720         od = PARM_GET(pod->width, pod->shift, reg);
 721
 722         return ((parent_rate_mhz * m / n) >> od) * 1000000;
 723 }
 724
 725 static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
 726 {
 727         ulong rate;
 728
 729         switch (id) {
 730         case CLKID_FIXED_PLL:
 731         case CLKID_SYS_PLL:
 732                 rate = meson_pll_get_rate(clk, id);
 733                 break;
 734         case CLKID_FCLK_DIV2:
 735                 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
 736                 break;
 737         case CLKID_FCLK_DIV3:
 738                 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
 739                 break;
 740         case CLKID_FCLK_DIV4:
 741                 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
 742                 break;
 743         case CLKID_FCLK_DIV5:
 744                 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
 745                 break;
 746         case CLKID_FCLK_DIV7:
 747                 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
 748                 break;
 749         case CLKID_MPLL0:
 750         case CLKID_MPLL1:
 751         case CLKID_MPLL2:
 752                 rate = meson_mpll_get_rate(clk, id);
 753                 break;
 754         case CLKID_CLK81:
 755                 rate = meson_clk81_get_rate(clk);
 756                 break;
 757         case CLKID_VPU_0:
 758                 rate = meson_div_get_rate(clk, CLKID_VPU_0_DIV);
 759                 break;
 760         case CLKID_VPU_1:
 761                 rate = meson_div_get_rate(clk, CLKID_VPU_1_DIV);
 762                 break;
 763         case CLKID_VAPB:
 764                 rate = meson_mux_get_rate(clk, CLKID_VAPB_SEL);
 765                 break;
 766         case CLKID_VAPB_0:
 767                 rate = meson_div_get_rate(clk, CLKID_VAPB_0_DIV);
 768                 break;
 769         case CLKID_VAPB_1:
 770                 rate = meson_div_get_rate(clk, CLKID_VAPB_1_DIV);
 771                 break;
 772         case CLKID_VPU_0_DIV:
 773         case CLKID_VPU_1_DIV:
 774         case CLKID_VAPB_0_DIV:
 775         case CLKID_VAPB_1_DIV:
 776                 rate = meson_div_get_rate(clk, id);
 777                 break;
 778         case CLKID_VPU:
 779         case CLKID_VPU_0_SEL:
 780         case CLKID_VPU_1_SEL:
 781         case CLKID_VAPB_SEL:
 782         case CLKID_VAPB_0_SEL:
 783         case CLKID_VAPB_1_SEL:
 784                 rate = meson_mux_get_rate(clk, id);
 785                 break;
 786         default:
 787                 if (gates[id].reg != 0) {
 788                         /* a clock gate */
 789                         rate = meson_clk81_get_rate(clk);
 790                         break;
 791                 }
 792                 return -ENOENT;
 793         }
 794
 795         debug("clock %lu has rate %lu\n", id, rate);
 796         return rate;
 797 }
 798
 799 static ulong meson_clk_get_rate(struct clk *clk)
 800 {
 801         return meson_clk_get_rate_by_id(clk, clk->id);
 802 }
 803
 804 static int meson_clk_set_parent(struct clk *clk, struct clk *parent)
 805 {
 806         return meson_mux_set_parent(clk, clk->id, parent->id);
 807 }
 808
 809 static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
 810                                       ulong rate, ulong current_rate)
 811 {
 812         if (current_rate == rate)
 813                 return 0;
 814
 815         switch (id) {
 816         /* Fixed clocks */
 817         case CLKID_FIXED_PLL:
 818         case CLKID_SYS_PLL:
 819         case CLKID_FCLK_DIV2:
 820         case CLKID_FCLK_DIV3:
 821         case CLKID_FCLK_DIV4:
 822         case CLKID_FCLK_DIV5:
 823         case CLKID_FCLK_DIV7:
 824         case CLKID_MPLL0:
 825         case CLKID_MPLL1:
 826         case CLKID_MPLL2:
 827         case CLKID_CLK81:
 828                 return -EINVAL;
 829         case CLKID_VPU:
 830                 return meson_clk_set_rate_by_id(clk,
 831                                 meson_mux_get_parent(clk, CLKID_VPU), rate,
 832                                                      current_rate);
 833         case CLKID_VAPB:
 834         case CLKID_VAPB_SEL:
 835                 return meson_clk_set_rate_by_id(clk,
 836                                 meson_mux_get_parent(clk, CLKID_VAPB_SEL),
 837                                 rate, current_rate);
 838         case CLKID_VPU_0:
 839                 return meson_div_set_rate(clk, CLKID_VPU_0_DIV, rate,
 840                                           current_rate);
 841         case CLKID_VPU_1:
 842                 return meson_div_set_rate(clk, CLKID_VPU_1_DIV, rate,
 843                                           current_rate);
 844         case CLKID_VAPB_0:
 845                 return meson_div_set_rate(clk, CLKID_VAPB_0_DIV, rate,
 846                                           current_rate);
 847         case CLKID_VAPB_1:
 848                 return meson_div_set_rate(clk, CLKID_VAPB_1_DIV, rate,
 849                                           current_rate);
 850         case CLKID_VPU_0_DIV:
 851         case CLKID_VPU_1_DIV:
 852         case CLKID_VAPB_0_DIV:
 853         case CLKID_VAPB_1_DIV:
 854                 return meson_div_set_rate(clk, id, rate, current_rate);
 855         default:
 856                 return -ENOENT;
 857         }
 858
 859         return -EINVAL;
 860 }
 861
 862 static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
 863 {
 864         ulong current_rate = meson_clk_get_rate_by_id(clk, clk->id);
 865         int ret;
 866
 867         if (IS_ERR_VALUE(current_rate))
 868                 return current_rate;
 869
 870         debug("%s: setting rate of %ld from %ld to %ld\n",
 871               __func__, clk->id, current_rate, rate);
 872
 873         ret = meson_clk_set_rate_by_id(clk, clk->id, rate, current_rate);
 874         if (IS_ERR_VALUE(ret))
 875                 return ret;
 876
 877         debug("clock %lu has new rate %lu\n", clk->id,
 878               meson_clk_get_rate_by_id(clk, clk->id));
 879
 880         return 0;
 881 }
 882
 883 static int meson_clk_probe(struct udevice *dev)
 884 {
 885         struct meson_clk *priv = dev_get_priv(dev);
 886
 887         priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
 888         if (IS_ERR(priv->map))
 889                 return PTR_ERR(priv->map);
 890
 891         /*
 892          * Depending on the boot src, the state of the MMC clock might
 893          * be different. Reset it to make sure we won't get stuck
 894          */
 895         regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
 896         regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
 897
 898         debug("meson-clk: probed\n");
 899
 900         return 0;
 901 }
 902
 903 static struct clk_ops meson_clk_ops = {
 904         .disable        = meson_clk_disable,
 905         .enable         = meson_clk_enable,
 906         .get_rate       = meson_clk_get_rate,
 907         .set_parent     = meson_clk_set_parent,
 908         .set_rate       = meson_clk_set_rate,
 909 };
 910
 911 static const struct udevice_id meson_clk_ids[] = {
 912         { .compatible = "amlogic,gxbb-clkc" },
 913         { .compatible = "amlogic,gxl-clkc" },
 914         { }
 915 };
 916
 917 U_BOOT_DRIVER(meson_clk) = {
 918         .name           = "meson_clk",
 919         .id             = UCLASS_CLK,
 920         .of_match       = meson_clk_ids,
 921         .priv_auto_alloc_size = sizeof(struct meson_clk),
 922         .ops            = &meson_clk_ops,
 923         .probe          = meson_clk_probe,
 924 };