1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
4 * (C) Copyright 2018 - BayLibre, SAS
5 * Author: Neil Armstrong <narmstrong@baylibre.com>
9 #include <asm/arch/clock-g12a.h>
11 #include <clk-uclass.h>
16 #include <dt-bindings/clock/g12a-clkc.h>
17 #include <linux/err.h>
18 #include <linux/kernel.h>
19 #include "clk_meson.h"
21 /* This driver support only basic clock tree operations :
22 * - Can calculate clock frequency on a limited tree
23 * - Can Read muxes and basic dividers (0-based only)
24 * - Can enable/disable gates with limited propagation
25 * - Can reparent without propagation, only on muxes
26 * - Can set rates without reparenting
27 * This driver is adapted to what is actually supported by U-Boot
30 /* Only the clocks ids we don't want to expose, such as the internal muxes
31 * and dividers of composite clocks, will remain defined here.
33 #define CLKID_MPEG_SEL 8
34 #define CLKID_MPEG_DIV 9
35 #define CLKID_SD_EMMC_A_CLK0_SEL 63
36 #define CLKID_SD_EMMC_A_CLK0_DIV 64
37 #define CLKID_SD_EMMC_B_CLK0_SEL 65
38 #define CLKID_SD_EMMC_B_CLK0_DIV 66
39 #define CLKID_SD_EMMC_C_CLK0_SEL 67
40 #define CLKID_SD_EMMC_C_CLK0_DIV 68
41 #define CLKID_MPLL0_DIV 69
42 #define CLKID_MPLL1_DIV 70
43 #define CLKID_MPLL2_DIV 71
44 #define CLKID_MPLL3_DIV 72
45 #define CLKID_MPLL_PREDIV 73
46 #define CLKID_FCLK_DIV2_DIV 75
47 #define CLKID_FCLK_DIV3_DIV 76
48 #define CLKID_FCLK_DIV4_DIV 77
49 #define CLKID_FCLK_DIV5_DIV 78
50 #define CLKID_FCLK_DIV7_DIV 79
51 #define CLKID_FCLK_DIV2P5_DIV 100
52 #define CLKID_FIXED_PLL_DCO 101
53 #define CLKID_SYS_PLL_DCO 102
54 #define CLKID_GP0_PLL_DCO 103
55 #define CLKID_HIFI_PLL_DCO 104
56 #define CLKID_VPU_0_DIV 111
57 #define CLKID_VPU_1_DIV 114
58 #define CLKID_VAPB_0_DIV 118
59 #define CLKID_VAPB_1_DIV 121
60 #define CLKID_HDMI_PLL_DCO 125
61 #define CLKID_HDMI_PLL_OD 126
62 #define CLKID_HDMI_PLL_OD2 127
63 #define CLKID_VID_PLL_SEL 130
64 #define CLKID_VID_PLL_DIV 131
65 #define CLKID_VCLK_SEL 132
66 #define CLKID_VCLK2_SEL 133
67 #define CLKID_VCLK_INPUT 134
68 #define CLKID_VCLK2_INPUT 135
69 #define CLKID_VCLK_DIV 136
70 #define CLKID_VCLK2_DIV 137
71 #define CLKID_VCLK_DIV2_EN 140
72 #define CLKID_VCLK_DIV4_EN 141
73 #define CLKID_VCLK_DIV6_EN 142
74 #define CLKID_VCLK_DIV12_EN 143
75 #define CLKID_VCLK2_DIV2_EN 144
76 #define CLKID_VCLK2_DIV4_EN 145
77 #define CLKID_VCLK2_DIV6_EN 146
78 #define CLKID_VCLK2_DIV12_EN 147
79 #define CLKID_CTS_ENCI_SEL 158
80 #define CLKID_CTS_ENCP_SEL 159
81 #define CLKID_CTS_VDAC_SEL 160
82 #define CLKID_HDMI_TX_SEL 161
83 #define CLKID_HDMI_SEL 166
84 #define CLKID_HDMI_DIV 167
85 #define CLKID_MALI_0_DIV 170
86 #define CLKID_MALI_1_DIV 173
88 #define CLKID_XTAL 0x10000000
90 #define XTAL_RATE 24000000
96 static ulong meson_div_get_rate(struct clk *clk, unsigned long id);
97 static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
99 static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
100 unsigned long parent_id);
101 static ulong meson_mux_get_rate(struct clk *clk, unsigned long id);
102 static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
103 ulong rate, ulong current_rate);
104 static ulong meson_mux_get_parent(struct clk *clk, unsigned long id);
105 static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
109 static struct meson_gate gates[NUM_CLKS] = {
110 /* Everything Else (EE) domain gates */
111 MESON_GATE(CLKID_SPICC0, HHI_GCLK_MPEG0, 8),
112 MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
113 MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
114 MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 14),
115 MESON_GATE(CLKID_SD_EMMC_A, HHI_GCLK_MPEG0, 4),
116 MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
117 MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
118 MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
119 MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
120 MESON_GATE(CLKID_USB, HHI_GCLK_MPEG1, 25),
121 MESON_GATE(CLKID_HTX_PCLK, HHI_GCLK_MPEG2, 4),
122 MESON_GATE(CLKID_USB1_DDR_BRIDGE, HHI_GCLK_MPEG2, 8),
123 MESON_GATE(CLKID_VPU_INTR, HHI_GCLK_MPEG2, 25),
125 /* Peripheral Gates */
126 MESON_GATE(CLKID_FCLK_DIV2, HHI_FIX_PLL_CNTL1, 24),
127 MESON_GATE(CLKID_FCLK_DIV3, HHI_FIX_PLL_CNTL1, 20),
128 MESON_GATE(CLKID_FCLK_DIV4, HHI_FIX_PLL_CNTL1, 21),
129 MESON_GATE(CLKID_FCLK_DIV5, HHI_FIX_PLL_CNTL1, 22),
130 MESON_GATE(CLKID_FCLK_DIV7, HHI_FIX_PLL_CNTL1, 23),
131 MESON_GATE(CLKID_SD_EMMC_A_CLK0, HHI_SD_EMMC_CLK_CNTL, 7),
132 MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
133 MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
134 MESON_GATE(CLKID_VPU_0, HHI_VPU_CLK_CNTL, 8),
135 MESON_GATE(CLKID_VPU_1, HHI_VPU_CLK_CNTL, 24),
136 MESON_GATE(CLKID_VAPB_0, HHI_VAPBCLK_CNTL, 8),
137 MESON_GATE(CLKID_VAPB_1, HHI_VAPBCLK_CNTL, 24),
138 MESON_GATE(CLKID_VAPB, HHI_VAPBCLK_CNTL, 30),
139 MESON_GATE(CLKID_HDMI, HHI_HDMI_CLK_CNTL, 8),
142 static int meson_set_gate_by_id(struct clk *clk, unsigned long id, bool on)
144 struct meson_clk *priv = dev_get_priv(clk->dev);
145 struct meson_gate *gate;
147 debug("%s: %sabling %ld\n", __func__, on ? "en" : "dis", id);
149 /* Propagate through muxes */
152 return meson_set_gate_by_id(clk,
153 meson_mux_get_parent(clk, CLKID_VPU), on);
155 return meson_set_gate_by_id(clk,
156 meson_mux_get_parent(clk, CLKID_VAPB_SEL), on);
159 if (id >= ARRAY_SIZE(gates))
167 debug("%s: really %sabling %ld\n", __func__, on ? "en" : "dis", id);
169 regmap_update_bits(priv->map, gate->reg,
170 BIT(gate->bit), on ? BIT(gate->bit) : 0);
172 /* Propagate to next gate(s) */
175 return meson_set_gate_by_id(clk, CLKID_VAPB_SEL, on);
177 return meson_set_gate_by_id(clk,
178 meson_mux_get_parent(clk, CLKID_VAPB_0_SEL), on);
180 return meson_set_gate_by_id(clk,
181 meson_mux_get_parent(clk, CLKID_VAPB_0_SEL), on);
183 return meson_set_gate_by_id(clk,
184 meson_mux_get_parent(clk, CLKID_VPU_0_SEL), on);
186 return meson_set_gate_by_id(clk,
187 meson_mux_get_parent(clk, CLKID_VPU_1_SEL), on);
193 static int meson_clk_enable(struct clk *clk)
195 return meson_set_gate_by_id(clk, clk->id, true);
198 static int meson_clk_disable(struct clk *clk)
200 return meson_set_gate_by_id(clk, clk->id, false);
203 static struct parm meson_vpu_0_div_parm = {
204 HHI_VPU_CLK_CNTL, 0, 7,
207 int meson_vpu_0_div_parent = CLKID_VPU_0_SEL;
209 static struct parm meson_vpu_1_div_parm = {
210 HHI_VPU_CLK_CNTL, 16, 7,
213 int meson_vpu_1_div_parent = CLKID_VPU_1_SEL;
215 static struct parm meson_vapb_0_div_parm = {
216 HHI_VAPBCLK_CNTL, 0, 7,
219 int meson_vapb_0_div_parent = CLKID_VAPB_0_SEL;
221 static struct parm meson_vapb_1_div_parm = {
222 HHI_VAPBCLK_CNTL, 16, 7,
225 int meson_vapb_1_div_parent = CLKID_VAPB_1_SEL;
227 static struct parm meson_hdmi_div_parm = {
228 HHI_HDMI_CLK_CNTL, 0, 7,
231 int meson_hdmi_div_parent = CLKID_HDMI_SEL;
233 static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
235 struct meson_clk *priv = dev_get_priv(clk->dev);
236 unsigned int rate, parent_rate;
242 case CLKID_VPU_0_DIV:
243 parm = &meson_vpu_0_div_parm;
244 parent = meson_vpu_0_div_parent;
246 case CLKID_VPU_1_DIV:
247 parm = &meson_vpu_1_div_parm;
248 parent = meson_vpu_1_div_parent;
250 case CLKID_VAPB_0_DIV:
251 parm = &meson_vapb_0_div_parm;
252 parent = meson_vapb_0_div_parent;
254 case CLKID_VAPB_1_DIV:
255 parm = &meson_vapb_1_div_parm;
256 parent = meson_vapb_1_div_parent;
259 parm = &meson_hdmi_div_parm;
260 parent = meson_hdmi_div_parent;
266 regmap_read(priv->map, parm->reg_off, ®);
267 reg = PARM_GET(parm->width, parm->shift, reg);
269 debug("%s: div of %ld is %d\n", __func__, id, reg + 1);
271 parent_rate = meson_clk_get_rate_by_id(clk, parent);
272 if (IS_ERR_VALUE(parent_rate))
275 debug("%s: parent rate of %ld is %d\n", __func__, id, parent_rate);
277 rate = parent_rate / (reg + 1);
279 debug("%s: rate of %ld is %d\n", __func__, id, rate);
284 static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
287 struct meson_clk *priv = dev_get_priv(clk->dev);
288 unsigned int new_div = -EINVAL;
289 unsigned long parent_rate;
294 if (current_rate == rate)
297 debug("%s: setting rate of %ld from %ld to %ld\n",
298 __func__, id, current_rate, rate);
301 case CLKID_VPU_0_DIV:
302 parm = &meson_vpu_0_div_parm;
303 parent = meson_vpu_0_div_parent;
305 case CLKID_VPU_1_DIV:
306 parm = &meson_vpu_1_div_parm;
307 parent = meson_vpu_1_div_parent;
309 case CLKID_VAPB_0_DIV:
310 parm = &meson_vapb_0_div_parm;
311 parent = meson_vapb_0_div_parent;
313 case CLKID_VAPB_1_DIV:
314 parm = &meson_vapb_1_div_parm;
315 parent = meson_vapb_1_div_parent;
318 parm = &meson_hdmi_div_parm;
319 parent = meson_hdmi_div_parent;
325 parent_rate = meson_clk_get_rate_by_id(clk, parent);
326 if (IS_ERR_VALUE(parent_rate))
329 debug("%s: parent rate of %ld is %ld\n", __func__, id, parent_rate);
331 /* If can't divide, set parent instead */
332 if (!parent_rate || rate > parent_rate)
333 return meson_clk_set_rate_by_id(clk, parent, rate,
336 new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
338 debug("%s: new div of %ld is %d\n", __func__, id, new_div);
340 /* If overflow, try to set parent rate and retry */
341 if (!new_div || new_div > (1 << parm->width)) {
342 ret = meson_clk_set_rate_by_id(clk, parent, rate, current_rate);
343 if (IS_ERR_VALUE(ret))
346 parent_rate = meson_clk_get_rate_by_id(clk, parent);
347 if (IS_ERR_VALUE(parent_rate))
350 new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
352 debug("%s: new new div of %ld is %d\n", __func__, id, new_div);
354 if (!new_div || new_div > (1 << parm->width))
358 debug("%s: setting div of %ld to %d\n", __func__, id, new_div);
360 regmap_update_bits(priv->map, parm->reg_off,
361 SETPMASK(parm->width, parm->shift),
362 (new_div - 1) << parm->shift);
364 debug("%s: new rate of %ld is %ld\n",
365 __func__, id, meson_div_get_rate(clk, id));
370 static struct parm meson_vpu_mux_parm = {
371 HHI_VPU_CLK_CNTL, 31, 1,
374 int meson_vpu_mux_parents[] = {
379 static struct parm meson_vpu_0_mux_parm = {
380 HHI_VPU_CLK_CNTL, 9, 3,
383 static struct parm meson_vpu_1_mux_parm = {
384 HHI_VPU_CLK_CNTL, 25, 3,
387 static int meson_vpu_0_1_mux_parents[] = {
398 static struct parm meson_vapb_sel_mux_parm = {
399 HHI_VAPBCLK_CNTL, 31, 1,
402 int meson_vapb_sel_mux_parents[] = {
407 static struct parm meson_vapb_0_mux_parm = {
408 HHI_VAPBCLK_CNTL, 9, 2,
411 static struct parm meson_vapb_1_mux_parm = {
412 HHI_VAPBCLK_CNTL, 25, 2,
415 static int meson_vapb_0_1_mux_parents[] = {
422 static struct parm meson_hdmi_mux_parm = {
423 HHI_HDMI_CLK_CNTL, 9, 2,
426 static int meson_hdmi_mux_parents[] = {
433 static ulong meson_mux_get_parent(struct clk *clk, unsigned long id)
435 struct meson_clk *priv = dev_get_priv(clk->dev);
442 parm = &meson_vpu_mux_parm;
443 parents = meson_vpu_mux_parents;
445 case CLKID_VPU_0_SEL:
446 parm = &meson_vpu_0_mux_parm;
447 parents = meson_vpu_0_1_mux_parents;
449 case CLKID_VPU_1_SEL:
450 parm = &meson_vpu_1_mux_parm;
451 parents = meson_vpu_0_1_mux_parents;
454 parm = &meson_vapb_sel_mux_parm;
455 parents = meson_vapb_sel_mux_parents;
457 case CLKID_VAPB_0_SEL:
458 parm = &meson_vapb_0_mux_parm;
459 parents = meson_vapb_0_1_mux_parents;
461 case CLKID_VAPB_1_SEL:
462 parm = &meson_vapb_1_mux_parm;
463 parents = meson_vapb_0_1_mux_parents;
466 parm = &meson_hdmi_mux_parm;
467 parents = meson_hdmi_mux_parents;
473 regmap_read(priv->map, parm->reg_off, ®);
474 reg = PARM_GET(parm->width, parm->shift, reg);
476 debug("%s: parent of %ld is %d (%d)\n",
477 __func__, id, parents[reg], reg);
482 static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
483 unsigned long parent_id)
485 unsigned long cur_parent = meson_mux_get_parent(clk, id);
486 struct meson_clk *priv = dev_get_priv(clk->dev);
487 unsigned int new_index = -EINVAL;
492 if (IS_ERR_VALUE(cur_parent))
495 debug("%s: setting parent of %ld from %ld to %ld\n",
496 __func__, id, cur_parent, parent_id);
498 if (cur_parent == parent_id)
503 parm = &meson_vpu_mux_parm;
504 parents = meson_vpu_mux_parents;
506 case CLKID_VPU_0_SEL:
507 parm = &meson_vpu_0_mux_parm;
508 parents = meson_vpu_0_1_mux_parents;
510 case CLKID_VPU_1_SEL:
511 parm = &meson_vpu_1_mux_parm;
512 parents = meson_vpu_0_1_mux_parents;
515 parm = &meson_vapb_sel_mux_parm;
516 parents = meson_vapb_sel_mux_parents;
518 case CLKID_VAPB_0_SEL:
519 parm = &meson_vapb_0_mux_parm;
520 parents = meson_vapb_0_1_mux_parents;
522 case CLKID_VAPB_1_SEL:
523 parm = &meson_vapb_1_mux_parm;
524 parents = meson_vapb_0_1_mux_parents;
527 parm = &meson_hdmi_mux_parm;
528 parents = meson_hdmi_mux_parents;
535 for (i = 0 ; i < (1 << parm->width) ; ++i) {
536 if (parents[i] == parent_id)
540 if (IS_ERR_VALUE(new_index))
543 debug("%s: new index of %ld is %d\n", __func__, id, new_index);
545 regmap_update_bits(priv->map, parm->reg_off,
546 SETPMASK(parm->width, parm->shift),
547 new_index << parm->shift);
549 debug("%s: new parent of %ld is %ld\n",
550 __func__, id, meson_mux_get_parent(clk, id));
555 static ulong meson_mux_get_rate(struct clk *clk, unsigned long id)
557 int parent = meson_mux_get_parent(clk, id);
559 if (IS_ERR_VALUE(parent))
562 return meson_clk_get_rate_by_id(clk, parent);
565 static unsigned long meson_clk81_get_rate(struct clk *clk)
567 struct meson_clk *priv = dev_get_priv(clk->dev);
568 unsigned long parent_rate;
582 regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
583 reg = (reg >> 12) & 7;
589 parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
593 regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
594 reg = reg & ((1 << 7) - 1);
596 return parent_rate / reg;
599 static long mpll_rate_from_params(unsigned long parent_rate,
603 unsigned long divisor = (SDM_DEN * n2) + sdm;
608 return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
611 static struct parm meson_mpll0_parm[2] = {
612 {HHI_MPLL_CNTL1, 0, 14}, /* psdm */
613 {HHI_MPLL_CNTL1, 20, 9}, /* pn2 */
616 static struct parm meson_mpll1_parm[2] = {
617 {HHI_MPLL_CNTL3, 0, 14}, /* psdm */
618 {HHI_MPLL_CNTL3, 20, 9}, /* pn2 */
621 static struct parm meson_mpll2_parm[2] = {
622 {HHI_MPLL_CNTL5, 0, 14}, /* psdm */
623 {HHI_MPLL_CNTL5, 20, 9}, /* pn2 */
627 * MultiPhase Locked Loops are outputs from a PLL with additional frequency
628 * scaling capabilities. MPLL rates are calculated as:
630 * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
632 static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
634 struct meson_clk *priv = dev_get_priv(clk->dev);
635 struct parm *psdm, *pn2;
636 unsigned long sdm, n2;
637 unsigned long parent_rate;
642 psdm = &meson_mpll0_parm[0];
643 pn2 = &meson_mpll0_parm[1];
646 psdm = &meson_mpll1_parm[0];
647 pn2 = &meson_mpll1_parm[1];
650 psdm = &meson_mpll2_parm[0];
651 pn2 = &meson_mpll2_parm[1];
657 parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
658 if (IS_ERR_VALUE(parent_rate))
661 regmap_read(priv->map, psdm->reg_off, ®);
662 sdm = PARM_GET(psdm->width, psdm->shift, reg);
664 regmap_read(priv->map, pn2->reg_off, ®);
665 n2 = PARM_GET(pn2->width, pn2->shift, reg);
667 return mpll_rate_from_params(parent_rate, sdm, n2);
670 static struct parm meson_fixed_pll_parm[4] = {
671 {HHI_FIX_PLL_CNTL0, 0, 9}, /* pm */
672 {HHI_FIX_PLL_CNTL0, 10, 5}, /* pn */
673 {HHI_FIX_PLL_CNTL0, 16, 2}, /* pod */
674 {HHI_FIX_PLL_CNTL1, 0, 17}, /* pfrac */
677 static struct parm meson_sys_pll_parm[3] = {
678 {HHI_SYS_PLL_CNTL0, 0, 9}, /* pm */
679 {HHI_SYS_PLL_CNTL0, 10, 5}, /* pn */
680 {HHI_SYS_PLL_CNTL0, 16, 3}, /* pod */
683 static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
685 struct meson_clk *priv = dev_get_priv(clk->dev);
686 struct parm *pm, *pn, *pod, *pfrac = NULL;
687 unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
693 * FIXME: Between the unit conversion and the missing frac, we know
694 * rate will be slightly off ...
698 case CLKID_FIXED_PLL:
699 pm = &meson_fixed_pll_parm[0];
700 pn = &meson_fixed_pll_parm[1];
701 pod = &meson_fixed_pll_parm[2];
702 pfrac = &meson_fixed_pll_parm[3];
705 pm = &meson_sys_pll_parm[0];
706 pn = &meson_sys_pll_parm[1];
707 pod = &meson_sys_pll_parm[2];
713 regmap_read(priv->map, pn->reg_off, ®);
714 n = PARM_GET(pn->width, pn->shift, reg);
716 regmap_read(priv->map, pm->reg_off, ®);
717 m = PARM_GET(pm->width, pm->shift, reg);
719 regmap_read(priv->map, pod->reg_off, ®);
720 od = PARM_GET(pod->width, pod->shift, reg);
722 rate = parent_rate_mhz * m;
727 regmap_read(priv->map, pfrac->reg_off, ®);
728 frac = PARM_GET(pfrac->width - 1, pfrac->shift, reg);
730 frac_rate = DIV_ROUND_UP_ULL((u64)parent_rate_mhz * frac,
731 1 << (pfrac->width - 2));
733 if (frac & BIT(pfrac->width - 1))
739 return (DIV_ROUND_UP_ULL(rate, n) >> od) * 1000000;
742 static struct parm meson_pcie_pll_parm[3] = {
743 {HHI_PCIE_PLL_CNTL0, 0, 8}, /* pm */
744 {HHI_PCIE_PLL_CNTL0, 10, 5}, /* pn */
745 {HHI_PCIE_PLL_CNTL0, 16, 5}, /* pod */
748 static ulong meson_pcie_pll_get_rate(struct clk *clk)
750 struct meson_clk *priv = dev_get_priv(clk->dev);
751 struct parm *pm, *pn, *pod;
752 unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
756 pm = &meson_pcie_pll_parm[0];
757 pn = &meson_pcie_pll_parm[1];
758 pod = &meson_pcie_pll_parm[2];
760 regmap_read(priv->map, pn->reg_off, ®);
761 n = PARM_GET(pn->width, pn->shift, reg);
763 regmap_read(priv->map, pm->reg_off, ®);
764 m = PARM_GET(pm->width, pm->shift, reg);
766 regmap_read(priv->map, pod->reg_off, ®);
767 od = PARM_GET(pod->width, pod->shift, reg);
769 return ((parent_rate_mhz * m / n) / 2 / od / 2) * 1000000;
772 static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
780 case CLKID_FIXED_PLL:
782 rate = meson_pll_get_rate(clk, id);
784 case CLKID_FCLK_DIV2:
785 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
787 case CLKID_FCLK_DIV3:
788 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
790 case CLKID_FCLK_DIV4:
791 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
793 case CLKID_FCLK_DIV5:
794 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
796 case CLKID_FCLK_DIV7:
797 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
802 rate = meson_mpll_get_rate(clk, id);
805 rate = meson_clk81_get_rate(clk);
808 rate = meson_pcie_pll_get_rate(clk);
811 rate = meson_div_get_rate(clk, CLKID_VPU_0_DIV);
814 rate = meson_div_get_rate(clk, CLKID_VPU_1_DIV);
817 rate = meson_mux_get_rate(clk, CLKID_VAPB_SEL);
820 rate = meson_div_get_rate(clk, CLKID_VAPB_0_DIV);
823 rate = meson_div_get_rate(clk, CLKID_VAPB_1_DIV);
826 rate = meson_div_get_rate(clk, CLKID_HDMI_DIV);
828 case CLKID_VPU_0_DIV:
829 case CLKID_VPU_1_DIV:
830 case CLKID_VAPB_0_DIV:
831 case CLKID_VAPB_1_DIV:
833 rate = meson_div_get_rate(clk, id);
836 case CLKID_VPU_0_SEL:
837 case CLKID_VPU_1_SEL:
839 case CLKID_VAPB_0_SEL:
840 case CLKID_VAPB_1_SEL:
842 rate = meson_mux_get_rate(clk, id);
845 if (gates[id].reg != 0) {
847 rate = meson_clk81_get_rate(clk);
853 debug("clock %lu has rate %lu\n", id, rate);
857 static ulong meson_clk_get_rate(struct clk *clk)
859 return meson_clk_get_rate_by_id(clk, clk->id);
862 static ulong meson_pcie_pll_set_rate(struct clk *clk, ulong rate)
864 struct meson_clk *priv = dev_get_priv(clk->dev);
866 regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x20090496);
867 regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x30090496);
868 regmap_write(priv->map, HHI_PCIE_PLL_CNTL1, 0x00000000);
869 regmap_write(priv->map, HHI_PCIE_PLL_CNTL2, 0x00001100);
870 regmap_write(priv->map, HHI_PCIE_PLL_CNTL3, 0x10058e00);
871 regmap_write(priv->map, HHI_PCIE_PLL_CNTL4, 0x000100c0);
872 regmap_write(priv->map, HHI_PCIE_PLL_CNTL5, 0x68000048);
873 regmap_write(priv->map, HHI_PCIE_PLL_CNTL5, 0x68000068);
875 regmap_write(priv->map, HHI_PCIE_PLL_CNTL4, 0x008100c0);
877 regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x34090496);
878 regmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x14090496);
880 regmap_write(priv->map, HHI_PCIE_PLL_CNTL2, 0x00001000);
881 regmap_update_bits(priv->map, HHI_PCIE_PLL_CNTL0,
882 0x1f << 16, 9 << 16);
887 static int meson_clk_set_parent(struct clk *clk, struct clk *parent)
889 return meson_mux_set_parent(clk, clk->id, parent->id);
892 static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
893 ulong rate, ulong current_rate)
895 if (current_rate == rate)
900 case CLKID_FIXED_PLL:
902 case CLKID_FCLK_DIV2:
903 case CLKID_FCLK_DIV3:
904 case CLKID_FCLK_DIV4:
905 case CLKID_FCLK_DIV5:
906 case CLKID_FCLK_DIV7:
911 if (current_rate != rate)
914 return meson_pcie_pll_set_rate(clk, rate);
918 return meson_clk_set_rate_by_id(clk,
919 meson_mux_get_parent(clk, CLKID_VPU), rate,
923 return meson_clk_set_rate_by_id(clk,
924 meson_mux_get_parent(clk, CLKID_VAPB_SEL),
927 return meson_div_set_rate(clk, CLKID_VPU_0_DIV, rate,
930 return meson_div_set_rate(clk, CLKID_VPU_1_DIV, rate,
933 return meson_div_set_rate(clk, CLKID_VAPB_0_DIV, rate,
936 return meson_div_set_rate(clk, CLKID_VAPB_1_DIV, rate,
938 case CLKID_VPU_0_DIV:
939 case CLKID_VPU_1_DIV:
940 case CLKID_VAPB_0_DIV:
941 case CLKID_VAPB_1_DIV:
943 return meson_div_set_rate(clk, id, rate, current_rate);
945 return meson_clk_set_rate_by_id(clk, CLKID_HDMI_DIV,
954 static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
956 ulong current_rate = meson_clk_get_rate_by_id(clk, clk->id);
959 if (IS_ERR_VALUE(current_rate))
962 debug("%s: setting rate of %ld from %ld to %ld\n",
963 __func__, clk->id, current_rate, rate);
965 ret = meson_clk_set_rate_by_id(clk, clk->id, rate, current_rate);
966 if (IS_ERR_VALUE(ret))
969 debug("clock %lu has new rate %lu\n", clk->id,
970 meson_clk_get_rate_by_id(clk, clk->id));
975 static int meson_clk_probe(struct udevice *dev)
977 struct meson_clk *priv = dev_get_priv(dev);
979 priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
980 if (IS_ERR(priv->map))
981 return PTR_ERR(priv->map);
984 * Depending on the boot src, the state of the MMC clock might
985 * be different. Reset it to make sure we won't get stuck
987 regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
988 regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
990 debug("meson-clk-g12a: probed\n");
995 static struct clk_ops meson_clk_ops = {
996 .disable = meson_clk_disable,
997 .enable = meson_clk_enable,
998 .get_rate = meson_clk_get_rate,
999 .set_parent = meson_clk_set_parent,
1000 .set_rate = meson_clk_set_rate,
1003 static const struct udevice_id meson_clk_ids[] = {
1004 { .compatible = "amlogic,g12a-clkc" },
1005 { .compatible = "amlogic,g12b-clkc" },
1006 { .compatible = "amlogic,sm1-clkc" },
1010 U_BOOT_DRIVER(meson_clk_g12a) = {
1011 .name = "meson_clk_g12a",
1013 .of_match = meson_clk_ids,
1014 .priv_auto_alloc_size = sizeof(struct meson_clk),
1015 .ops = &meson_clk_ops,
1016 .probe = meson_clk_probe,