1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-G12A Clock Controller Driver
5 * Copyright (c) 2016 Baylibre SAS.
6 * Author: Michael Turquette <mturquette@baylibre.com>
8 * Copyright (c) 2018 Amlogic, inc.
9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
10 * Author: Jian Hu <jian.hu@amlogic.com>
13 #include <linux/clk-provider.h>
14 #include <linux/init.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/clk.h>
21 #include "clk-regmap.h"
22 #include "clk-cpu-dyndiv.h"
23 #include "vid-pll-div.h"
24 #include "meson-eeclk.h"
27 static DEFINE_SPINLOCK(meson_clk_lock);
29 static struct clk_regmap g12a_fixed_pll_dco = {
30 .data = &(struct meson_clk_pll_data){
32 .reg_off = HHI_FIX_PLL_CNTL0,
37 .reg_off = HHI_FIX_PLL_CNTL0,
42 .reg_off = HHI_FIX_PLL_CNTL0,
47 .reg_off = HHI_FIX_PLL_CNTL1,
52 .reg_off = HHI_FIX_PLL_CNTL0,
57 .reg_off = HHI_FIX_PLL_CNTL0,
62 .hw.init = &(struct clk_init_data){
63 .name = "fixed_pll_dco",
64 .ops = &meson_clk_pll_ro_ops,
65 .parent_data = &(const struct clk_parent_data) {
72 static struct clk_regmap g12a_fixed_pll = {
73 .data = &(struct clk_regmap_div_data){
74 .offset = HHI_FIX_PLL_CNTL0,
77 .flags = CLK_DIVIDER_POWER_OF_TWO,
79 .hw.init = &(struct clk_init_data){
81 .ops = &clk_regmap_divider_ro_ops,
82 .parent_hws = (const struct clk_hw *[]) {
83 &g12a_fixed_pll_dco.hw
87 * This clock won't ever change at runtime so
88 * CLK_SET_RATE_PARENT is not required
93 static const struct pll_mult_range g12a_sys_pll_mult_range = {
98 static struct clk_regmap g12a_sys_pll_dco = {
99 .data = &(struct meson_clk_pll_data){
101 .reg_off = HHI_SYS_PLL_CNTL0,
106 .reg_off = HHI_SYS_PLL_CNTL0,
111 .reg_off = HHI_SYS_PLL_CNTL0,
116 .reg_off = HHI_SYS_PLL_CNTL0,
121 .reg_off = HHI_SYS_PLL_CNTL0,
125 .range = &g12a_sys_pll_mult_range,
127 .hw.init = &(struct clk_init_data){
128 .name = "sys_pll_dco",
129 .ops = &meson_clk_pll_ops,
130 .parent_data = &(const struct clk_parent_data) {
134 /* This clock feeds the CPU, avoid disabling it */
135 .flags = CLK_IS_CRITICAL,
139 static struct clk_regmap g12a_sys_pll = {
140 .data = &(struct clk_regmap_div_data){
141 .offset = HHI_SYS_PLL_CNTL0,
144 .flags = CLK_DIVIDER_POWER_OF_TWO,
146 .hw.init = &(struct clk_init_data){
148 .ops = &clk_regmap_divider_ops,
149 .parent_hws = (const struct clk_hw *[]) {
153 .flags = CLK_SET_RATE_PARENT,
157 static struct clk_regmap g12b_sys1_pll_dco = {
158 .data = &(struct meson_clk_pll_data){
160 .reg_off = HHI_SYS1_PLL_CNTL0,
165 .reg_off = HHI_SYS1_PLL_CNTL0,
170 .reg_off = HHI_SYS1_PLL_CNTL0,
175 .reg_off = HHI_SYS1_PLL_CNTL0,
180 .reg_off = HHI_SYS1_PLL_CNTL0,
184 .range = &g12a_sys_pll_mult_range,
186 .hw.init = &(struct clk_init_data){
187 .name = "sys1_pll_dco",
188 .ops = &meson_clk_pll_ops,
189 .parent_data = &(const struct clk_parent_data) {
193 /* This clock feeds the CPU, avoid disabling it */
194 .flags = CLK_IS_CRITICAL,
198 static struct clk_regmap g12b_sys1_pll = {
199 .data = &(struct clk_regmap_div_data){
200 .offset = HHI_SYS1_PLL_CNTL0,
203 .flags = CLK_DIVIDER_POWER_OF_TWO,
205 .hw.init = &(struct clk_init_data){
207 .ops = &clk_regmap_divider_ops,
208 .parent_hws = (const struct clk_hw *[]) {
209 &g12b_sys1_pll_dco.hw
212 .flags = CLK_SET_RATE_PARENT,
216 static struct clk_regmap g12a_sys_pll_div16_en = {
217 .data = &(struct clk_regmap_gate_data){
218 .offset = HHI_SYS_CPU_CLK_CNTL1,
221 .hw.init = &(struct clk_init_data) {
222 .name = "sys_pll_div16_en",
223 .ops = &clk_regmap_gate_ro_ops,
224 .parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
227 * This clock is used to debug the sys_pll range
228 * Linux should not change it at runtime
233 static struct clk_regmap g12b_sys1_pll_div16_en = {
234 .data = &(struct clk_regmap_gate_data){
235 .offset = HHI_SYS_CPUB_CLK_CNTL1,
238 .hw.init = &(struct clk_init_data) {
239 .name = "sys1_pll_div16_en",
240 .ops = &clk_regmap_gate_ro_ops,
241 .parent_hws = (const struct clk_hw *[]) {
246 * This clock is used to debug the sys_pll range
247 * Linux should not change it at runtime
252 static struct clk_fixed_factor g12a_sys_pll_div16 = {
255 .hw.init = &(struct clk_init_data){
256 .name = "sys_pll_div16",
257 .ops = &clk_fixed_factor_ops,
258 .parent_hws = (const struct clk_hw *[]) {
259 &g12a_sys_pll_div16_en.hw
265 static struct clk_fixed_factor g12b_sys1_pll_div16 = {
268 .hw.init = &(struct clk_init_data){
269 .name = "sys1_pll_div16",
270 .ops = &clk_fixed_factor_ops,
271 .parent_hws = (const struct clk_hw *[]) {
272 &g12b_sys1_pll_div16_en.hw
278 static struct clk_fixed_factor g12a_fclk_div2_div = {
281 .hw.init = &(struct clk_init_data){
282 .name = "fclk_div2_div",
283 .ops = &clk_fixed_factor_ops,
284 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
289 static struct clk_regmap g12a_fclk_div2 = {
290 .data = &(struct clk_regmap_gate_data){
291 .offset = HHI_FIX_PLL_CNTL1,
294 .hw.init = &(struct clk_init_data){
296 .ops = &clk_regmap_gate_ops,
297 .parent_hws = (const struct clk_hw *[]) {
298 &g12a_fclk_div2_div.hw
304 static struct clk_fixed_factor g12a_fclk_div3_div = {
307 .hw.init = &(struct clk_init_data){
308 .name = "fclk_div3_div",
309 .ops = &clk_fixed_factor_ops,
310 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
315 static struct clk_regmap g12a_fclk_div3 = {
316 .data = &(struct clk_regmap_gate_data){
317 .offset = HHI_FIX_PLL_CNTL1,
320 .hw.init = &(struct clk_init_data){
322 .ops = &clk_regmap_gate_ops,
323 .parent_hws = (const struct clk_hw *[]) {
324 &g12a_fclk_div3_div.hw
328 * This clock is used by the resident firmware and is required
329 * by the platform to operate correctly.
330 * Until the following condition are met, we need this clock to
331 * be marked as critical:
332 * a) Mark the clock used by a firmware resource, if possible
333 * b) CCF has a clock hand-off mechanism to make the sure the
334 * clock stays on until the proper driver comes along
336 .flags = CLK_IS_CRITICAL,
340 /* Datasheet names this field as "premux0" */
341 static struct clk_regmap g12a_cpu_clk_premux0 = {
342 .data = &(struct clk_regmap_mux_data){
343 .offset = HHI_SYS_CPU_CLK_CNTL0,
347 .hw.init = &(struct clk_init_data){
348 .name = "cpu_clk_dyn0_sel",
349 .ops = &clk_regmap_mux_ops,
350 .parent_data = (const struct clk_parent_data []) {
351 { .fw_name = "xtal", },
352 { .hw = &g12a_fclk_div2.hw },
353 { .hw = &g12a_fclk_div3.hw },
356 /* This sub-tree is used a parking clock */
357 .flags = CLK_SET_RATE_NO_REPARENT,
361 /* Datasheet names this field as "premux1" */
362 static struct clk_regmap g12a_cpu_clk_premux1 = {
363 .data = &(struct clk_regmap_mux_data){
364 .offset = HHI_SYS_CPU_CLK_CNTL0,
368 .hw.init = &(struct clk_init_data){
369 .name = "cpu_clk_dyn1_sel",
370 .ops = &clk_regmap_mux_ops,
371 .parent_data = (const struct clk_parent_data []) {
372 { .fw_name = "xtal", },
373 { .hw = &g12a_fclk_div2.hw },
374 { .hw = &g12a_fclk_div3.hw },
377 /* This sub-tree is used a parking clock */
378 .flags = CLK_SET_RATE_NO_REPARENT
382 /* Datasheet names this field as "mux0_divn_tcnt" */
383 static struct clk_regmap g12a_cpu_clk_mux0_div = {
384 .data = &(struct meson_clk_cpu_dyndiv_data){
386 .reg_off = HHI_SYS_CPU_CLK_CNTL0,
391 .reg_off = HHI_SYS_CPU_CLK_CNTL0,
396 .hw.init = &(struct clk_init_data){
397 .name = "cpu_clk_dyn0_div",
398 .ops = &meson_clk_cpu_dyndiv_ops,
399 .parent_hws = (const struct clk_hw *[]) {
400 &g12a_cpu_clk_premux0.hw
403 .flags = CLK_SET_RATE_PARENT,
407 /* Datasheet names this field as "postmux0" */
408 static struct clk_regmap g12a_cpu_clk_postmux0 = {
409 .data = &(struct clk_regmap_mux_data){
410 .offset = HHI_SYS_CPU_CLK_CNTL0,
414 .hw.init = &(struct clk_init_data){
415 .name = "cpu_clk_dyn0",
416 .ops = &clk_regmap_mux_ops,
417 .parent_hws = (const struct clk_hw *[]) {
418 &g12a_cpu_clk_premux0.hw,
419 &g12a_cpu_clk_mux0_div.hw,
422 .flags = CLK_SET_RATE_PARENT,
426 /* Datasheet names this field as "Mux1_divn_tcnt" */
427 static struct clk_regmap g12a_cpu_clk_mux1_div = {
428 .data = &(struct clk_regmap_div_data){
429 .offset = HHI_SYS_CPU_CLK_CNTL0,
433 .hw.init = &(struct clk_init_data){
434 .name = "cpu_clk_dyn1_div",
435 .ops = &clk_regmap_divider_ro_ops,
436 .parent_hws = (const struct clk_hw *[]) {
437 &g12a_cpu_clk_premux1.hw
443 /* Datasheet names this field as "postmux1" */
444 static struct clk_regmap g12a_cpu_clk_postmux1 = {
445 .data = &(struct clk_regmap_mux_data){
446 .offset = HHI_SYS_CPU_CLK_CNTL0,
450 .hw.init = &(struct clk_init_data){
451 .name = "cpu_clk_dyn1",
452 .ops = &clk_regmap_mux_ops,
453 .parent_hws = (const struct clk_hw *[]) {
454 &g12a_cpu_clk_premux1.hw,
455 &g12a_cpu_clk_mux1_div.hw,
458 /* This sub-tree is used a parking clock */
459 .flags = CLK_SET_RATE_NO_REPARENT,
463 /* Datasheet names this field as "Final_dyn_mux_sel" */
464 static struct clk_regmap g12a_cpu_clk_dyn = {
465 .data = &(struct clk_regmap_mux_data){
466 .offset = HHI_SYS_CPU_CLK_CNTL0,
470 .hw.init = &(struct clk_init_data){
471 .name = "cpu_clk_dyn",
472 .ops = &clk_regmap_mux_ops,
473 .parent_hws = (const struct clk_hw *[]) {
474 &g12a_cpu_clk_postmux0.hw,
475 &g12a_cpu_clk_postmux1.hw,
478 .flags = CLK_SET_RATE_PARENT,
482 /* Datasheet names this field as "Final_mux_sel" */
483 static struct clk_regmap g12a_cpu_clk = {
484 .data = &(struct clk_regmap_mux_data){
485 .offset = HHI_SYS_CPU_CLK_CNTL0,
489 .hw.init = &(struct clk_init_data){
491 .ops = &clk_regmap_mux_ops,
492 .parent_hws = (const struct clk_hw *[]) {
493 &g12a_cpu_clk_dyn.hw,
497 .flags = CLK_SET_RATE_PARENT,
501 /* Datasheet names this field as "Final_mux_sel" */
502 static struct clk_regmap g12b_cpu_clk = {
503 .data = &(struct clk_regmap_mux_data){
504 .offset = HHI_SYS_CPU_CLK_CNTL0,
508 .hw.init = &(struct clk_init_data){
510 .ops = &clk_regmap_mux_ops,
511 .parent_hws = (const struct clk_hw *[]) {
512 &g12a_cpu_clk_dyn.hw,
516 .flags = CLK_SET_RATE_PARENT,
520 /* Datasheet names this field as "premux0" */
521 static struct clk_regmap g12b_cpub_clk_premux0 = {
522 .data = &(struct clk_regmap_mux_data){
523 .offset = HHI_SYS_CPUB_CLK_CNTL,
527 .hw.init = &(struct clk_init_data){
528 .name = "cpub_clk_dyn0_sel",
529 .ops = &clk_regmap_mux_ops,
530 .parent_data = (const struct clk_parent_data []) {
531 { .fw_name = "xtal", },
532 { .hw = &g12a_fclk_div2.hw },
533 { .hw = &g12a_fclk_div3.hw },
539 /* Datasheet names this field as "mux0_divn_tcnt" */
540 static struct clk_regmap g12b_cpub_clk_mux0_div = {
541 .data = &(struct meson_clk_cpu_dyndiv_data){
543 .reg_off = HHI_SYS_CPUB_CLK_CNTL,
548 .reg_off = HHI_SYS_CPUB_CLK_CNTL,
553 .hw.init = &(struct clk_init_data){
554 .name = "cpub_clk_dyn0_div",
555 .ops = &meson_clk_cpu_dyndiv_ops,
556 .parent_hws = (const struct clk_hw *[]) {
557 &g12b_cpub_clk_premux0.hw
560 .flags = CLK_SET_RATE_PARENT,
564 /* Datasheet names this field as "postmux0" */
565 static struct clk_regmap g12b_cpub_clk_postmux0 = {
566 .data = &(struct clk_regmap_mux_data){
567 .offset = HHI_SYS_CPUB_CLK_CNTL,
571 .hw.init = &(struct clk_init_data){
572 .name = "cpub_clk_dyn0",
573 .ops = &clk_regmap_mux_ops,
574 .parent_hws = (const struct clk_hw *[]) {
575 &g12b_cpub_clk_premux0.hw,
576 &g12b_cpub_clk_mux0_div.hw
579 .flags = CLK_SET_RATE_PARENT,
583 /* Datasheet names this field as "premux1" */
584 static struct clk_regmap g12b_cpub_clk_premux1 = {
585 .data = &(struct clk_regmap_mux_data){
586 .offset = HHI_SYS_CPUB_CLK_CNTL,
590 .hw.init = &(struct clk_init_data){
591 .name = "cpub_clk_dyn1_sel",
592 .ops = &clk_regmap_mux_ops,
593 .parent_data = (const struct clk_parent_data []) {
594 { .fw_name = "xtal", },
595 { .hw = &g12a_fclk_div2.hw },
596 { .hw = &g12a_fclk_div3.hw },
599 /* This sub-tree is used a parking clock */
600 .flags = CLK_SET_RATE_NO_REPARENT,
604 /* Datasheet names this field as "Mux1_divn_tcnt" */
605 static struct clk_regmap g12b_cpub_clk_mux1_div = {
606 .data = &(struct clk_regmap_div_data){
607 .offset = HHI_SYS_CPUB_CLK_CNTL,
611 .hw.init = &(struct clk_init_data){
612 .name = "cpub_clk_dyn1_div",
613 .ops = &clk_regmap_divider_ro_ops,
614 .parent_hws = (const struct clk_hw *[]) {
615 &g12b_cpub_clk_premux1.hw
621 /* Datasheet names this field as "postmux1" */
622 static struct clk_regmap g12b_cpub_clk_postmux1 = {
623 .data = &(struct clk_regmap_mux_data){
624 .offset = HHI_SYS_CPUB_CLK_CNTL,
628 .hw.init = &(struct clk_init_data){
629 .name = "cpub_clk_dyn1",
630 .ops = &clk_regmap_mux_ops,
631 .parent_hws = (const struct clk_hw *[]) {
632 &g12b_cpub_clk_premux1.hw,
633 &g12b_cpub_clk_mux1_div.hw
636 /* This sub-tree is used a parking clock */
637 .flags = CLK_SET_RATE_NO_REPARENT,
641 /* Datasheet names this field as "Final_dyn_mux_sel" */
642 static struct clk_regmap g12b_cpub_clk_dyn = {
643 .data = &(struct clk_regmap_mux_data){
644 .offset = HHI_SYS_CPUB_CLK_CNTL,
648 .hw.init = &(struct clk_init_data){
649 .name = "cpub_clk_dyn",
650 .ops = &clk_regmap_mux_ops,
651 .parent_hws = (const struct clk_hw *[]) {
652 &g12b_cpub_clk_postmux0.hw,
653 &g12b_cpub_clk_postmux1.hw
656 .flags = CLK_SET_RATE_PARENT,
660 /* Datasheet names this field as "Final_mux_sel" */
661 static struct clk_regmap g12b_cpub_clk = {
662 .data = &(struct clk_regmap_mux_data){
663 .offset = HHI_SYS_CPUB_CLK_CNTL,
667 .hw.init = &(struct clk_init_data){
669 .ops = &clk_regmap_mux_ops,
670 .parent_hws = (const struct clk_hw *[]) {
671 &g12b_cpub_clk_dyn.hw,
675 .flags = CLK_SET_RATE_PARENT,
679 static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,
680 unsigned long event, void *data)
682 if (event == POST_RATE_CHANGE || event == PRE_RATE_CHANGE) {
683 /* Wait for clock propagation before/after changing the mux */
691 static struct notifier_block g12a_cpu_clk_mux_nb = {
692 .notifier_call = g12a_cpu_clk_mux_notifier_cb,
695 struct g12a_cpu_clk_postmux_nb_data {
696 struct notifier_block nb;
698 struct clk_hw *cpu_clk_dyn;
699 struct clk_hw *cpu_clk_postmux0;
700 struct clk_hw *cpu_clk_postmux1;
701 struct clk_hw *cpu_clk_premux1;
704 static int g12a_cpu_clk_postmux_notifier_cb(struct notifier_block *nb,
705 unsigned long event, void *data)
707 struct g12a_cpu_clk_postmux_nb_data *nb_data =
708 container_of(nb, struct g12a_cpu_clk_postmux_nb_data, nb);
711 case PRE_RATE_CHANGE:
713 * This notifier means cpu_clk_postmux0 clock will be changed
714 * to feed cpu_clk, this is the current path :
717 * \- cpu_clk_postmux0
718 * \- cpu_clk_muxX_div
720 * \- fclk_div3 or fclk_div2
723 * \- fclk_div3 or fclk_div2
726 /* Setup cpu_clk_premux1 to xtal */
727 clk_hw_set_parent(nb_data->cpu_clk_premux1,
730 /* Setup cpu_clk_postmux1 to bypass divider */
731 clk_hw_set_parent(nb_data->cpu_clk_postmux1,
732 nb_data->cpu_clk_premux1);
734 /* Switch to parking clk on cpu_clk_postmux1 */
735 clk_hw_set_parent(nb_data->cpu_clk_dyn,
736 nb_data->cpu_clk_postmux1);
739 * Now, cpu_clk is 24MHz in the current path :
742 * \- cpu_clk_postmux1
751 case POST_RATE_CHANGE:
753 * The cpu_clk_postmux0 has ben updated, now switch back
754 * cpu_clk_dyn to cpu_clk_postmux0 and take the changes
758 /* Configure cpu_clk_dyn back to cpu_clk_postmux0 */
759 clk_hw_set_parent(nb_data->cpu_clk_dyn,
760 nb_data->cpu_clk_postmux0);
766 * \- cpu_clk_postmux0
767 * \- cpu_clk_muxX_div
769 * \- fclk_div3 or fclk_div2
772 * \- fclk_div3 or fclk_div2
784 static struct g12a_cpu_clk_postmux_nb_data g12a_cpu_clk_postmux0_nb_data = {
785 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
786 .cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
787 .cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
788 .cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
789 .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
792 static struct g12a_cpu_clk_postmux_nb_data g12b_cpub_clk_postmux0_nb_data = {
793 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
794 .cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
795 .cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
796 .cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
797 .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
800 struct g12a_sys_pll_nb_data {
801 struct notifier_block nb;
802 struct clk_hw *sys_pll;
803 struct clk_hw *cpu_clk;
804 struct clk_hw *cpu_clk_dyn;
807 static int g12a_sys_pll_notifier_cb(struct notifier_block *nb,
808 unsigned long event, void *data)
810 struct g12a_sys_pll_nb_data *nb_data =
811 container_of(nb, struct g12a_sys_pll_nb_data, nb);
814 case PRE_RATE_CHANGE:
816 * This notifier means sys_pll clock will be changed
817 * to feed cpu_clk, this the current path :
823 /* Configure cpu_clk to use cpu_clk_dyn */
824 clk_hw_set_parent(nb_data->cpu_clk,
825 nb_data->cpu_clk_dyn);
828 * Now, cpu_clk uses the dyn path
832 * \- cpu_clk_dynX_sel
833 * \- cpu_clk_dynX_div
834 * \- xtal/fclk_div2/fclk_div3
835 * \- xtal/fclk_div2/fclk_div3
842 case POST_RATE_CHANGE:
844 * The sys_pll has ben updated, now switch back cpu_clk to
848 /* Configure cpu_clk to use sys_pll */
849 clk_hw_set_parent(nb_data->cpu_clk,
867 static struct g12a_sys_pll_nb_data g12a_sys_pll_nb_data = {
868 .sys_pll = &g12a_sys_pll.hw,
869 .cpu_clk = &g12a_cpu_clk.hw,
870 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
871 .nb.notifier_call = g12a_sys_pll_notifier_cb,
874 /* G12B first CPU cluster uses sys1_pll */
875 static struct g12a_sys_pll_nb_data g12b_cpu_clk_sys1_pll_nb_data = {
876 .sys_pll = &g12b_sys1_pll.hw,
877 .cpu_clk = &g12b_cpu_clk.hw,
878 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
879 .nb.notifier_call = g12a_sys_pll_notifier_cb,
882 /* G12B second CPU cluster uses sys_pll */
883 static struct g12a_sys_pll_nb_data g12b_cpub_clk_sys_pll_nb_data = {
884 .sys_pll = &g12a_sys_pll.hw,
885 .cpu_clk = &g12b_cpub_clk.hw,
886 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
887 .nb.notifier_call = g12a_sys_pll_notifier_cb,
890 static struct clk_regmap g12a_cpu_clk_div16_en = {
891 .data = &(struct clk_regmap_gate_data){
892 .offset = HHI_SYS_CPU_CLK_CNTL1,
895 .hw.init = &(struct clk_init_data) {
896 .name = "cpu_clk_div16_en",
897 .ops = &clk_regmap_gate_ro_ops,
898 .parent_hws = (const struct clk_hw *[]) {
903 * This clock is used to debug the cpu_clk range
904 * Linux should not change it at runtime
909 static struct clk_regmap g12b_cpub_clk_div16_en = {
910 .data = &(struct clk_regmap_gate_data){
911 .offset = HHI_SYS_CPUB_CLK_CNTL1,
914 .hw.init = &(struct clk_init_data) {
915 .name = "cpub_clk_div16_en",
916 .ops = &clk_regmap_gate_ro_ops,
917 .parent_hws = (const struct clk_hw *[]) {
922 * This clock is used to debug the cpu_clk range
923 * Linux should not change it at runtime
928 static struct clk_fixed_factor g12a_cpu_clk_div16 = {
931 .hw.init = &(struct clk_init_data){
932 .name = "cpu_clk_div16",
933 .ops = &clk_fixed_factor_ops,
934 .parent_hws = (const struct clk_hw *[]) {
935 &g12a_cpu_clk_div16_en.hw
941 static struct clk_fixed_factor g12b_cpub_clk_div16 = {
944 .hw.init = &(struct clk_init_data){
945 .name = "cpub_clk_div16",
946 .ops = &clk_fixed_factor_ops,
947 .parent_hws = (const struct clk_hw *[]) {
948 &g12b_cpub_clk_div16_en.hw
954 static struct clk_regmap g12a_cpu_clk_apb_div = {
955 .data = &(struct clk_regmap_div_data){
956 .offset = HHI_SYS_CPU_CLK_CNTL1,
959 .flags = CLK_DIVIDER_POWER_OF_TWO,
961 .hw.init = &(struct clk_init_data){
962 .name = "cpu_clk_apb_div",
963 .ops = &clk_regmap_divider_ro_ops,
964 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
969 static struct clk_regmap g12a_cpu_clk_apb = {
970 .data = &(struct clk_regmap_gate_data){
971 .offset = HHI_SYS_CPU_CLK_CNTL1,
974 .hw.init = &(struct clk_init_data) {
975 .name = "cpu_clk_apb",
976 .ops = &clk_regmap_gate_ro_ops,
977 .parent_hws = (const struct clk_hw *[]) {
978 &g12a_cpu_clk_apb_div.hw
982 * This clock is set by the ROM monitor code,
983 * Linux should not change it at runtime
988 static struct clk_regmap g12a_cpu_clk_atb_div = {
989 .data = &(struct clk_regmap_div_data){
990 .offset = HHI_SYS_CPU_CLK_CNTL1,
993 .flags = CLK_DIVIDER_POWER_OF_TWO,
995 .hw.init = &(struct clk_init_data){
996 .name = "cpu_clk_atb_div",
997 .ops = &clk_regmap_divider_ro_ops,
998 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1003 static struct clk_regmap g12a_cpu_clk_atb = {
1004 .data = &(struct clk_regmap_gate_data){
1005 .offset = HHI_SYS_CPU_CLK_CNTL1,
1008 .hw.init = &(struct clk_init_data) {
1009 .name = "cpu_clk_atb",
1010 .ops = &clk_regmap_gate_ro_ops,
1011 .parent_hws = (const struct clk_hw *[]) {
1012 &g12a_cpu_clk_atb_div.hw
1016 * This clock is set by the ROM monitor code,
1017 * Linux should not change it at runtime
1022 static struct clk_regmap g12a_cpu_clk_axi_div = {
1023 .data = &(struct clk_regmap_div_data){
1024 .offset = HHI_SYS_CPU_CLK_CNTL1,
1027 .flags = CLK_DIVIDER_POWER_OF_TWO,
1029 .hw.init = &(struct clk_init_data){
1030 .name = "cpu_clk_axi_div",
1031 .ops = &clk_regmap_divider_ro_ops,
1032 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1037 static struct clk_regmap g12a_cpu_clk_axi = {
1038 .data = &(struct clk_regmap_gate_data){
1039 .offset = HHI_SYS_CPU_CLK_CNTL1,
1042 .hw.init = &(struct clk_init_data) {
1043 .name = "cpu_clk_axi",
1044 .ops = &clk_regmap_gate_ro_ops,
1045 .parent_hws = (const struct clk_hw *[]) {
1046 &g12a_cpu_clk_axi_div.hw
1050 * This clock is set by the ROM monitor code,
1051 * Linux should not change it at runtime
1056 static struct clk_regmap g12a_cpu_clk_trace_div = {
1057 .data = &(struct clk_regmap_div_data){
1058 .offset = HHI_SYS_CPU_CLK_CNTL1,
1061 .flags = CLK_DIVIDER_POWER_OF_TWO,
1063 .hw.init = &(struct clk_init_data){
1064 .name = "cpu_clk_trace_div",
1065 .ops = &clk_regmap_divider_ro_ops,
1066 .parent_data = &(const struct clk_parent_data) {
1069 * G12A and G12B have different cpu_clks (with
1070 * different struct clk_hw). We fallback to the global
1071 * naming string mechanism so cpu_clk_trace_div picks
1072 * up the appropriate one.
1081 static struct clk_regmap g12a_cpu_clk_trace = {
1082 .data = &(struct clk_regmap_gate_data){
1083 .offset = HHI_SYS_CPU_CLK_CNTL1,
1086 .hw.init = &(struct clk_init_data) {
1087 .name = "cpu_clk_trace",
1088 .ops = &clk_regmap_gate_ro_ops,
1089 .parent_hws = (const struct clk_hw *[]) {
1090 &g12a_cpu_clk_trace_div.hw
1094 * This clock is set by the ROM monitor code,
1095 * Linux should not change it at runtime
1100 static struct clk_fixed_factor g12b_cpub_clk_div2 = {
1103 .hw.init = &(struct clk_init_data){
1104 .name = "cpub_clk_div2",
1105 .ops = &clk_fixed_factor_ops,
1106 .parent_hws = (const struct clk_hw *[]) {
1113 static struct clk_fixed_factor g12b_cpub_clk_div3 = {
1116 .hw.init = &(struct clk_init_data){
1117 .name = "cpub_clk_div3",
1118 .ops = &clk_fixed_factor_ops,
1119 .parent_hws = (const struct clk_hw *[]) {
1126 static struct clk_fixed_factor g12b_cpub_clk_div4 = {
1129 .hw.init = &(struct clk_init_data){
1130 .name = "cpub_clk_div4",
1131 .ops = &clk_fixed_factor_ops,
1132 .parent_hws = (const struct clk_hw *[]) {
1139 static struct clk_fixed_factor g12b_cpub_clk_div5 = {
1142 .hw.init = &(struct clk_init_data){
1143 .name = "cpub_clk_div5",
1144 .ops = &clk_fixed_factor_ops,
1145 .parent_hws = (const struct clk_hw *[]) {
1152 static struct clk_fixed_factor g12b_cpub_clk_div6 = {
1155 .hw.init = &(struct clk_init_data){
1156 .name = "cpub_clk_div6",
1157 .ops = &clk_fixed_factor_ops,
1158 .parent_hws = (const struct clk_hw *[]) {
1165 static struct clk_fixed_factor g12b_cpub_clk_div7 = {
1168 .hw.init = &(struct clk_init_data){
1169 .name = "cpub_clk_div7",
1170 .ops = &clk_fixed_factor_ops,
1171 .parent_hws = (const struct clk_hw *[]) {
1178 static struct clk_fixed_factor g12b_cpub_clk_div8 = {
1181 .hw.init = &(struct clk_init_data){
1182 .name = "cpub_clk_div8",
1183 .ops = &clk_fixed_factor_ops,
1184 .parent_hws = (const struct clk_hw *[]) {
1191 static u32 mux_table_cpub[] = { 1, 2, 3, 4, 5, 6, 7 };
1192 static struct clk_regmap g12b_cpub_clk_apb_sel = {
1193 .data = &(struct clk_regmap_mux_data){
1194 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1197 .table = mux_table_cpub,
1199 .hw.init = &(struct clk_init_data){
1200 .name = "cpub_clk_apb_sel",
1201 .ops = &clk_regmap_mux_ro_ops,
1202 .parent_hws = (const struct clk_hw *[]) {
1203 &g12b_cpub_clk_div2.hw,
1204 &g12b_cpub_clk_div3.hw,
1205 &g12b_cpub_clk_div4.hw,
1206 &g12b_cpub_clk_div5.hw,
1207 &g12b_cpub_clk_div6.hw,
1208 &g12b_cpub_clk_div7.hw,
1209 &g12b_cpub_clk_div8.hw
1215 static struct clk_regmap g12b_cpub_clk_apb = {
1216 .data = &(struct clk_regmap_gate_data){
1217 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1219 .flags = CLK_GATE_SET_TO_DISABLE,
1221 .hw.init = &(struct clk_init_data) {
1222 .name = "cpub_clk_apb",
1223 .ops = &clk_regmap_gate_ro_ops,
1224 .parent_hws = (const struct clk_hw *[]) {
1225 &g12b_cpub_clk_apb_sel.hw
1229 * This clock is set by the ROM monitor code,
1230 * Linux should not change it at runtime
1235 static struct clk_regmap g12b_cpub_clk_atb_sel = {
1236 .data = &(struct clk_regmap_mux_data){
1237 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1240 .table = mux_table_cpub,
1242 .hw.init = &(struct clk_init_data){
1243 .name = "cpub_clk_atb_sel",
1244 .ops = &clk_regmap_mux_ro_ops,
1245 .parent_hws = (const struct clk_hw *[]) {
1246 &g12b_cpub_clk_div2.hw,
1247 &g12b_cpub_clk_div3.hw,
1248 &g12b_cpub_clk_div4.hw,
1249 &g12b_cpub_clk_div5.hw,
1250 &g12b_cpub_clk_div6.hw,
1251 &g12b_cpub_clk_div7.hw,
1252 &g12b_cpub_clk_div8.hw
1258 static struct clk_regmap g12b_cpub_clk_atb = {
1259 .data = &(struct clk_regmap_gate_data){
1260 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1262 .flags = CLK_GATE_SET_TO_DISABLE,
1264 .hw.init = &(struct clk_init_data) {
1265 .name = "cpub_clk_atb",
1266 .ops = &clk_regmap_gate_ro_ops,
1267 .parent_hws = (const struct clk_hw *[]) {
1268 &g12b_cpub_clk_atb_sel.hw
1272 * This clock is set by the ROM monitor code,
1273 * Linux should not change it at runtime
1278 static struct clk_regmap g12b_cpub_clk_axi_sel = {
1279 .data = &(struct clk_regmap_mux_data){
1280 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1283 .table = mux_table_cpub,
1285 .hw.init = &(struct clk_init_data){
1286 .name = "cpub_clk_axi_sel",
1287 .ops = &clk_regmap_mux_ro_ops,
1288 .parent_hws = (const struct clk_hw *[]) {
1289 &g12b_cpub_clk_div2.hw,
1290 &g12b_cpub_clk_div3.hw,
1291 &g12b_cpub_clk_div4.hw,
1292 &g12b_cpub_clk_div5.hw,
1293 &g12b_cpub_clk_div6.hw,
1294 &g12b_cpub_clk_div7.hw,
1295 &g12b_cpub_clk_div8.hw
1301 static struct clk_regmap g12b_cpub_clk_axi = {
1302 .data = &(struct clk_regmap_gate_data){
1303 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1305 .flags = CLK_GATE_SET_TO_DISABLE,
1307 .hw.init = &(struct clk_init_data) {
1308 .name = "cpub_clk_axi",
1309 .ops = &clk_regmap_gate_ro_ops,
1310 .parent_hws = (const struct clk_hw *[]) {
1311 &g12b_cpub_clk_axi_sel.hw
1315 * This clock is set by the ROM monitor code,
1316 * Linux should not change it at runtime
1321 static struct clk_regmap g12b_cpub_clk_trace_sel = {
1322 .data = &(struct clk_regmap_mux_data){
1323 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1326 .table = mux_table_cpub,
1328 .hw.init = &(struct clk_init_data){
1329 .name = "cpub_clk_trace_sel",
1330 .ops = &clk_regmap_mux_ro_ops,
1331 .parent_hws = (const struct clk_hw *[]) {
1332 &g12b_cpub_clk_div2.hw,
1333 &g12b_cpub_clk_div3.hw,
1334 &g12b_cpub_clk_div4.hw,
1335 &g12b_cpub_clk_div5.hw,
1336 &g12b_cpub_clk_div6.hw,
1337 &g12b_cpub_clk_div7.hw,
1338 &g12b_cpub_clk_div8.hw
1344 static struct clk_regmap g12b_cpub_clk_trace = {
1345 .data = &(struct clk_regmap_gate_data){
1346 .offset = HHI_SYS_CPUB_CLK_CNTL1,
1348 .flags = CLK_GATE_SET_TO_DISABLE,
1350 .hw.init = &(struct clk_init_data) {
1351 .name = "cpub_clk_trace",
1352 .ops = &clk_regmap_gate_ro_ops,
1353 .parent_hws = (const struct clk_hw *[]) {
1354 &g12b_cpub_clk_trace_sel.hw
1358 * This clock is set by the ROM monitor code,
1359 * Linux should not change it at runtime
1364 static const struct pll_mult_range g12a_gp0_pll_mult_range = {
1370 * Internal gp0 pll emulation configuration parameters
1372 static const struct reg_sequence g12a_gp0_init_regs[] = {
1373 { .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 },
1374 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 },
1375 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 },
1376 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 },
1377 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 },
1378 { .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000 },
1381 static struct clk_regmap g12a_gp0_pll_dco = {
1382 .data = &(struct meson_clk_pll_data){
1384 .reg_off = HHI_GP0_PLL_CNTL0,
1389 .reg_off = HHI_GP0_PLL_CNTL0,
1394 .reg_off = HHI_GP0_PLL_CNTL0,
1399 .reg_off = HHI_GP0_PLL_CNTL1,
1404 .reg_off = HHI_GP0_PLL_CNTL0,
1409 .reg_off = HHI_GP0_PLL_CNTL0,
1413 .range = &g12a_gp0_pll_mult_range,
1414 .init_regs = g12a_gp0_init_regs,
1415 .init_count = ARRAY_SIZE(g12a_gp0_init_regs),
1417 .hw.init = &(struct clk_init_data){
1418 .name = "gp0_pll_dco",
1419 .ops = &meson_clk_pll_ops,
1420 .parent_data = &(const struct clk_parent_data) {
1427 static struct clk_regmap g12a_gp0_pll = {
1428 .data = &(struct clk_regmap_div_data){
1429 .offset = HHI_GP0_PLL_CNTL0,
1432 .flags = (CLK_DIVIDER_POWER_OF_TWO |
1433 CLK_DIVIDER_ROUND_CLOSEST),
1435 .hw.init = &(struct clk_init_data){
1437 .ops = &clk_regmap_divider_ops,
1438 .parent_hws = (const struct clk_hw *[]) {
1439 &g12a_gp0_pll_dco.hw
1442 .flags = CLK_SET_RATE_PARENT,
1447 * Internal hifi pll emulation configuration parameters
1449 static const struct reg_sequence g12a_hifi_init_regs[] = {
1450 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 },
1451 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 },
1452 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 },
1453 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 },
1454 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 },
1455 { .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 },
1458 static struct clk_regmap g12a_hifi_pll_dco = {
1459 .data = &(struct meson_clk_pll_data){
1461 .reg_off = HHI_HIFI_PLL_CNTL0,
1466 .reg_off = HHI_HIFI_PLL_CNTL0,
1471 .reg_off = HHI_HIFI_PLL_CNTL0,
1476 .reg_off = HHI_HIFI_PLL_CNTL1,
1481 .reg_off = HHI_HIFI_PLL_CNTL0,
1486 .reg_off = HHI_HIFI_PLL_CNTL0,
1490 .range = &g12a_gp0_pll_mult_range,
1491 .init_regs = g12a_hifi_init_regs,
1492 .init_count = ARRAY_SIZE(g12a_hifi_init_regs),
1493 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
1495 .hw.init = &(struct clk_init_data){
1496 .name = "hifi_pll_dco",
1497 .ops = &meson_clk_pll_ops,
1498 .parent_data = &(const struct clk_parent_data) {
1505 static struct clk_regmap g12a_hifi_pll = {
1506 .data = &(struct clk_regmap_div_data){
1507 .offset = HHI_HIFI_PLL_CNTL0,
1510 .flags = (CLK_DIVIDER_POWER_OF_TWO |
1511 CLK_DIVIDER_ROUND_CLOSEST),
1513 .hw.init = &(struct clk_init_data){
1515 .ops = &clk_regmap_divider_ops,
1516 .parent_hws = (const struct clk_hw *[]) {
1517 &g12a_hifi_pll_dco.hw
1520 .flags = CLK_SET_RATE_PARENT,
1525 * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
1526 * 100MHz reference clock for the PCIe Analog PHY, and thus requires
1527 * a strict register sequence to enable the PLL.
1529 static const struct reg_sequence g12a_pcie_pll_init_regs[] = {
1530 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496 },
1531 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496 },
1532 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000 },
1533 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100 },
1534 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00 },
1535 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0 },
1536 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048 },
1537 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 },
1538 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 },
1539 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496 },
1540 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 },
1541 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000 },
1544 /* Keep a single entry table for recalc/round_rate() ops */
1545 static const struct pll_params_table g12a_pcie_pll_table[] = {
1550 static struct clk_regmap g12a_pcie_pll_dco = {
1551 .data = &(struct meson_clk_pll_data){
1553 .reg_off = HHI_PCIE_PLL_CNTL0,
1558 .reg_off = HHI_PCIE_PLL_CNTL0,
1563 .reg_off = HHI_PCIE_PLL_CNTL0,
1568 .reg_off = HHI_PCIE_PLL_CNTL1,
1573 .reg_off = HHI_PCIE_PLL_CNTL0,
1578 .reg_off = HHI_PCIE_PLL_CNTL0,
1582 .table = g12a_pcie_pll_table,
1583 .init_regs = g12a_pcie_pll_init_regs,
1584 .init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),
1586 .hw.init = &(struct clk_init_data){
1587 .name = "pcie_pll_dco",
1588 .ops = &meson_clk_pcie_pll_ops,
1589 .parent_data = &(const struct clk_parent_data) {
1596 static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
1599 .hw.init = &(struct clk_init_data){
1600 .name = "pcie_pll_dco_div2",
1601 .ops = &clk_fixed_factor_ops,
1602 .parent_hws = (const struct clk_hw *[]) {
1603 &g12a_pcie_pll_dco.hw
1606 .flags = CLK_SET_RATE_PARENT,
1610 static struct clk_regmap g12a_pcie_pll_od = {
1611 .data = &(struct clk_regmap_div_data){
1612 .offset = HHI_PCIE_PLL_CNTL0,
1615 .flags = CLK_DIVIDER_ROUND_CLOSEST |
1616 CLK_DIVIDER_ONE_BASED |
1617 CLK_DIVIDER_ALLOW_ZERO,
1619 .hw.init = &(struct clk_init_data){
1620 .name = "pcie_pll_od",
1621 .ops = &clk_regmap_divider_ops,
1622 .parent_hws = (const struct clk_hw *[]) {
1623 &g12a_pcie_pll_dco_div2.hw
1626 .flags = CLK_SET_RATE_PARENT,
1630 static struct clk_fixed_factor g12a_pcie_pll = {
1633 .hw.init = &(struct clk_init_data){
1634 .name = "pcie_pll_pll",
1635 .ops = &clk_fixed_factor_ops,
1636 .parent_hws = (const struct clk_hw *[]) {
1637 &g12a_pcie_pll_od.hw
1640 .flags = CLK_SET_RATE_PARENT,
1644 static struct clk_regmap g12a_hdmi_pll_dco = {
1645 .data = &(struct meson_clk_pll_data){
1647 .reg_off = HHI_HDMI_PLL_CNTL0,
1652 .reg_off = HHI_HDMI_PLL_CNTL0,
1657 .reg_off = HHI_HDMI_PLL_CNTL0,
1662 .reg_off = HHI_HDMI_PLL_CNTL1,
1667 .reg_off = HHI_HDMI_PLL_CNTL0,
1672 .reg_off = HHI_HDMI_PLL_CNTL0,
1677 .hw.init = &(struct clk_init_data){
1678 .name = "hdmi_pll_dco",
1679 .ops = &meson_clk_pll_ro_ops,
1680 .parent_data = &(const struct clk_parent_data) {
1685 * Display directly handle hdmi pll registers ATM, we need
1686 * NOCACHE to keep our view of the clock as accurate as possible
1688 .flags = CLK_GET_RATE_NOCACHE,
1692 static struct clk_regmap g12a_hdmi_pll_od = {
1693 .data = &(struct clk_regmap_div_data){
1694 .offset = HHI_HDMI_PLL_CNTL0,
1697 .flags = CLK_DIVIDER_POWER_OF_TWO,
1699 .hw.init = &(struct clk_init_data){
1700 .name = "hdmi_pll_od",
1701 .ops = &clk_regmap_divider_ro_ops,
1702 .parent_hws = (const struct clk_hw *[]) {
1703 &g12a_hdmi_pll_dco.hw
1706 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
1710 static struct clk_regmap g12a_hdmi_pll_od2 = {
1711 .data = &(struct clk_regmap_div_data){
1712 .offset = HHI_HDMI_PLL_CNTL0,
1715 .flags = CLK_DIVIDER_POWER_OF_TWO,
1717 .hw.init = &(struct clk_init_data){
1718 .name = "hdmi_pll_od2",
1719 .ops = &clk_regmap_divider_ro_ops,
1720 .parent_hws = (const struct clk_hw *[]) {
1721 &g12a_hdmi_pll_od.hw
1724 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
1728 static struct clk_regmap g12a_hdmi_pll = {
1729 .data = &(struct clk_regmap_div_data){
1730 .offset = HHI_HDMI_PLL_CNTL0,
1733 .flags = CLK_DIVIDER_POWER_OF_TWO,
1735 .hw.init = &(struct clk_init_data){
1737 .ops = &clk_regmap_divider_ro_ops,
1738 .parent_hws = (const struct clk_hw *[]) {
1739 &g12a_hdmi_pll_od2.hw
1742 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
1746 static struct clk_fixed_factor g12a_fclk_div4_div = {
1749 .hw.init = &(struct clk_init_data){
1750 .name = "fclk_div4_div",
1751 .ops = &clk_fixed_factor_ops,
1752 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
1757 static struct clk_regmap g12a_fclk_div4 = {
1758 .data = &(struct clk_regmap_gate_data){
1759 .offset = HHI_FIX_PLL_CNTL1,
1762 .hw.init = &(struct clk_init_data){
1763 .name = "fclk_div4",
1764 .ops = &clk_regmap_gate_ops,
1765 .parent_hws = (const struct clk_hw *[]) {
1766 &g12a_fclk_div4_div.hw
1772 static struct clk_fixed_factor g12a_fclk_div5_div = {
1775 .hw.init = &(struct clk_init_data){
1776 .name = "fclk_div5_div",
1777 .ops = &clk_fixed_factor_ops,
1778 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
1783 static struct clk_regmap g12a_fclk_div5 = {
1784 .data = &(struct clk_regmap_gate_data){
1785 .offset = HHI_FIX_PLL_CNTL1,
1788 .hw.init = &(struct clk_init_data){
1789 .name = "fclk_div5",
1790 .ops = &clk_regmap_gate_ops,
1791 .parent_hws = (const struct clk_hw *[]) {
1792 &g12a_fclk_div5_div.hw
1798 static struct clk_fixed_factor g12a_fclk_div7_div = {
1801 .hw.init = &(struct clk_init_data){
1802 .name = "fclk_div7_div",
1803 .ops = &clk_fixed_factor_ops,
1804 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
1809 static struct clk_regmap g12a_fclk_div7 = {
1810 .data = &(struct clk_regmap_gate_data){
1811 .offset = HHI_FIX_PLL_CNTL1,
1814 .hw.init = &(struct clk_init_data){
1815 .name = "fclk_div7",
1816 .ops = &clk_regmap_gate_ops,
1817 .parent_hws = (const struct clk_hw *[]) {
1818 &g12a_fclk_div7_div.hw
1824 static struct clk_fixed_factor g12a_fclk_div2p5_div = {
1827 .hw.init = &(struct clk_init_data){
1828 .name = "fclk_div2p5_div",
1829 .ops = &clk_fixed_factor_ops,
1830 .parent_hws = (const struct clk_hw *[]) {
1831 &g12a_fixed_pll_dco.hw
1837 static struct clk_regmap g12a_fclk_div2p5 = {
1838 .data = &(struct clk_regmap_gate_data){
1839 .offset = HHI_FIX_PLL_CNTL1,
1842 .hw.init = &(struct clk_init_data){
1843 .name = "fclk_div2p5",
1844 .ops = &clk_regmap_gate_ops,
1845 .parent_hws = (const struct clk_hw *[]) {
1846 &g12a_fclk_div2p5_div.hw
1852 static struct clk_fixed_factor g12a_mpll_50m_div = {
1855 .hw.init = &(struct clk_init_data){
1856 .name = "mpll_50m_div",
1857 .ops = &clk_fixed_factor_ops,
1858 .parent_hws = (const struct clk_hw *[]) {
1859 &g12a_fixed_pll_dco.hw
1865 static struct clk_regmap g12a_mpll_50m = {
1866 .data = &(struct clk_regmap_mux_data){
1867 .offset = HHI_FIX_PLL_CNTL3,
1871 .hw.init = &(struct clk_init_data){
1873 .ops = &clk_regmap_mux_ro_ops,
1874 .parent_data = (const struct clk_parent_data []) {
1875 { .fw_name = "xtal", },
1876 { .hw = &g12a_mpll_50m_div.hw },
1882 static struct clk_fixed_factor g12a_mpll_prediv = {
1885 .hw.init = &(struct clk_init_data){
1886 .name = "mpll_prediv",
1887 .ops = &clk_fixed_factor_ops,
1888 .parent_hws = (const struct clk_hw *[]) {
1889 &g12a_fixed_pll_dco.hw
1895 static const struct reg_sequence g12a_mpll0_init_regs[] = {
1896 { .reg = HHI_MPLL_CNTL2, .def = 0x40000033 },
1899 static struct clk_regmap g12a_mpll0_div = {
1900 .data = &(struct meson_clk_mpll_data){
1902 .reg_off = HHI_MPLL_CNTL1,
1907 .reg_off = HHI_MPLL_CNTL1,
1912 .reg_off = HHI_MPLL_CNTL1,
1917 .reg_off = HHI_MPLL_CNTL1,
1921 .lock = &meson_clk_lock,
1922 .init_regs = g12a_mpll0_init_regs,
1923 .init_count = ARRAY_SIZE(g12a_mpll0_init_regs),
1925 .hw.init = &(struct clk_init_data){
1926 .name = "mpll0_div",
1927 .ops = &meson_clk_mpll_ops,
1928 .parent_hws = (const struct clk_hw *[]) {
1929 &g12a_mpll_prediv.hw
1935 static struct clk_regmap g12a_mpll0 = {
1936 .data = &(struct clk_regmap_gate_data){
1937 .offset = HHI_MPLL_CNTL1,
1940 .hw.init = &(struct clk_init_data){
1942 .ops = &clk_regmap_gate_ops,
1943 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
1945 .flags = CLK_SET_RATE_PARENT,
1949 static const struct reg_sequence g12a_mpll1_init_regs[] = {
1950 { .reg = HHI_MPLL_CNTL4, .def = 0x40000033 },
1953 static struct clk_regmap g12a_mpll1_div = {
1954 .data = &(struct meson_clk_mpll_data){
1956 .reg_off = HHI_MPLL_CNTL3,
1961 .reg_off = HHI_MPLL_CNTL3,
1966 .reg_off = HHI_MPLL_CNTL3,
1971 .reg_off = HHI_MPLL_CNTL3,
1975 .lock = &meson_clk_lock,
1976 .init_regs = g12a_mpll1_init_regs,
1977 .init_count = ARRAY_SIZE(g12a_mpll1_init_regs),
1979 .hw.init = &(struct clk_init_data){
1980 .name = "mpll1_div",
1981 .ops = &meson_clk_mpll_ops,
1982 .parent_hws = (const struct clk_hw *[]) {
1983 &g12a_mpll_prediv.hw
1989 static struct clk_regmap g12a_mpll1 = {
1990 .data = &(struct clk_regmap_gate_data){
1991 .offset = HHI_MPLL_CNTL3,
1994 .hw.init = &(struct clk_init_data){
1996 .ops = &clk_regmap_gate_ops,
1997 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
1999 .flags = CLK_SET_RATE_PARENT,
2003 static const struct reg_sequence g12a_mpll2_init_regs[] = {
2004 { .reg = HHI_MPLL_CNTL6, .def = 0x40000033 },
2007 static struct clk_regmap g12a_mpll2_div = {
2008 .data = &(struct meson_clk_mpll_data){
2010 .reg_off = HHI_MPLL_CNTL5,
2015 .reg_off = HHI_MPLL_CNTL5,
2020 .reg_off = HHI_MPLL_CNTL5,
2025 .reg_off = HHI_MPLL_CNTL5,
2029 .lock = &meson_clk_lock,
2030 .init_regs = g12a_mpll2_init_regs,
2031 .init_count = ARRAY_SIZE(g12a_mpll2_init_regs),
2033 .hw.init = &(struct clk_init_data){
2034 .name = "mpll2_div",
2035 .ops = &meson_clk_mpll_ops,
2036 .parent_hws = (const struct clk_hw *[]) {
2037 &g12a_mpll_prediv.hw
2043 static struct clk_regmap g12a_mpll2 = {
2044 .data = &(struct clk_regmap_gate_data){
2045 .offset = HHI_MPLL_CNTL5,
2048 .hw.init = &(struct clk_init_data){
2050 .ops = &clk_regmap_gate_ops,
2051 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
2053 .flags = CLK_SET_RATE_PARENT,
2057 static const struct reg_sequence g12a_mpll3_init_regs[] = {
2058 { .reg = HHI_MPLL_CNTL8, .def = 0x40000033 },
2061 static struct clk_regmap g12a_mpll3_div = {
2062 .data = &(struct meson_clk_mpll_data){
2064 .reg_off = HHI_MPLL_CNTL7,
2069 .reg_off = HHI_MPLL_CNTL7,
2074 .reg_off = HHI_MPLL_CNTL7,
2079 .reg_off = HHI_MPLL_CNTL7,
2083 .lock = &meson_clk_lock,
2084 .init_regs = g12a_mpll3_init_regs,
2085 .init_count = ARRAY_SIZE(g12a_mpll3_init_regs),
2087 .hw.init = &(struct clk_init_data){
2088 .name = "mpll3_div",
2089 .ops = &meson_clk_mpll_ops,
2090 .parent_hws = (const struct clk_hw *[]) {
2091 &g12a_mpll_prediv.hw
2097 static struct clk_regmap g12a_mpll3 = {
2098 .data = &(struct clk_regmap_gate_data){
2099 .offset = HHI_MPLL_CNTL7,
2102 .hw.init = &(struct clk_init_data){
2104 .ops = &clk_regmap_gate_ops,
2105 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
2107 .flags = CLK_SET_RATE_PARENT,
2111 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
2112 static const struct clk_parent_data clk81_parent_data[] = {
2113 { .fw_name = "xtal", },
2114 { .hw = &g12a_fclk_div7.hw },
2115 { .hw = &g12a_mpll1.hw },
2116 { .hw = &g12a_mpll2.hw },
2117 { .hw = &g12a_fclk_div4.hw },
2118 { .hw = &g12a_fclk_div3.hw },
2119 { .hw = &g12a_fclk_div5.hw },
2122 static struct clk_regmap g12a_mpeg_clk_sel = {
2123 .data = &(struct clk_regmap_mux_data){
2124 .offset = HHI_MPEG_CLK_CNTL,
2127 .table = mux_table_clk81,
2129 .hw.init = &(struct clk_init_data){
2130 .name = "mpeg_clk_sel",
2131 .ops = &clk_regmap_mux_ro_ops,
2132 .parent_data = clk81_parent_data,
2133 .num_parents = ARRAY_SIZE(clk81_parent_data),
2137 static struct clk_regmap g12a_mpeg_clk_div = {
2138 .data = &(struct clk_regmap_div_data){
2139 .offset = HHI_MPEG_CLK_CNTL,
2143 .hw.init = &(struct clk_init_data){
2144 .name = "mpeg_clk_div",
2145 .ops = &clk_regmap_divider_ops,
2146 .parent_hws = (const struct clk_hw *[]) {
2147 &g12a_mpeg_clk_sel.hw
2150 .flags = CLK_SET_RATE_PARENT,
2154 static struct clk_regmap g12a_clk81 = {
2155 .data = &(struct clk_regmap_gate_data){
2156 .offset = HHI_MPEG_CLK_CNTL,
2159 .hw.init = &(struct clk_init_data){
2161 .ops = &clk_regmap_gate_ops,
2162 .parent_hws = (const struct clk_hw *[]) {
2163 &g12a_mpeg_clk_div.hw
2166 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
2170 static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = {
2171 { .fw_name = "xtal", },
2172 { .hw = &g12a_fclk_div2.hw },
2173 { .hw = &g12a_fclk_div3.hw },
2174 { .hw = &g12a_fclk_div5.hw },
2175 { .hw = &g12a_fclk_div7.hw },
2177 * Following these parent clocks, we should also have had mpll2, mpll3
2178 * and gp0_pll but these clocks are too precious to be used here. All
2179 * the necessary rates for MMC and NAND operation can be acheived using
2180 * g12a_ee_core or fclk_div clocks
2185 static struct clk_regmap g12a_sd_emmc_a_clk0_sel = {
2186 .data = &(struct clk_regmap_mux_data){
2187 .offset = HHI_SD_EMMC_CLK_CNTL,
2191 .hw.init = &(struct clk_init_data) {
2192 .name = "sd_emmc_a_clk0_sel",
2193 .ops = &clk_regmap_mux_ops,
2194 .parent_data = g12a_sd_emmc_clk0_parent_data,
2195 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2196 .flags = CLK_SET_RATE_PARENT,
2200 static struct clk_regmap g12a_sd_emmc_a_clk0_div = {
2201 .data = &(struct clk_regmap_div_data){
2202 .offset = HHI_SD_EMMC_CLK_CNTL,
2206 .hw.init = &(struct clk_init_data) {
2207 .name = "sd_emmc_a_clk0_div",
2208 .ops = &clk_regmap_divider_ops,
2209 .parent_hws = (const struct clk_hw *[]) {
2210 &g12a_sd_emmc_a_clk0_sel.hw
2213 .flags = CLK_SET_RATE_PARENT,
2217 static struct clk_regmap g12a_sd_emmc_a_clk0 = {
2218 .data = &(struct clk_regmap_gate_data){
2219 .offset = HHI_SD_EMMC_CLK_CNTL,
2222 .hw.init = &(struct clk_init_data){
2223 .name = "sd_emmc_a_clk0",
2224 .ops = &clk_regmap_gate_ops,
2225 .parent_hws = (const struct clk_hw *[]) {
2226 &g12a_sd_emmc_a_clk0_div.hw
2229 .flags = CLK_SET_RATE_PARENT,
2234 static struct clk_regmap g12a_sd_emmc_b_clk0_sel = {
2235 .data = &(struct clk_regmap_mux_data){
2236 .offset = HHI_SD_EMMC_CLK_CNTL,
2240 .hw.init = &(struct clk_init_data) {
2241 .name = "sd_emmc_b_clk0_sel",
2242 .ops = &clk_regmap_mux_ops,
2243 .parent_data = g12a_sd_emmc_clk0_parent_data,
2244 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2245 .flags = CLK_SET_RATE_PARENT,
2249 static struct clk_regmap g12a_sd_emmc_b_clk0_div = {
2250 .data = &(struct clk_regmap_div_data){
2251 .offset = HHI_SD_EMMC_CLK_CNTL,
2255 .hw.init = &(struct clk_init_data) {
2256 .name = "sd_emmc_b_clk0_div",
2257 .ops = &clk_regmap_divider_ops,
2258 .parent_hws = (const struct clk_hw *[]) {
2259 &g12a_sd_emmc_b_clk0_sel.hw
2262 .flags = CLK_SET_RATE_PARENT,
2266 static struct clk_regmap g12a_sd_emmc_b_clk0 = {
2267 .data = &(struct clk_regmap_gate_data){
2268 .offset = HHI_SD_EMMC_CLK_CNTL,
2271 .hw.init = &(struct clk_init_data){
2272 .name = "sd_emmc_b_clk0",
2273 .ops = &clk_regmap_gate_ops,
2274 .parent_hws = (const struct clk_hw *[]) {
2275 &g12a_sd_emmc_b_clk0_div.hw
2278 .flags = CLK_SET_RATE_PARENT,
2282 /* EMMC/NAND clock */
2283 static struct clk_regmap g12a_sd_emmc_c_clk0_sel = {
2284 .data = &(struct clk_regmap_mux_data){
2285 .offset = HHI_NAND_CLK_CNTL,
2289 .hw.init = &(struct clk_init_data) {
2290 .name = "sd_emmc_c_clk0_sel",
2291 .ops = &clk_regmap_mux_ops,
2292 .parent_data = g12a_sd_emmc_clk0_parent_data,
2293 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2294 .flags = CLK_SET_RATE_PARENT,
2298 static struct clk_regmap g12a_sd_emmc_c_clk0_div = {
2299 .data = &(struct clk_regmap_div_data){
2300 .offset = HHI_NAND_CLK_CNTL,
2304 .hw.init = &(struct clk_init_data) {
2305 .name = "sd_emmc_c_clk0_div",
2306 .ops = &clk_regmap_divider_ops,
2307 .parent_hws = (const struct clk_hw *[]) {
2308 &g12a_sd_emmc_c_clk0_sel.hw
2311 .flags = CLK_SET_RATE_PARENT,
2315 static struct clk_regmap g12a_sd_emmc_c_clk0 = {
2316 .data = &(struct clk_regmap_gate_data){
2317 .offset = HHI_NAND_CLK_CNTL,
2320 .hw.init = &(struct clk_init_data){
2321 .name = "sd_emmc_c_clk0",
2322 .ops = &clk_regmap_gate_ops,
2323 .parent_hws = (const struct clk_hw *[]) {
2324 &g12a_sd_emmc_c_clk0_div.hw
2327 .flags = CLK_SET_RATE_PARENT,
2333 static struct clk_regmap g12a_vid_pll_div = {
2334 .data = &(struct meson_vid_pll_div_data){
2336 .reg_off = HHI_VID_PLL_CLK_DIV,
2341 .reg_off = HHI_VID_PLL_CLK_DIV,
2346 .hw.init = &(struct clk_init_data) {
2347 .name = "vid_pll_div",
2348 .ops = &meson_vid_pll_div_ro_ops,
2349 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
2351 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2355 static const struct clk_hw *g12a_vid_pll_parent_hws[] = {
2356 &g12a_vid_pll_div.hw,
2360 static struct clk_regmap g12a_vid_pll_sel = {
2361 .data = &(struct clk_regmap_mux_data){
2362 .offset = HHI_VID_PLL_CLK_DIV,
2366 .hw.init = &(struct clk_init_data){
2367 .name = "vid_pll_sel",
2368 .ops = &clk_regmap_mux_ops,
2370 * bit 18 selects from 2 possible parents:
2371 * vid_pll_div or hdmi_pll
2373 .parent_hws = g12a_vid_pll_parent_hws,
2374 .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_hws),
2375 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2379 static struct clk_regmap g12a_vid_pll = {
2380 .data = &(struct clk_regmap_gate_data){
2381 .offset = HHI_VID_PLL_CLK_DIV,
2384 .hw.init = &(struct clk_init_data) {
2386 .ops = &clk_regmap_gate_ops,
2387 .parent_hws = (const struct clk_hw *[]) {
2388 &g12a_vid_pll_sel.hw
2391 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2397 static const struct clk_hw *g12a_vpu_parent_hws[] = {
2408 static struct clk_regmap g12a_vpu_0_sel = {
2409 .data = &(struct clk_regmap_mux_data){
2410 .offset = HHI_VPU_CLK_CNTL,
2414 .hw.init = &(struct clk_init_data){
2415 .name = "vpu_0_sel",
2416 .ops = &clk_regmap_mux_ops,
2417 .parent_hws = g12a_vpu_parent_hws,
2418 .num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
2419 .flags = CLK_SET_RATE_NO_REPARENT,
2423 static struct clk_regmap g12a_vpu_0_div = {
2424 .data = &(struct clk_regmap_div_data){
2425 .offset = HHI_VPU_CLK_CNTL,
2429 .hw.init = &(struct clk_init_data){
2430 .name = "vpu_0_div",
2431 .ops = &clk_regmap_divider_ops,
2432 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
2434 .flags = CLK_SET_RATE_PARENT,
2438 static struct clk_regmap g12a_vpu_0 = {
2439 .data = &(struct clk_regmap_gate_data){
2440 .offset = HHI_VPU_CLK_CNTL,
2443 .hw.init = &(struct clk_init_data) {
2445 .ops = &clk_regmap_gate_ops,
2446 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
2448 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2452 static struct clk_regmap g12a_vpu_1_sel = {
2453 .data = &(struct clk_regmap_mux_data){
2454 .offset = HHI_VPU_CLK_CNTL,
2458 .hw.init = &(struct clk_init_data){
2459 .name = "vpu_1_sel",
2460 .ops = &clk_regmap_mux_ops,
2461 .parent_hws = g12a_vpu_parent_hws,
2462 .num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
2463 .flags = CLK_SET_RATE_NO_REPARENT,
2467 static struct clk_regmap g12a_vpu_1_div = {
2468 .data = &(struct clk_regmap_div_data){
2469 .offset = HHI_VPU_CLK_CNTL,
2473 .hw.init = &(struct clk_init_data){
2474 .name = "vpu_1_div",
2475 .ops = &clk_regmap_divider_ops,
2476 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
2478 .flags = CLK_SET_RATE_PARENT,
2482 static struct clk_regmap g12a_vpu_1 = {
2483 .data = &(struct clk_regmap_gate_data){
2484 .offset = HHI_VPU_CLK_CNTL,
2487 .hw.init = &(struct clk_init_data) {
2489 .ops = &clk_regmap_gate_ops,
2490 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
2492 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2496 static struct clk_regmap g12a_vpu = {
2497 .data = &(struct clk_regmap_mux_data){
2498 .offset = HHI_VPU_CLK_CNTL,
2502 .hw.init = &(struct clk_init_data){
2504 .ops = &clk_regmap_mux_ops,
2506 * bit 31 selects from 2 possible parents:
2509 .parent_hws = (const struct clk_hw *[]) {
2514 .flags = CLK_SET_RATE_NO_REPARENT,
2520 static const struct clk_hw *g12a_vdec_parent_hws[] = {
2521 &g12a_fclk_div2p5.hw,
2530 static struct clk_regmap g12a_vdec_1_sel = {
2531 .data = &(struct clk_regmap_mux_data){
2532 .offset = HHI_VDEC_CLK_CNTL,
2535 .flags = CLK_MUX_ROUND_CLOSEST,
2537 .hw.init = &(struct clk_init_data){
2538 .name = "vdec_1_sel",
2539 .ops = &clk_regmap_mux_ops,
2540 .parent_hws = g12a_vdec_parent_hws,
2541 .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2542 .flags = CLK_SET_RATE_PARENT,
2546 static struct clk_regmap g12a_vdec_1_div = {
2547 .data = &(struct clk_regmap_div_data){
2548 .offset = HHI_VDEC_CLK_CNTL,
2551 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2553 .hw.init = &(struct clk_init_data){
2554 .name = "vdec_1_div",
2555 .ops = &clk_regmap_divider_ops,
2556 .parent_hws = (const struct clk_hw *[]) {
2560 .flags = CLK_SET_RATE_PARENT,
2564 static struct clk_regmap g12a_vdec_1 = {
2565 .data = &(struct clk_regmap_gate_data){
2566 .offset = HHI_VDEC_CLK_CNTL,
2569 .hw.init = &(struct clk_init_data) {
2571 .ops = &clk_regmap_gate_ops,
2572 .parent_hws = (const struct clk_hw *[]) {
2576 .flags = CLK_SET_RATE_PARENT,
2580 static struct clk_regmap g12a_vdec_hevcf_sel = {
2581 .data = &(struct clk_regmap_mux_data){
2582 .offset = HHI_VDEC2_CLK_CNTL,
2585 .flags = CLK_MUX_ROUND_CLOSEST,
2587 .hw.init = &(struct clk_init_data){
2588 .name = "vdec_hevcf_sel",
2589 .ops = &clk_regmap_mux_ops,
2590 .parent_hws = g12a_vdec_parent_hws,
2591 .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2592 .flags = CLK_SET_RATE_PARENT,
2596 static struct clk_regmap g12a_vdec_hevcf_div = {
2597 .data = &(struct clk_regmap_div_data){
2598 .offset = HHI_VDEC2_CLK_CNTL,
2601 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2603 .hw.init = &(struct clk_init_data){
2604 .name = "vdec_hevcf_div",
2605 .ops = &clk_regmap_divider_ops,
2606 .parent_hws = (const struct clk_hw *[]) {
2607 &g12a_vdec_hevcf_sel.hw
2610 .flags = CLK_SET_RATE_PARENT,
2614 static struct clk_regmap g12a_vdec_hevcf = {
2615 .data = &(struct clk_regmap_gate_data){
2616 .offset = HHI_VDEC2_CLK_CNTL,
2619 .hw.init = &(struct clk_init_data) {
2620 .name = "vdec_hevcf",
2621 .ops = &clk_regmap_gate_ops,
2622 .parent_hws = (const struct clk_hw *[]) {
2623 &g12a_vdec_hevcf_div.hw
2626 .flags = CLK_SET_RATE_PARENT,
2630 static struct clk_regmap g12a_vdec_hevc_sel = {
2631 .data = &(struct clk_regmap_mux_data){
2632 .offset = HHI_VDEC2_CLK_CNTL,
2635 .flags = CLK_MUX_ROUND_CLOSEST,
2637 .hw.init = &(struct clk_init_data){
2638 .name = "vdec_hevc_sel",
2639 .ops = &clk_regmap_mux_ops,
2640 .parent_hws = g12a_vdec_parent_hws,
2641 .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2642 .flags = CLK_SET_RATE_PARENT,
2646 static struct clk_regmap g12a_vdec_hevc_div = {
2647 .data = &(struct clk_regmap_div_data){
2648 .offset = HHI_VDEC2_CLK_CNTL,
2651 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2653 .hw.init = &(struct clk_init_data){
2654 .name = "vdec_hevc_div",
2655 .ops = &clk_regmap_divider_ops,
2656 .parent_hws = (const struct clk_hw *[]) {
2657 &g12a_vdec_hevc_sel.hw
2660 .flags = CLK_SET_RATE_PARENT,
2664 static struct clk_regmap g12a_vdec_hevc = {
2665 .data = &(struct clk_regmap_gate_data){
2666 .offset = HHI_VDEC2_CLK_CNTL,
2669 .hw.init = &(struct clk_init_data) {
2670 .name = "vdec_hevc",
2671 .ops = &clk_regmap_gate_ops,
2672 .parent_hws = (const struct clk_hw *[]) {
2673 &g12a_vdec_hevc_div.hw
2676 .flags = CLK_SET_RATE_PARENT,
2682 static const struct clk_hw *g12a_vapb_parent_hws[] = {
2690 &g12a_fclk_div2p5.hw,
2693 static struct clk_regmap g12a_vapb_0_sel = {
2694 .data = &(struct clk_regmap_mux_data){
2695 .offset = HHI_VAPBCLK_CNTL,
2699 .hw.init = &(struct clk_init_data){
2700 .name = "vapb_0_sel",
2701 .ops = &clk_regmap_mux_ops,
2702 .parent_hws = g12a_vapb_parent_hws,
2703 .num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
2704 .flags = CLK_SET_RATE_NO_REPARENT,
2708 static struct clk_regmap g12a_vapb_0_div = {
2709 .data = &(struct clk_regmap_div_data){
2710 .offset = HHI_VAPBCLK_CNTL,
2714 .hw.init = &(struct clk_init_data){
2715 .name = "vapb_0_div",
2716 .ops = &clk_regmap_divider_ops,
2717 .parent_hws = (const struct clk_hw *[]) {
2721 .flags = CLK_SET_RATE_PARENT,
2725 static struct clk_regmap g12a_vapb_0 = {
2726 .data = &(struct clk_regmap_gate_data){
2727 .offset = HHI_VAPBCLK_CNTL,
2730 .hw.init = &(struct clk_init_data) {
2732 .ops = &clk_regmap_gate_ops,
2733 .parent_hws = (const struct clk_hw *[]) {
2737 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2741 static struct clk_regmap g12a_vapb_1_sel = {
2742 .data = &(struct clk_regmap_mux_data){
2743 .offset = HHI_VAPBCLK_CNTL,
2747 .hw.init = &(struct clk_init_data){
2748 .name = "vapb_1_sel",
2749 .ops = &clk_regmap_mux_ops,
2750 .parent_hws = g12a_vapb_parent_hws,
2751 .num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
2752 .flags = CLK_SET_RATE_NO_REPARENT,
2756 static struct clk_regmap g12a_vapb_1_div = {
2757 .data = &(struct clk_regmap_div_data){
2758 .offset = HHI_VAPBCLK_CNTL,
2762 .hw.init = &(struct clk_init_data){
2763 .name = "vapb_1_div",
2764 .ops = &clk_regmap_divider_ops,
2765 .parent_hws = (const struct clk_hw *[]) {
2769 .flags = CLK_SET_RATE_PARENT,
2773 static struct clk_regmap g12a_vapb_1 = {
2774 .data = &(struct clk_regmap_gate_data){
2775 .offset = HHI_VAPBCLK_CNTL,
2778 .hw.init = &(struct clk_init_data) {
2780 .ops = &clk_regmap_gate_ops,
2781 .parent_hws = (const struct clk_hw *[]) {
2785 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2789 static struct clk_regmap g12a_vapb_sel = {
2790 .data = &(struct clk_regmap_mux_data){
2791 .offset = HHI_VAPBCLK_CNTL,
2795 .hw.init = &(struct clk_init_data){
2797 .ops = &clk_regmap_mux_ops,
2799 * bit 31 selects from 2 possible parents:
2802 .parent_hws = (const struct clk_hw *[]) {
2807 .flags = CLK_SET_RATE_NO_REPARENT,
2811 static struct clk_regmap g12a_vapb = {
2812 .data = &(struct clk_regmap_gate_data){
2813 .offset = HHI_VAPBCLK_CNTL,
2816 .hw.init = &(struct clk_init_data) {
2818 .ops = &clk_regmap_gate_ops,
2819 .parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
2821 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2825 static const struct clk_hw *g12a_vclk_parent_hws[] = {
2836 static struct clk_regmap g12a_vclk_sel = {
2837 .data = &(struct clk_regmap_mux_data){
2838 .offset = HHI_VID_CLK_CNTL,
2842 .hw.init = &(struct clk_init_data){
2844 .ops = &clk_regmap_mux_ops,
2845 .parent_hws = g12a_vclk_parent_hws,
2846 .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
2847 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2851 static struct clk_regmap g12a_vclk2_sel = {
2852 .data = &(struct clk_regmap_mux_data){
2853 .offset = HHI_VIID_CLK_CNTL,
2857 .hw.init = &(struct clk_init_data){
2858 .name = "vclk2_sel",
2859 .ops = &clk_regmap_mux_ops,
2860 .parent_hws = g12a_vclk_parent_hws,
2861 .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
2862 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2866 static struct clk_regmap g12a_vclk_input = {
2867 .data = &(struct clk_regmap_gate_data){
2868 .offset = HHI_VID_CLK_DIV,
2871 .hw.init = &(struct clk_init_data) {
2872 .name = "vclk_input",
2873 .ops = &clk_regmap_gate_ops,
2874 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
2876 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2880 static struct clk_regmap g12a_vclk2_input = {
2881 .data = &(struct clk_regmap_gate_data){
2882 .offset = HHI_VIID_CLK_DIV,
2885 .hw.init = &(struct clk_init_data) {
2886 .name = "vclk2_input",
2887 .ops = &clk_regmap_gate_ops,
2888 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
2890 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2894 static struct clk_regmap g12a_vclk_div = {
2895 .data = &(struct clk_regmap_div_data){
2896 .offset = HHI_VID_CLK_DIV,
2900 .hw.init = &(struct clk_init_data){
2902 .ops = &clk_regmap_divider_ops,
2903 .parent_hws = (const struct clk_hw *[]) {
2907 .flags = CLK_GET_RATE_NOCACHE,
2911 static struct clk_regmap g12a_vclk2_div = {
2912 .data = &(struct clk_regmap_div_data){
2913 .offset = HHI_VIID_CLK_DIV,
2917 .hw.init = &(struct clk_init_data){
2918 .name = "vclk2_div",
2919 .ops = &clk_regmap_divider_ops,
2920 .parent_hws = (const struct clk_hw *[]) {
2921 &g12a_vclk2_input.hw
2924 .flags = CLK_GET_RATE_NOCACHE,
2928 static struct clk_regmap g12a_vclk = {
2929 .data = &(struct clk_regmap_gate_data){
2930 .offset = HHI_VID_CLK_CNTL,
2933 .hw.init = &(struct clk_init_data) {
2935 .ops = &clk_regmap_gate_ops,
2936 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
2938 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2942 static struct clk_regmap g12a_vclk2 = {
2943 .data = &(struct clk_regmap_gate_data){
2944 .offset = HHI_VIID_CLK_CNTL,
2947 .hw.init = &(struct clk_init_data) {
2949 .ops = &clk_regmap_gate_ops,
2950 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
2952 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2956 static struct clk_regmap g12a_vclk_div1 = {
2957 .data = &(struct clk_regmap_gate_data){
2958 .offset = HHI_VID_CLK_CNTL,
2961 .hw.init = &(struct clk_init_data) {
2962 .name = "vclk_div1",
2963 .ops = &clk_regmap_gate_ops,
2964 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
2966 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2970 static struct clk_regmap g12a_vclk_div2_en = {
2971 .data = &(struct clk_regmap_gate_data){
2972 .offset = HHI_VID_CLK_CNTL,
2975 .hw.init = &(struct clk_init_data) {
2976 .name = "vclk_div2_en",
2977 .ops = &clk_regmap_gate_ops,
2978 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
2980 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2984 static struct clk_regmap g12a_vclk_div4_en = {
2985 .data = &(struct clk_regmap_gate_data){
2986 .offset = HHI_VID_CLK_CNTL,
2989 .hw.init = &(struct clk_init_data) {
2990 .name = "vclk_div4_en",
2991 .ops = &clk_regmap_gate_ops,
2992 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
2994 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2998 static struct clk_regmap g12a_vclk_div6_en = {
2999 .data = &(struct clk_regmap_gate_data){
3000 .offset = HHI_VID_CLK_CNTL,
3003 .hw.init = &(struct clk_init_data) {
3004 .name = "vclk_div6_en",
3005 .ops = &clk_regmap_gate_ops,
3006 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3008 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3012 static struct clk_regmap g12a_vclk_div12_en = {
3013 .data = &(struct clk_regmap_gate_data){
3014 .offset = HHI_VID_CLK_CNTL,
3017 .hw.init = &(struct clk_init_data) {
3018 .name = "vclk_div12_en",
3019 .ops = &clk_regmap_gate_ops,
3020 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3022 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3026 static struct clk_regmap g12a_vclk2_div1 = {
3027 .data = &(struct clk_regmap_gate_data){
3028 .offset = HHI_VIID_CLK_CNTL,
3031 .hw.init = &(struct clk_init_data) {
3032 .name = "vclk2_div1",
3033 .ops = &clk_regmap_gate_ops,
3034 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3036 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3040 static struct clk_regmap g12a_vclk2_div2_en = {
3041 .data = &(struct clk_regmap_gate_data){
3042 .offset = HHI_VIID_CLK_CNTL,
3045 .hw.init = &(struct clk_init_data) {
3046 .name = "vclk2_div2_en",
3047 .ops = &clk_regmap_gate_ops,
3048 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3050 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3054 static struct clk_regmap g12a_vclk2_div4_en = {
3055 .data = &(struct clk_regmap_gate_data){
3056 .offset = HHI_VIID_CLK_CNTL,
3059 .hw.init = &(struct clk_init_data) {
3060 .name = "vclk2_div4_en",
3061 .ops = &clk_regmap_gate_ops,
3062 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3064 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3068 static struct clk_regmap g12a_vclk2_div6_en = {
3069 .data = &(struct clk_regmap_gate_data){
3070 .offset = HHI_VIID_CLK_CNTL,
3073 .hw.init = &(struct clk_init_data) {
3074 .name = "vclk2_div6_en",
3075 .ops = &clk_regmap_gate_ops,
3076 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3078 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3082 static struct clk_regmap g12a_vclk2_div12_en = {
3083 .data = &(struct clk_regmap_gate_data){
3084 .offset = HHI_VIID_CLK_CNTL,
3087 .hw.init = &(struct clk_init_data) {
3088 .name = "vclk2_div12_en",
3089 .ops = &clk_regmap_gate_ops,
3090 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3092 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3096 static struct clk_fixed_factor g12a_vclk_div2 = {
3099 .hw.init = &(struct clk_init_data){
3100 .name = "vclk_div2",
3101 .ops = &clk_fixed_factor_ops,
3102 .parent_hws = (const struct clk_hw *[]) {
3103 &g12a_vclk_div2_en.hw
3109 static struct clk_fixed_factor g12a_vclk_div4 = {
3112 .hw.init = &(struct clk_init_data){
3113 .name = "vclk_div4",
3114 .ops = &clk_fixed_factor_ops,
3115 .parent_hws = (const struct clk_hw *[]) {
3116 &g12a_vclk_div4_en.hw
3122 static struct clk_fixed_factor g12a_vclk_div6 = {
3125 .hw.init = &(struct clk_init_data){
3126 .name = "vclk_div6",
3127 .ops = &clk_fixed_factor_ops,
3128 .parent_hws = (const struct clk_hw *[]) {
3129 &g12a_vclk_div6_en.hw
3135 static struct clk_fixed_factor g12a_vclk_div12 = {
3138 .hw.init = &(struct clk_init_data){
3139 .name = "vclk_div12",
3140 .ops = &clk_fixed_factor_ops,
3141 .parent_hws = (const struct clk_hw *[]) {
3142 &g12a_vclk_div12_en.hw
3148 static struct clk_fixed_factor g12a_vclk2_div2 = {
3151 .hw.init = &(struct clk_init_data){
3152 .name = "vclk2_div2",
3153 .ops = &clk_fixed_factor_ops,
3154 .parent_hws = (const struct clk_hw *[]) {
3155 &g12a_vclk2_div2_en.hw
3161 static struct clk_fixed_factor g12a_vclk2_div4 = {
3164 .hw.init = &(struct clk_init_data){
3165 .name = "vclk2_div4",
3166 .ops = &clk_fixed_factor_ops,
3167 .parent_hws = (const struct clk_hw *[]) {
3168 &g12a_vclk2_div4_en.hw
3174 static struct clk_fixed_factor g12a_vclk2_div6 = {
3177 .hw.init = &(struct clk_init_data){
3178 .name = "vclk2_div6",
3179 .ops = &clk_fixed_factor_ops,
3180 .parent_hws = (const struct clk_hw *[]) {
3181 &g12a_vclk2_div6_en.hw
3187 static struct clk_fixed_factor g12a_vclk2_div12 = {
3190 .hw.init = &(struct clk_init_data){
3191 .name = "vclk2_div12",
3192 .ops = &clk_fixed_factor_ops,
3193 .parent_hws = (const struct clk_hw *[]) {
3194 &g12a_vclk2_div12_en.hw
3200 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3201 static const struct clk_hw *g12a_cts_parent_hws[] = {
3206 &g12a_vclk_div12.hw,
3207 &g12a_vclk2_div1.hw,
3208 &g12a_vclk2_div2.hw,
3209 &g12a_vclk2_div4.hw,
3210 &g12a_vclk2_div6.hw,
3211 &g12a_vclk2_div12.hw,
3214 static struct clk_regmap g12a_cts_enci_sel = {
3215 .data = &(struct clk_regmap_mux_data){
3216 .offset = HHI_VID_CLK_DIV,
3219 .table = mux_table_cts_sel,
3221 .hw.init = &(struct clk_init_data){
3222 .name = "cts_enci_sel",
3223 .ops = &clk_regmap_mux_ops,
3224 .parent_hws = g12a_cts_parent_hws,
3225 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3226 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3230 static struct clk_regmap g12a_cts_encp_sel = {
3231 .data = &(struct clk_regmap_mux_data){
3232 .offset = HHI_VID_CLK_DIV,
3235 .table = mux_table_cts_sel,
3237 .hw.init = &(struct clk_init_data){
3238 .name = "cts_encp_sel",
3239 .ops = &clk_regmap_mux_ops,
3240 .parent_hws = g12a_cts_parent_hws,
3241 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3242 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3246 static struct clk_regmap g12a_cts_vdac_sel = {
3247 .data = &(struct clk_regmap_mux_data){
3248 .offset = HHI_VIID_CLK_DIV,
3251 .table = mux_table_cts_sel,
3253 .hw.init = &(struct clk_init_data){
3254 .name = "cts_vdac_sel",
3255 .ops = &clk_regmap_mux_ops,
3256 .parent_hws = g12a_cts_parent_hws,
3257 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3258 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3262 /* TOFIX: add support for cts_tcon */
3263 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3264 static const struct clk_hw *g12a_cts_hdmi_tx_parent_hws[] = {
3269 &g12a_vclk_div12.hw,
3270 &g12a_vclk2_div1.hw,
3271 &g12a_vclk2_div2.hw,
3272 &g12a_vclk2_div4.hw,
3273 &g12a_vclk2_div6.hw,
3274 &g12a_vclk2_div12.hw,
3277 static struct clk_regmap g12a_hdmi_tx_sel = {
3278 .data = &(struct clk_regmap_mux_data){
3279 .offset = HHI_HDMI_CLK_CNTL,
3282 .table = mux_table_hdmi_tx_sel,
3284 .hw.init = &(struct clk_init_data){
3285 .name = "hdmi_tx_sel",
3286 .ops = &clk_regmap_mux_ops,
3287 .parent_hws = g12a_cts_hdmi_tx_parent_hws,
3288 .num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_hws),
3289 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3293 static struct clk_regmap g12a_cts_enci = {
3294 .data = &(struct clk_regmap_gate_data){
3295 .offset = HHI_VID_CLK_CNTL2,
3298 .hw.init = &(struct clk_init_data) {
3300 .ops = &clk_regmap_gate_ops,
3301 .parent_hws = (const struct clk_hw *[]) {
3302 &g12a_cts_enci_sel.hw
3305 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3309 static struct clk_regmap g12a_cts_encp = {
3310 .data = &(struct clk_regmap_gate_data){
3311 .offset = HHI_VID_CLK_CNTL2,
3314 .hw.init = &(struct clk_init_data) {
3316 .ops = &clk_regmap_gate_ops,
3317 .parent_hws = (const struct clk_hw *[]) {
3318 &g12a_cts_encp_sel.hw
3321 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3325 static struct clk_regmap g12a_cts_vdac = {
3326 .data = &(struct clk_regmap_gate_data){
3327 .offset = HHI_VID_CLK_CNTL2,
3330 .hw.init = &(struct clk_init_data) {
3332 .ops = &clk_regmap_gate_ops,
3333 .parent_hws = (const struct clk_hw *[]) {
3334 &g12a_cts_vdac_sel.hw
3337 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3341 static struct clk_regmap g12a_hdmi_tx = {
3342 .data = &(struct clk_regmap_gate_data){
3343 .offset = HHI_VID_CLK_CNTL2,
3346 .hw.init = &(struct clk_init_data) {
3348 .ops = &clk_regmap_gate_ops,
3349 .parent_hws = (const struct clk_hw *[]) {
3350 &g12a_hdmi_tx_sel.hw
3353 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3359 static const struct clk_parent_data g12a_hdmi_parent_data[] = {
3360 { .fw_name = "xtal", },
3361 { .hw = &g12a_fclk_div4.hw },
3362 { .hw = &g12a_fclk_div3.hw },
3363 { .hw = &g12a_fclk_div5.hw },
3366 static struct clk_regmap g12a_hdmi_sel = {
3367 .data = &(struct clk_regmap_mux_data){
3368 .offset = HHI_HDMI_CLK_CNTL,
3371 .flags = CLK_MUX_ROUND_CLOSEST,
3373 .hw.init = &(struct clk_init_data){
3375 .ops = &clk_regmap_mux_ops,
3376 .parent_data = g12a_hdmi_parent_data,
3377 .num_parents = ARRAY_SIZE(g12a_hdmi_parent_data),
3378 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3382 static struct clk_regmap g12a_hdmi_div = {
3383 .data = &(struct clk_regmap_div_data){
3384 .offset = HHI_HDMI_CLK_CNTL,
3388 .hw.init = &(struct clk_init_data){
3390 .ops = &clk_regmap_divider_ops,
3391 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
3393 .flags = CLK_GET_RATE_NOCACHE,
3397 static struct clk_regmap g12a_hdmi = {
3398 .data = &(struct clk_regmap_gate_data){
3399 .offset = HHI_HDMI_CLK_CNTL,
3402 .hw.init = &(struct clk_init_data) {
3404 .ops = &clk_regmap_gate_ops,
3405 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
3407 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3412 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
3413 * muxed by a glitch-free switch.
3415 static const struct clk_parent_data g12a_mali_0_1_parent_data[] = {
3416 { .fw_name = "xtal", },
3417 { .hw = &g12a_gp0_pll.hw },
3418 { .hw = &g12a_hifi_pll.hw },
3419 { .hw = &g12a_fclk_div2p5.hw },
3420 { .hw = &g12a_fclk_div3.hw },
3421 { .hw = &g12a_fclk_div4.hw },
3422 { .hw = &g12a_fclk_div5.hw },
3423 { .hw = &g12a_fclk_div7.hw },
3426 static struct clk_regmap g12a_mali_0_sel = {
3427 .data = &(struct clk_regmap_mux_data){
3428 .offset = HHI_MALI_CLK_CNTL,
3432 .hw.init = &(struct clk_init_data){
3433 .name = "mali_0_sel",
3434 .ops = &clk_regmap_mux_ops,
3435 .parent_data = g12a_mali_0_1_parent_data,
3437 .flags = CLK_SET_RATE_NO_REPARENT,
3441 static struct clk_regmap g12a_mali_0_div = {
3442 .data = &(struct clk_regmap_div_data){
3443 .offset = HHI_MALI_CLK_CNTL,
3447 .hw.init = &(struct clk_init_data){
3448 .name = "mali_0_div",
3449 .ops = &clk_regmap_divider_ops,
3450 .parent_hws = (const struct clk_hw *[]) {
3454 .flags = CLK_SET_RATE_NO_REPARENT,
3458 static struct clk_regmap g12a_mali_0 = {
3459 .data = &(struct clk_regmap_gate_data){
3460 .offset = HHI_MALI_CLK_CNTL,
3463 .hw.init = &(struct clk_init_data){
3465 .ops = &clk_regmap_gate_ops,
3466 .parent_hws = (const struct clk_hw *[]) {
3470 .flags = CLK_SET_RATE_PARENT,
3474 static struct clk_regmap g12a_mali_1_sel = {
3475 .data = &(struct clk_regmap_mux_data){
3476 .offset = HHI_MALI_CLK_CNTL,
3480 .hw.init = &(struct clk_init_data){
3481 .name = "mali_1_sel",
3482 .ops = &clk_regmap_mux_ops,
3483 .parent_data = g12a_mali_0_1_parent_data,
3485 .flags = CLK_SET_RATE_NO_REPARENT,
3489 static struct clk_regmap g12a_mali_1_div = {
3490 .data = &(struct clk_regmap_div_data){
3491 .offset = HHI_MALI_CLK_CNTL,
3495 .hw.init = &(struct clk_init_data){
3496 .name = "mali_1_div",
3497 .ops = &clk_regmap_divider_ops,
3498 .parent_hws = (const struct clk_hw *[]) {
3502 .flags = CLK_SET_RATE_NO_REPARENT,
3506 static struct clk_regmap g12a_mali_1 = {
3507 .data = &(struct clk_regmap_gate_data){
3508 .offset = HHI_MALI_CLK_CNTL,
3511 .hw.init = &(struct clk_init_data){
3513 .ops = &clk_regmap_gate_ops,
3514 .parent_hws = (const struct clk_hw *[]) {
3518 .flags = CLK_SET_RATE_PARENT,
3522 static const struct clk_hw *g12a_mali_parent_hws[] = {
3527 static struct clk_regmap g12a_mali = {
3528 .data = &(struct clk_regmap_mux_data){
3529 .offset = HHI_MALI_CLK_CNTL,
3533 .hw.init = &(struct clk_init_data){
3535 .ops = &clk_regmap_mux_ops,
3536 .parent_hws = g12a_mali_parent_hws,
3538 .flags = CLK_SET_RATE_NO_REPARENT,
3542 static struct clk_regmap g12a_ts_div = {
3543 .data = &(struct clk_regmap_div_data){
3544 .offset = HHI_TS_CLK_CNTL,
3548 .hw.init = &(struct clk_init_data){
3550 .ops = &clk_regmap_divider_ro_ops,
3551 .parent_data = &(const struct clk_parent_data) {
3558 static struct clk_regmap g12a_ts = {
3559 .data = &(struct clk_regmap_gate_data){
3560 .offset = HHI_TS_CLK_CNTL,
3563 .hw.init = &(struct clk_init_data){
3565 .ops = &clk_regmap_gate_ops,
3566 .parent_hws = (const struct clk_hw *[]) {
3573 #define MESON_GATE(_name, _reg, _bit) \
3574 MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
3576 #define MESON_GATE_RO(_name, _reg, _bit) \
3577 MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
3579 /* Everything Else (EE) domain gates */
3580 static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0);
3581 static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1);
3582 static MESON_GATE(g12a_audio_locker, HHI_GCLK_MPEG0, 2);
3583 static MESON_GATE(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
3584 static MESON_GATE(g12a_eth_phy, HHI_GCLK_MPEG0, 4);
3585 static MESON_GATE(g12a_isa, HHI_GCLK_MPEG0, 5);
3586 static MESON_GATE(g12a_pl301, HHI_GCLK_MPEG0, 6);
3587 static MESON_GATE(g12a_periphs, HHI_GCLK_MPEG0, 7);
3588 static MESON_GATE(g12a_spicc_0, HHI_GCLK_MPEG0, 8);
3589 static MESON_GATE(g12a_i2c, HHI_GCLK_MPEG0, 9);
3590 static MESON_GATE(g12a_sana, HHI_GCLK_MPEG0, 10);
3591 static MESON_GATE(g12a_sd, HHI_GCLK_MPEG0, 11);
3592 static MESON_GATE(g12a_rng0, HHI_GCLK_MPEG0, 12);
3593 static MESON_GATE(g12a_uart0, HHI_GCLK_MPEG0, 13);
3594 static MESON_GATE(g12a_spicc_1, HHI_GCLK_MPEG0, 14);
3595 static MESON_GATE(g12a_hiu_reg, HHI_GCLK_MPEG0, 19);
3596 static MESON_GATE(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20);
3597 static MESON_GATE(g12a_assist_misc, HHI_GCLK_MPEG0, 23);
3598 static MESON_GATE(g12a_emmc_a, HHI_GCLK_MPEG0, 4);
3599 static MESON_GATE(g12a_emmc_b, HHI_GCLK_MPEG0, 25);
3600 static MESON_GATE(g12a_emmc_c, HHI_GCLK_MPEG0, 26);
3601 static MESON_GATE(g12a_audio_codec, HHI_GCLK_MPEG0, 28);
3603 static MESON_GATE(g12a_audio, HHI_GCLK_MPEG1, 0);
3604 static MESON_GATE(g12a_eth_core, HHI_GCLK_MPEG1, 3);
3605 static MESON_GATE(g12a_demux, HHI_GCLK_MPEG1, 4);
3606 static MESON_GATE(g12a_audio_ififo, HHI_GCLK_MPEG1, 11);
3607 static MESON_GATE(g12a_adc, HHI_GCLK_MPEG1, 13);
3608 static MESON_GATE(g12a_uart1, HHI_GCLK_MPEG1, 16);
3609 static MESON_GATE(g12a_g2d, HHI_GCLK_MPEG1, 20);
3610 static MESON_GATE(g12a_reset, HHI_GCLK_MPEG1, 23);
3611 static MESON_GATE(g12a_pcie_comb, HHI_GCLK_MPEG1, 24);
3612 static MESON_GATE(g12a_parser, HHI_GCLK_MPEG1, 25);
3613 static MESON_GATE(g12a_usb_general, HHI_GCLK_MPEG1, 26);
3614 static MESON_GATE(g12a_pcie_phy, HHI_GCLK_MPEG1, 27);
3615 static MESON_GATE(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29);
3617 static MESON_GATE(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1);
3618 static MESON_GATE(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
3619 static MESON_GATE(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3);
3620 static MESON_GATE(g12a_htx_pclk, HHI_GCLK_MPEG2, 4);
3621 static MESON_GATE(g12a_bt656, HHI_GCLK_MPEG2, 6);
3622 static MESON_GATE(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
3623 static MESON_GATE(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11);
3624 static MESON_GATE(g12a_uart2, HHI_GCLK_MPEG2, 15);
3625 static MESON_GATE(g12a_vpu_intr, HHI_GCLK_MPEG2, 25);
3626 static MESON_GATE(g12a_gic, HHI_GCLK_MPEG2, 30);
3628 static MESON_GATE(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1);
3629 static MESON_GATE(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2);
3630 static MESON_GATE(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3);
3631 static MESON_GATE(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4);
3632 static MESON_GATE(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5);
3633 static MESON_GATE(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6);
3634 static MESON_GATE(g12a_vclk2_other, HHI_GCLK_OTHER, 7);
3635 static MESON_GATE(g12a_vclk2_enci, HHI_GCLK_OTHER, 8);
3636 static MESON_GATE(g12a_vclk2_encp, HHI_GCLK_OTHER, 9);
3637 static MESON_GATE(g12a_dac_clk, HHI_GCLK_OTHER, 10);
3638 static MESON_GATE(g12a_aoclk_gate, HHI_GCLK_OTHER, 14);
3639 static MESON_GATE(g12a_iec958_gate, HHI_GCLK_OTHER, 16);
3640 static MESON_GATE(g12a_enc480p, HHI_GCLK_OTHER, 20);
3641 static MESON_GATE(g12a_rng1, HHI_GCLK_OTHER, 21);
3642 static MESON_GATE(g12a_vclk2_enct, HHI_GCLK_OTHER, 22);
3643 static MESON_GATE(g12a_vclk2_encl, HHI_GCLK_OTHER, 23);
3644 static MESON_GATE(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24);
3645 static MESON_GATE(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25);
3646 static MESON_GATE(g12a_vclk2_other1, HHI_GCLK_OTHER, 26);
3648 static MESON_GATE_RO(g12a_dma, HHI_GCLK_OTHER2, 0);
3649 static MESON_GATE_RO(g12a_efuse, HHI_GCLK_OTHER2, 1);
3650 static MESON_GATE_RO(g12a_rom_boot, HHI_GCLK_OTHER2, 2);
3651 static MESON_GATE_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3);
3652 static MESON_GATE_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4);
3654 /* Array of all clocks provided by this provider */
3655 static struct clk_hw_onecell_data g12a_hw_onecell_data = {
3657 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
3658 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
3659 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
3660 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
3661 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
3662 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
3663 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
3664 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
3665 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
3666 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
3667 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
3668 [CLKID_CLK81] = &g12a_clk81.hw,
3669 [CLKID_MPLL0] = &g12a_mpll0.hw,
3670 [CLKID_MPLL1] = &g12a_mpll1.hw,
3671 [CLKID_MPLL2] = &g12a_mpll2.hw,
3672 [CLKID_MPLL3] = &g12a_mpll3.hw,
3673 [CLKID_DDR] = &g12a_ddr.hw,
3674 [CLKID_DOS] = &g12a_dos.hw,
3675 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
3676 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
3677 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
3678 [CLKID_ISA] = &g12a_isa.hw,
3679 [CLKID_PL301] = &g12a_pl301.hw,
3680 [CLKID_PERIPHS] = &g12a_periphs.hw,
3681 [CLKID_SPICC0] = &g12a_spicc_0.hw,
3682 [CLKID_I2C] = &g12a_i2c.hw,
3683 [CLKID_SANA] = &g12a_sana.hw,
3684 [CLKID_SD] = &g12a_sd.hw,
3685 [CLKID_RNG0] = &g12a_rng0.hw,
3686 [CLKID_UART0] = &g12a_uart0.hw,
3687 [CLKID_SPICC1] = &g12a_spicc_1.hw,
3688 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
3689 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
3690 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
3691 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
3692 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
3693 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
3694 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
3695 [CLKID_AUDIO] = &g12a_audio.hw,
3696 [CLKID_ETH] = &g12a_eth_core.hw,
3697 [CLKID_DEMUX] = &g12a_demux.hw,
3698 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
3699 [CLKID_ADC] = &g12a_adc.hw,
3700 [CLKID_UART1] = &g12a_uart1.hw,
3701 [CLKID_G2D] = &g12a_g2d.hw,
3702 [CLKID_RESET] = &g12a_reset.hw,
3703 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
3704 [CLKID_PARSER] = &g12a_parser.hw,
3705 [CLKID_USB] = &g12a_usb_general.hw,
3706 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
3707 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
3708 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
3709 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
3710 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
3711 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
3712 [CLKID_BT656] = &g12a_bt656.hw,
3713 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
3714 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
3715 [CLKID_UART2] = &g12a_uart2.hw,
3716 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
3717 [CLKID_GIC] = &g12a_gic.hw,
3718 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
3719 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
3720 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
3721 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
3722 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
3723 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
3724 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
3725 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
3726 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
3727 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
3728 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
3729 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
3730 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
3731 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
3732 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
3733 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
3734 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
3735 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
3736 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
3737 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
3738 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
3739 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
3740 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
3741 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
3742 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
3743 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
3744 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
3745 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
3746 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
3747 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
3748 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
3749 [CLKID_IEC958] = &g12a_iec958_gate.hw,
3750 [CLKID_ENC480P] = &g12a_enc480p.hw,
3751 [CLKID_RNG1] = &g12a_rng1.hw,
3752 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
3753 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
3754 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
3755 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
3756 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
3757 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
3758 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
3759 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
3760 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
3761 [CLKID_DMA] = &g12a_dma.hw,
3762 [CLKID_EFUSE] = &g12a_efuse.hw,
3763 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
3764 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
3765 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
3766 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
3767 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
3768 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
3769 [CLKID_VPU_0] = &g12a_vpu_0.hw,
3770 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
3771 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
3772 [CLKID_VPU_1] = &g12a_vpu_1.hw,
3773 [CLKID_VPU] = &g12a_vpu.hw,
3774 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
3775 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
3776 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
3777 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
3778 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
3779 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
3780 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
3781 [CLKID_VAPB] = &g12a_vapb.hw,
3782 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
3783 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
3784 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
3785 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
3786 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
3787 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
3788 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
3789 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
3790 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
3791 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
3792 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
3793 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
3794 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
3795 [CLKID_VCLK] = &g12a_vclk.hw,
3796 [CLKID_VCLK2] = &g12a_vclk2.hw,
3797 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
3798 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
3799 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
3800 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
3801 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
3802 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
3803 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
3804 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
3805 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
3806 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
3807 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
3808 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
3809 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
3810 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
3811 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
3812 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
3813 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
3814 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
3815 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
3816 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
3817 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
3818 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
3819 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
3820 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
3821 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
3822 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
3823 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
3824 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
3825 [CLKID_HDMI] = &g12a_hdmi.hw,
3826 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
3827 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
3828 [CLKID_MALI_0] = &g12a_mali_0.hw,
3829 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
3830 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
3831 [CLKID_MALI_1] = &g12a_mali_1.hw,
3832 [CLKID_MALI] = &g12a_mali.hw,
3833 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
3834 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
3835 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
3836 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
3837 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
3838 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
3839 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
3840 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
3841 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
3842 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
3843 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
3844 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
3845 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
3846 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
3847 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
3848 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
3849 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
3850 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
3851 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
3852 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
3853 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
3854 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
3855 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
3856 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
3857 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
3858 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
3859 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
3860 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
3861 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
3862 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
3863 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
3864 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
3865 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
3866 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
3867 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
3868 [CLKID_TS_DIV] = &g12a_ts_div.hw,
3869 [CLKID_TS] = &g12a_ts.hw,
3875 static struct clk_hw_onecell_data g12b_hw_onecell_data = {
3877 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
3878 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
3879 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
3880 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
3881 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
3882 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
3883 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
3884 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
3885 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
3886 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
3887 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
3888 [CLKID_CLK81] = &g12a_clk81.hw,
3889 [CLKID_MPLL0] = &g12a_mpll0.hw,
3890 [CLKID_MPLL1] = &g12a_mpll1.hw,
3891 [CLKID_MPLL2] = &g12a_mpll2.hw,
3892 [CLKID_MPLL3] = &g12a_mpll3.hw,
3893 [CLKID_DDR] = &g12a_ddr.hw,
3894 [CLKID_DOS] = &g12a_dos.hw,
3895 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
3896 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
3897 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
3898 [CLKID_ISA] = &g12a_isa.hw,
3899 [CLKID_PL301] = &g12a_pl301.hw,
3900 [CLKID_PERIPHS] = &g12a_periphs.hw,
3901 [CLKID_SPICC0] = &g12a_spicc_0.hw,
3902 [CLKID_I2C] = &g12a_i2c.hw,
3903 [CLKID_SANA] = &g12a_sana.hw,
3904 [CLKID_SD] = &g12a_sd.hw,
3905 [CLKID_RNG0] = &g12a_rng0.hw,
3906 [CLKID_UART0] = &g12a_uart0.hw,
3907 [CLKID_SPICC1] = &g12a_spicc_1.hw,
3908 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
3909 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
3910 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
3911 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
3912 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
3913 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
3914 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
3915 [CLKID_AUDIO] = &g12a_audio.hw,
3916 [CLKID_ETH] = &g12a_eth_core.hw,
3917 [CLKID_DEMUX] = &g12a_demux.hw,
3918 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
3919 [CLKID_ADC] = &g12a_adc.hw,
3920 [CLKID_UART1] = &g12a_uart1.hw,
3921 [CLKID_G2D] = &g12a_g2d.hw,
3922 [CLKID_RESET] = &g12a_reset.hw,
3923 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
3924 [CLKID_PARSER] = &g12a_parser.hw,
3925 [CLKID_USB] = &g12a_usb_general.hw,
3926 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
3927 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
3928 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
3929 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
3930 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
3931 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
3932 [CLKID_BT656] = &g12a_bt656.hw,
3933 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
3934 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
3935 [CLKID_UART2] = &g12a_uart2.hw,
3936 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
3937 [CLKID_GIC] = &g12a_gic.hw,
3938 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
3939 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
3940 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
3941 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
3942 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
3943 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
3944 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
3945 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
3946 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
3947 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
3948 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
3949 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
3950 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
3951 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
3952 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
3953 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
3954 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
3955 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
3956 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
3957 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
3958 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
3959 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
3960 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
3961 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
3962 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
3963 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
3964 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
3965 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
3966 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
3967 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
3968 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
3969 [CLKID_IEC958] = &g12a_iec958_gate.hw,
3970 [CLKID_ENC480P] = &g12a_enc480p.hw,
3971 [CLKID_RNG1] = &g12a_rng1.hw,
3972 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
3973 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
3974 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
3975 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
3976 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
3977 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
3978 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
3979 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
3980 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
3981 [CLKID_DMA] = &g12a_dma.hw,
3982 [CLKID_EFUSE] = &g12a_efuse.hw,
3983 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
3984 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
3985 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
3986 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
3987 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
3988 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
3989 [CLKID_VPU_0] = &g12a_vpu_0.hw,
3990 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
3991 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
3992 [CLKID_VPU_1] = &g12a_vpu_1.hw,
3993 [CLKID_VPU] = &g12a_vpu.hw,
3994 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
3995 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
3996 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
3997 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
3998 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
3999 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4000 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4001 [CLKID_VAPB] = &g12a_vapb.hw,
4002 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4003 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4004 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4005 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4006 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4007 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4008 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4009 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4010 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4011 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4012 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4013 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4014 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4015 [CLKID_VCLK] = &g12a_vclk.hw,
4016 [CLKID_VCLK2] = &g12a_vclk2.hw,
4017 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4018 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4019 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4020 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4021 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4022 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4023 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4024 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4025 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4026 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4027 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4028 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4029 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4030 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4031 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4032 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4033 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4034 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4035 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4036 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4037 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4038 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4039 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4040 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4041 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4042 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4043 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4044 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4045 [CLKID_HDMI] = &g12a_hdmi.hw,
4046 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4047 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4048 [CLKID_MALI_0] = &g12a_mali_0.hw,
4049 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4050 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4051 [CLKID_MALI_1] = &g12a_mali_1.hw,
4052 [CLKID_MALI] = &g12a_mali.hw,
4053 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4054 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4055 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4056 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4057 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4058 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4059 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4060 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4061 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4062 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4063 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4064 [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
4065 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4066 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4067 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4068 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4069 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4070 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4071 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4072 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4073 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4074 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4075 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4076 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4077 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4078 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4079 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4080 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4081 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4082 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4083 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4084 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4085 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4086 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4087 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4088 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4089 [CLKID_TS] = &g12a_ts.hw,
4090 [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
4091 [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
4092 [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
4093 [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
4094 [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,
4095 [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,
4096 [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,
4097 [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,
4098 [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,
4099 [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,
4100 [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
4101 [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
4102 [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
4103 [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
4104 [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
4105 [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
4106 [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
4107 [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
4108 [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
4109 [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
4110 [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
4111 [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
4112 [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
4113 [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
4114 [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
4115 [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
4116 [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
4117 [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
4118 [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
4124 /* Convenience table to populate regmap in .probe */
4125 static struct clk_regmap *const g12a_clk_regmaps[] = {
4130 &g12a_mipi_dsi_host,
4171 &g12a_sd_emmc_a_clk0,
4172 &g12a_sd_emmc_b_clk0,
4173 &g12a_sd_emmc_c_clk0,
4175 &g12a_sd_emmc_a_clk0_div,
4176 &g12a_sd_emmc_b_clk0_div,
4177 &g12a_sd_emmc_c_clk0_div,
4179 &g12a_sd_emmc_a_clk0_sel,
4180 &g12a_sd_emmc_b_clk0_sel,
4181 &g12a_sd_emmc_c_clk0_sel,
4210 &g12a_vclk2_venclmmc,
4213 &g12a_fixed_pll_dco,
4262 &g12a_vclk_div12_en,
4264 &g12a_vclk2_div2_en,
4265 &g12a_vclk2_div4_en,
4266 &g12a_vclk2_div6_en,
4267 &g12a_vclk2_div12_en,
4287 &g12a_sys_pll_div16_en,
4288 &g12a_cpu_clk_premux0,
4289 &g12a_cpu_clk_mux0_div,
4290 &g12a_cpu_clk_postmux0,
4291 &g12a_cpu_clk_premux1,
4292 &g12a_cpu_clk_mux1_div,
4293 &g12a_cpu_clk_postmux1,
4296 &g12a_cpu_clk_div16_en,
4297 &g12a_cpu_clk_apb_div,
4299 &g12a_cpu_clk_atb_div,
4301 &g12a_cpu_clk_axi_div,
4303 &g12a_cpu_clk_trace_div,
4304 &g12a_cpu_clk_trace,
4310 &g12a_vdec_hevc_sel,
4311 &g12a_vdec_hevc_div,
4313 &g12a_vdec_hevcf_sel,
4314 &g12a_vdec_hevcf_div,
4321 &g12b_sys1_pll_div16_en,
4322 &g12b_cpub_clk_premux0,
4323 &g12b_cpub_clk_mux0_div,
4324 &g12b_cpub_clk_postmux0,
4325 &g12b_cpub_clk_premux1,
4326 &g12b_cpub_clk_mux1_div,
4327 &g12b_cpub_clk_postmux1,
4330 &g12b_cpub_clk_div16_en,
4331 &g12b_cpub_clk_apb_sel,
4333 &g12b_cpub_clk_atb_sel,
4335 &g12b_cpub_clk_axi_sel,
4337 &g12b_cpub_clk_trace_sel,
4338 &g12b_cpub_clk_trace,
4341 static const struct reg_sequence g12a_init_regs[] = {
4342 { .reg = HHI_MPLL_CNTL0, .def = 0x00000543 },
4345 static int meson_g12a_dvfs_setup_common(struct platform_device *pdev,
4346 struct clk_hw **hws)
4348 const char *notifier_clk_name;
4349 struct clk *notifier_clk;
4350 struct clk_hw *xtal;
4353 xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
4355 /* Setup clock notifier for cpu_clk_postmux0 */
4356 g12a_cpu_clk_postmux0_nb_data.xtal = xtal;
4357 notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_postmux0.hw);
4358 notifier_clk = __clk_lookup(notifier_clk_name);
4359 ret = clk_notifier_register(notifier_clk,
4360 &g12a_cpu_clk_postmux0_nb_data.nb);
4362 dev_err(&pdev->dev, "failed to register the cpu_clk_postmux0 notifier\n");
4366 /* Setup clock notifier for cpu_clk_dyn mux */
4367 notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_dyn.hw);
4368 notifier_clk = __clk_lookup(notifier_clk_name);
4369 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
4371 dev_err(&pdev->dev, "failed to register the cpu_clk_dyn notifier\n");
4378 static int meson_g12b_dvfs_setup(struct platform_device *pdev)
4380 struct clk_hw **hws = g12b_hw_onecell_data.hws;
4381 const char *notifier_clk_name;
4382 struct clk *notifier_clk;
4383 struct clk_hw *xtal;
4386 ret = meson_g12a_dvfs_setup_common(pdev, hws);
4390 xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
4392 /* Setup clock notifier for cpu_clk mux */
4393 notifier_clk_name = clk_hw_get_name(&g12b_cpu_clk.hw);
4394 notifier_clk = __clk_lookup(notifier_clk_name);
4395 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
4397 dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n");
4401 /* Setup clock notifier for sys1_pll */
4402 notifier_clk_name = clk_hw_get_name(&g12b_sys1_pll.hw);
4403 notifier_clk = __clk_lookup(notifier_clk_name);
4404 ret = clk_notifier_register(notifier_clk,
4405 &g12b_cpu_clk_sys1_pll_nb_data.nb);
4407 dev_err(&pdev->dev, "failed to register the sys1_pll notifier\n");
4411 /* Add notifiers for the second CPU cluster */
4413 /* Setup clock notifier for cpub_clk_postmux0 */
4414 g12b_cpub_clk_postmux0_nb_data.xtal = xtal;
4415 notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_postmux0.hw);
4416 notifier_clk = __clk_lookup(notifier_clk_name);
4417 ret = clk_notifier_register(notifier_clk,
4418 &g12b_cpub_clk_postmux0_nb_data.nb);
4420 dev_err(&pdev->dev, "failed to register the cpub_clk_postmux0 notifier\n");
4424 /* Setup clock notifier for cpub_clk_dyn mux */
4425 notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_dyn.hw);
4426 notifier_clk = __clk_lookup(notifier_clk_name);
4427 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
4429 dev_err(&pdev->dev, "failed to register the cpub_clk_dyn notifier\n");
4433 /* Setup clock notifier for cpub_clk mux */
4434 notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk.hw);
4435 notifier_clk = __clk_lookup(notifier_clk_name);
4436 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
4438 dev_err(&pdev->dev, "failed to register the cpub_clk notifier\n");
4442 /* Setup clock notifier for sys_pll */
4443 notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw);
4444 notifier_clk = __clk_lookup(notifier_clk_name);
4445 ret = clk_notifier_register(notifier_clk,
4446 &g12b_cpub_clk_sys_pll_nb_data.nb);
4448 dev_err(&pdev->dev, "failed to register the sys_pll notifier\n");
4455 static int meson_g12a_dvfs_setup(struct platform_device *pdev)
4457 struct clk_hw **hws = g12a_hw_onecell_data.hws;
4458 const char *notifier_clk_name;
4459 struct clk *notifier_clk;
4462 ret = meson_g12a_dvfs_setup_common(pdev, hws);
4466 /* Setup clock notifier for cpu_clk mux */
4467 notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk.hw);
4468 notifier_clk = __clk_lookup(notifier_clk_name);
4469 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
4471 dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n");
4475 /* Setup clock notifier for sys_pll */
4476 notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw);
4477 notifier_clk = __clk_lookup(notifier_clk_name);
4478 ret = clk_notifier_register(notifier_clk, &g12a_sys_pll_nb_data.nb);
4480 dev_err(&pdev->dev, "failed to register the sys_pll notifier\n");
4487 struct meson_g12a_data {
4488 const struct meson_eeclkc_data eeclkc_data;
4489 int (*dvfs_setup)(struct platform_device *pdev);
4492 static int meson_g12a_probe(struct platform_device *pdev)
4494 const struct meson_eeclkc_data *eeclkc_data;
4495 const struct meson_g12a_data *g12a_data;
4498 eeclkc_data = of_device_get_match_data(&pdev->dev);
4502 ret = meson_eeclkc_probe(pdev);
4506 g12a_data = container_of(eeclkc_data, struct meson_g12a_data,
4509 if (g12a_data->dvfs_setup)
4510 return g12a_data->dvfs_setup(pdev);
4515 static const struct meson_g12a_data g12a_clkc_data = {
4517 .regmap_clks = g12a_clk_regmaps,
4518 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
4519 .hw_onecell_data = &g12a_hw_onecell_data,
4520 .init_regs = g12a_init_regs,
4521 .init_count = ARRAY_SIZE(g12a_init_regs),
4523 .dvfs_setup = meson_g12a_dvfs_setup,
4526 static const struct meson_g12a_data g12b_clkc_data = {
4528 .regmap_clks = g12a_clk_regmaps,
4529 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
4530 .hw_onecell_data = &g12b_hw_onecell_data,
4532 .dvfs_setup = meson_g12b_dvfs_setup,
4535 static const struct of_device_id clkc_match_table[] = {
4537 .compatible = "amlogic,g12a-clkc",
4538 .data = &g12a_clkc_data.eeclkc_data
4541 .compatible = "amlogic,g12b-clkc",
4542 .data = &g12b_clkc_data.eeclkc_data
4547 static struct platform_driver g12a_driver = {
4548 .probe = meson_g12a_probe,
4550 .name = "g12a-clkc",
4551 .of_match_table = clkc_match_table,
4555 builtin_platform_driver(g12a_driver);