1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
6 * Copyright (c) 2018 Baylibre, SAS.
7 * Author: Jerome Brunet <jbrunet@baylibre.com>
11 * In the most basic form, a Meson PLL is composed as follows:
14 * +--------------------------------+
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
24 * +--------------------------------+
26 * out = in * (m + frac / frac_max) / n
29 #include <linux/clk-provider.h>
30 #include <linux/delay.h>
31 #include <linux/err.h>
33 #include <linux/math64.h>
34 #include <linux/module.h>
36 #include "clk-regmap.h"
39 static inline struct meson_clk_pll_data *
40 meson_clk_pll_data(struct clk_regmap *clk)
42 return (struct meson_clk_pll_data *)clk->data;
45 static int __pll_round_closest_mult(struct meson_clk_pll_data *pll)
47 if ((pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) &&
48 !MESON_PARM_APPLICABLE(&pll->frac))
54 static unsigned long __pll_params_to_rate(unsigned long parent_rate,
55 unsigned int m, unsigned int n,
57 struct meson_clk_pll_data *pll)
59 u64 rate = (u64)parent_rate * m;
61 if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
62 u64 frac_rate = (u64)parent_rate * frac;
64 rate += DIV_ROUND_UP_ULL(frac_rate,
65 (1 << pll->frac.width));
68 return DIV_ROUND_UP_ULL(rate, n);
71 static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
72 unsigned long parent_rate)
74 struct clk_regmap *clk = to_clk_regmap(hw);
75 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
76 unsigned int m, n, frac;
78 n = meson_parm_read(clk->map, &pll->n);
81 * On some HW, N is set to zero on init. This value is invalid as
82 * it would result in a division by zero. The rate can't be
83 * calculated in this case
88 m = meson_parm_read(clk->map, &pll->m);
90 frac = MESON_PARM_APPLICABLE(&pll->frac) ?
91 meson_parm_read(clk->map, &pll->frac) :
94 return __pll_params_to_rate(parent_rate, m, n, frac, pll);
97 static unsigned int __pll_params_with_frac(unsigned long rate,
98 unsigned long parent_rate,
101 struct meson_clk_pll_data *pll)
103 unsigned int frac_max = (1 << pll->frac.width);
104 u64 val = (u64)rate * n;
106 /* Bail out if we are already over the requested rate */
107 if (rate < parent_rate * m / n)
110 if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST)
111 val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate);
113 val = div_u64(val * frac_max, parent_rate);
117 return min((unsigned int)val, (frac_max - 1));
120 static bool meson_clk_pll_is_better(unsigned long rate,
123 struct meson_clk_pll_data *pll)
125 if (__pll_round_closest_mult(pll)) {
127 if (abs(now - rate) < abs(best - rate))
131 if (now <= rate && best < now)
138 static int meson_clk_get_pll_table_index(unsigned int index,
141 struct meson_clk_pll_data *pll)
143 if (!pll->table[index].n)
146 *m = pll->table[index].m;
147 *n = pll->table[index].n;
152 static unsigned int meson_clk_get_pll_range_m(unsigned long rate,
153 unsigned long parent_rate,
155 struct meson_clk_pll_data *pll)
157 u64 val = (u64)rate * n;
159 if (__pll_round_closest_mult(pll))
160 return DIV_ROUND_CLOSEST_ULL(val, parent_rate);
162 return div_u64(val, parent_rate);
165 static int meson_clk_get_pll_range_index(unsigned long rate,
166 unsigned long parent_rate,
170 struct meson_clk_pll_data *pll)
174 /* Check the predivider range */
175 if (*n >= (1 << pll->n.width))
179 /* Get the boundaries out the way */
180 if (rate <= pll->range->min * parent_rate) {
181 *m = pll->range->min;
183 } else if (rate >= pll->range->max * parent_rate) {
184 *m = pll->range->max;
189 *m = meson_clk_get_pll_range_m(rate, parent_rate, *n, pll);
191 /* the pre-divider gives a multiplier too big - stop */
192 if (*m >= (1 << pll->m.width))
198 static int meson_clk_get_pll_get_index(unsigned long rate,
199 unsigned long parent_rate,
203 struct meson_clk_pll_data *pll)
206 return meson_clk_get_pll_range_index(rate, parent_rate,
209 return meson_clk_get_pll_table_index(index, m, n, pll);
214 static int meson_clk_get_pll_settings(unsigned long rate,
215 unsigned long parent_rate,
216 unsigned int *best_m,
217 unsigned int *best_n,
218 struct meson_clk_pll_data *pll)
220 unsigned long best = 0, now = 0;
221 unsigned int i, m, n;
224 for (i = 0, ret = 0; !ret; i++) {
225 ret = meson_clk_get_pll_get_index(rate, parent_rate,
230 now = __pll_params_to_rate(parent_rate, m, n, 0, pll);
231 if (meson_clk_pll_is_better(rate, best, now, pll)) {
241 return best ? 0 : -EINVAL;
244 static int meson_clk_pll_determine_rate(struct clk_hw *hw,
245 struct clk_rate_request *req)
247 struct clk_regmap *clk = to_clk_regmap(hw);
248 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
249 unsigned int m, n, frac;
253 ret = meson_clk_get_pll_settings(req->rate, req->best_parent_rate,
258 round = __pll_params_to_rate(req->best_parent_rate, m, n, 0, pll);
260 if (!MESON_PARM_APPLICABLE(&pll->frac) || req->rate == round) {
266 * The rate provided by the setting is not an exact match, let's
267 * try to improve the result using the fractional parameter
269 frac = __pll_params_with_frac(req->rate, req->best_parent_rate, m, n, pll);
270 req->rate = __pll_params_to_rate(req->best_parent_rate, m, n, frac, pll);
275 static int meson_clk_pll_wait_lock(struct clk_hw *hw)
277 struct clk_regmap *clk = to_clk_regmap(hw);
278 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
282 /* Is the clock locked now ? Time out after 100ms. */
283 if (meson_parm_read(clk->map, &pll->l))
292 static int meson_clk_pll_init(struct clk_hw *hw)
294 struct clk_regmap *clk = to_clk_regmap(hw);
295 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
297 if (pll->init_count) {
298 if (MESON_PARM_APPLICABLE(&pll->rst))
299 meson_parm_write(clk->map, &pll->rst, 1);
301 regmap_multi_reg_write(clk->map, pll->init_regs,
304 if (MESON_PARM_APPLICABLE(&pll->rst))
305 meson_parm_write(clk->map, &pll->rst, 0);
311 static int meson_clk_pll_is_enabled(struct clk_hw *hw)
313 struct clk_regmap *clk = to_clk_regmap(hw);
314 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
316 if (MESON_PARM_APPLICABLE(&pll->rst) &&
317 meson_parm_read(clk->map, &pll->rst))
320 if (!meson_parm_read(clk->map, &pll->en) ||
321 !meson_parm_read(clk->map, &pll->l))
327 static int meson_clk_pcie_pll_enable(struct clk_hw *hw)
332 meson_clk_pll_init(hw);
333 if (!meson_clk_pll_wait_lock(hw))
335 pr_info("Retry enabling PCIe PLL clock\n");
341 static int meson_clk_pll_enable(struct clk_hw *hw)
343 struct clk_regmap *clk = to_clk_regmap(hw);
344 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
346 /* do nothing if the PLL is already enabled */
347 if (clk_hw_is_enabled(hw))
350 /* Make sure the pll is in reset */
351 if (MESON_PARM_APPLICABLE(&pll->rst))
352 meson_parm_write(clk->map, &pll->rst, 1);
355 meson_parm_write(clk->map, &pll->en, 1);
357 /* Take the pll out reset */
358 if (MESON_PARM_APPLICABLE(&pll->rst))
359 meson_parm_write(clk->map, &pll->rst, 0);
362 * Compared with the previous SoCs, self-adaption current module
363 * is newly added for A1, keep the new power-on sequence to enable the
364 * PLL. The sequence is:
365 * 1. enable the pll, delay for 10us
366 * 2. enable the pll self-adaption current module, delay for 40us
367 * 3. enable the lock detect module
369 if (MESON_PARM_APPLICABLE(&pll->current_en)) {
370 usleep_range(10, 20);
371 meson_parm_write(clk->map, &pll->current_en, 1);
372 usleep_range(40, 50);
375 if (MESON_PARM_APPLICABLE(&pll->l_detect)) {
376 meson_parm_write(clk->map, &pll->l_detect, 1);
377 meson_parm_write(clk->map, &pll->l_detect, 0);
380 if (meson_clk_pll_wait_lock(hw))
386 static void meson_clk_pll_disable(struct clk_hw *hw)
388 struct clk_regmap *clk = to_clk_regmap(hw);
389 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
391 /* Put the pll is in reset */
392 if (MESON_PARM_APPLICABLE(&pll->rst))
393 meson_parm_write(clk->map, &pll->rst, 1);
395 /* Disable the pll */
396 meson_parm_write(clk->map, &pll->en, 0);
398 /* Disable PLL internal self-adaption current module */
399 if (MESON_PARM_APPLICABLE(&pll->current_en))
400 meson_parm_write(clk->map, &pll->current_en, 0);
403 static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
404 unsigned long parent_rate)
406 struct clk_regmap *clk = to_clk_regmap(hw);
407 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
408 unsigned int enabled, m, n, frac = 0;
409 unsigned long old_rate;
412 if (parent_rate == 0 || rate == 0)
415 old_rate = clk_hw_get_rate(hw);
417 ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll);
421 enabled = meson_parm_read(clk->map, &pll->en);
423 meson_clk_pll_disable(hw);
425 meson_parm_write(clk->map, &pll->n, n);
426 meson_parm_write(clk->map, &pll->m, m);
428 if (MESON_PARM_APPLICABLE(&pll->frac)) {
429 frac = __pll_params_with_frac(rate, parent_rate, m, n, pll);
430 meson_parm_write(clk->map, &pll->frac, frac);
433 /* If the pll is stopped, bail out now */
437 ret = meson_clk_pll_enable(hw);
439 pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
442 * FIXME: Do we really need/want this HACK ?
443 * It looks unsafe. what happens if the clock gets into a
444 * broken state and we can't lock back on the old_rate ? Looks
445 * like an infinite recursion is possible
447 meson_clk_pll_set_rate(hw, old_rate, parent_rate);
454 * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
455 * 100MHz reference clock for the PCIe Analog PHY, and thus requires
456 * a strict register sequence to enable the PLL.
457 * To simplify, re-use the _init() op to enable the PLL and keep
458 * the other ops except set_rate since the rate is fixed.
460 const struct clk_ops meson_clk_pcie_pll_ops = {
461 .recalc_rate = meson_clk_pll_recalc_rate,
462 .determine_rate = meson_clk_pll_determine_rate,
463 .is_enabled = meson_clk_pll_is_enabled,
464 .enable = meson_clk_pcie_pll_enable,
465 .disable = meson_clk_pll_disable
467 EXPORT_SYMBOL_GPL(meson_clk_pcie_pll_ops);
469 const struct clk_ops meson_clk_pll_ops = {
470 .init = meson_clk_pll_init,
471 .recalc_rate = meson_clk_pll_recalc_rate,
472 .determine_rate = meson_clk_pll_determine_rate,
473 .set_rate = meson_clk_pll_set_rate,
474 .is_enabled = meson_clk_pll_is_enabled,
475 .enable = meson_clk_pll_enable,
476 .disable = meson_clk_pll_disable
478 EXPORT_SYMBOL_GPL(meson_clk_pll_ops);
480 const struct clk_ops meson_clk_pll_ro_ops = {
481 .recalc_rate = meson_clk_pll_recalc_rate,
482 .is_enabled = meson_clk_pll_is_enabled,
484 EXPORT_SYMBOL_GPL(meson_clk_pll_ro_ops);
486 MODULE_DESCRIPTION("Amlogic PLL driver");
487 MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>");
488 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
489 MODULE_LICENSE("GPL v2");