1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
5 * Copyright (c) 2016 Baylibre SAS.
6 * Author: Michael Turquette <mturquette@baylibre.com>
8 * Copyright (c) 2017 Amlogic, inc.
9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
12 #include <linux/clk-provider.h>
13 #include <linux/init.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/module.h>
18 #include "clk-regmap.h"
22 #include "meson-eeclk.h"
24 static DEFINE_SPINLOCK(meson_clk_lock);
26 static struct clk_regmap axg_fixed_pll_dco = {
27 .data = &(struct meson_clk_pll_data){
29 .reg_off = HHI_MPLL_CNTL,
34 .reg_off = HHI_MPLL_CNTL,
39 .reg_off = HHI_MPLL_CNTL,
44 .reg_off = HHI_MPLL_CNTL2,
49 .reg_off = HHI_MPLL_CNTL,
54 .reg_off = HHI_MPLL_CNTL,
59 .hw.init = &(struct clk_init_data){
60 .name = "fixed_pll_dco",
61 .ops = &meson_clk_pll_ro_ops,
62 .parent_data = &(const struct clk_parent_data) {
69 static struct clk_regmap axg_fixed_pll = {
70 .data = &(struct clk_regmap_div_data){
71 .offset = HHI_MPLL_CNTL,
74 .flags = CLK_DIVIDER_POWER_OF_TWO,
76 .hw.init = &(struct clk_init_data){
78 .ops = &clk_regmap_divider_ro_ops,
79 .parent_hws = (const struct clk_hw *[]) {
84 * This clock won't ever change at runtime so
85 * CLK_SET_RATE_PARENT is not required
90 static struct clk_regmap axg_sys_pll_dco = {
91 .data = &(struct meson_clk_pll_data){
93 .reg_off = HHI_SYS_PLL_CNTL,
98 .reg_off = HHI_SYS_PLL_CNTL,
103 .reg_off = HHI_SYS_PLL_CNTL,
108 .reg_off = HHI_SYS_PLL_CNTL,
113 .reg_off = HHI_SYS_PLL_CNTL,
118 .hw.init = &(struct clk_init_data){
119 .name = "sys_pll_dco",
120 .ops = &meson_clk_pll_ro_ops,
121 .parent_data = &(const struct clk_parent_data) {
128 static struct clk_regmap axg_sys_pll = {
129 .data = &(struct clk_regmap_div_data){
130 .offset = HHI_SYS_PLL_CNTL,
133 .flags = CLK_DIVIDER_POWER_OF_TWO,
135 .hw.init = &(struct clk_init_data){
137 .ops = &clk_regmap_divider_ro_ops,
138 .parent_hws = (const struct clk_hw *[]) {
142 .flags = CLK_SET_RATE_PARENT,
146 static const struct pll_params_table axg_gp0_pll_params_table[] = {
179 static const struct reg_sequence axg_gp0_init_regs[] = {
180 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
181 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
182 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
183 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
184 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
187 static struct clk_regmap axg_gp0_pll_dco = {
188 .data = &(struct meson_clk_pll_data){
190 .reg_off = HHI_GP0_PLL_CNTL,
195 .reg_off = HHI_GP0_PLL_CNTL,
200 .reg_off = HHI_GP0_PLL_CNTL,
205 .reg_off = HHI_GP0_PLL_CNTL1,
210 .reg_off = HHI_GP0_PLL_CNTL,
215 .reg_off = HHI_GP0_PLL_CNTL,
219 .table = axg_gp0_pll_params_table,
220 .init_regs = axg_gp0_init_regs,
221 .init_count = ARRAY_SIZE(axg_gp0_init_regs),
223 .hw.init = &(struct clk_init_data){
224 .name = "gp0_pll_dco",
225 .ops = &meson_clk_pll_ops,
226 .parent_data = &(const struct clk_parent_data) {
233 static struct clk_regmap axg_gp0_pll = {
234 .data = &(struct clk_regmap_div_data){
235 .offset = HHI_GP0_PLL_CNTL,
238 .flags = CLK_DIVIDER_POWER_OF_TWO,
240 .hw.init = &(struct clk_init_data){
242 .ops = &clk_regmap_divider_ops,
243 .parent_hws = (const struct clk_hw *[]) {
247 .flags = CLK_SET_RATE_PARENT,
251 static const struct reg_sequence axg_hifi_init_regs[] = {
252 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 },
253 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be },
254 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 },
255 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d },
256 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 },
259 static struct clk_regmap axg_hifi_pll_dco = {
260 .data = &(struct meson_clk_pll_data){
262 .reg_off = HHI_HIFI_PLL_CNTL,
267 .reg_off = HHI_HIFI_PLL_CNTL,
272 .reg_off = HHI_HIFI_PLL_CNTL,
277 .reg_off = HHI_HIFI_PLL_CNTL5,
282 .reg_off = HHI_HIFI_PLL_CNTL,
287 .reg_off = HHI_HIFI_PLL_CNTL,
291 .table = axg_gp0_pll_params_table,
292 .init_regs = axg_hifi_init_regs,
293 .init_count = ARRAY_SIZE(axg_hifi_init_regs),
294 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
296 .hw.init = &(struct clk_init_data){
297 .name = "hifi_pll_dco",
298 .ops = &meson_clk_pll_ops,
299 .parent_data = &(const struct clk_parent_data) {
306 static struct clk_regmap axg_hifi_pll = {
307 .data = &(struct clk_regmap_div_data){
308 .offset = HHI_HIFI_PLL_CNTL,
311 .flags = CLK_DIVIDER_POWER_OF_TWO,
313 .hw.init = &(struct clk_init_data){
315 .ops = &clk_regmap_divider_ops,
316 .parent_hws = (const struct clk_hw *[]) {
320 .flags = CLK_SET_RATE_PARENT,
324 static struct clk_fixed_factor axg_fclk_div2_div = {
327 .hw.init = &(struct clk_init_data){
328 .name = "fclk_div2_div",
329 .ops = &clk_fixed_factor_ops,
330 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
335 static struct clk_regmap axg_fclk_div2 = {
336 .data = &(struct clk_regmap_gate_data){
337 .offset = HHI_MPLL_CNTL6,
340 .hw.init = &(struct clk_init_data){
342 .ops = &clk_regmap_gate_ops,
343 .parent_hws = (const struct clk_hw *[]) {
344 &axg_fclk_div2_div.hw
347 .flags = CLK_IS_CRITICAL,
351 static struct clk_fixed_factor axg_fclk_div3_div = {
354 .hw.init = &(struct clk_init_data){
355 .name = "fclk_div3_div",
356 .ops = &clk_fixed_factor_ops,
357 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
362 static struct clk_regmap axg_fclk_div3 = {
363 .data = &(struct clk_regmap_gate_data){
364 .offset = HHI_MPLL_CNTL6,
367 .hw.init = &(struct clk_init_data){
369 .ops = &clk_regmap_gate_ops,
370 .parent_hws = (const struct clk_hw *[]) {
371 &axg_fclk_div3_div.hw
376 * This clock, as fdiv2, is used by the SCPI FW and is required
377 * by the platform to operate correctly.
378 * Until the following condition are met, we need this clock to
379 * be marked as critical:
380 * a) The SCPI generic driver claims and enable all the clocks
382 * b) CCF has a clock hand-off mechanism to make the sure the
383 * clock stays on until the proper driver comes along
385 .flags = CLK_IS_CRITICAL,
389 static struct clk_fixed_factor axg_fclk_div4_div = {
392 .hw.init = &(struct clk_init_data){
393 .name = "fclk_div4_div",
394 .ops = &clk_fixed_factor_ops,
395 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
400 static struct clk_regmap axg_fclk_div4 = {
401 .data = &(struct clk_regmap_gate_data){
402 .offset = HHI_MPLL_CNTL6,
405 .hw.init = &(struct clk_init_data){
407 .ops = &clk_regmap_gate_ops,
408 .parent_hws = (const struct clk_hw *[]) {
409 &axg_fclk_div4_div.hw
415 static struct clk_fixed_factor axg_fclk_div5_div = {
418 .hw.init = &(struct clk_init_data){
419 .name = "fclk_div5_div",
420 .ops = &clk_fixed_factor_ops,
421 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
426 static struct clk_regmap axg_fclk_div5 = {
427 .data = &(struct clk_regmap_gate_data){
428 .offset = HHI_MPLL_CNTL6,
431 .hw.init = &(struct clk_init_data){
433 .ops = &clk_regmap_gate_ops,
434 .parent_hws = (const struct clk_hw *[]) {
435 &axg_fclk_div5_div.hw
441 static struct clk_fixed_factor axg_fclk_div7_div = {
444 .hw.init = &(struct clk_init_data){
445 .name = "fclk_div7_div",
446 .ops = &clk_fixed_factor_ops,
447 .parent_hws = (const struct clk_hw *[]) {
454 static struct clk_regmap axg_fclk_div7 = {
455 .data = &(struct clk_regmap_gate_data){
456 .offset = HHI_MPLL_CNTL6,
459 .hw.init = &(struct clk_init_data){
461 .ops = &clk_regmap_gate_ops,
462 .parent_hws = (const struct clk_hw *[]) {
463 &axg_fclk_div7_div.hw
469 static struct clk_regmap axg_mpll_prediv = {
470 .data = &(struct clk_regmap_div_data){
471 .offset = HHI_MPLL_CNTL5,
475 .hw.init = &(struct clk_init_data){
476 .name = "mpll_prediv",
477 .ops = &clk_regmap_divider_ro_ops,
478 .parent_hws = (const struct clk_hw *[]) {
485 static struct clk_regmap axg_mpll0_div = {
486 .data = &(struct meson_clk_mpll_data){
488 .reg_off = HHI_MPLL_CNTL7,
493 .reg_off = HHI_MPLL_CNTL7,
498 .reg_off = HHI_MPLL_CNTL7,
503 .reg_off = HHI_PLL_TOP_MISC,
507 .lock = &meson_clk_lock,
508 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
510 .hw.init = &(struct clk_init_data){
512 .ops = &meson_clk_mpll_ops,
513 .parent_hws = (const struct clk_hw *[]) {
520 static struct clk_regmap axg_mpll0 = {
521 .data = &(struct clk_regmap_gate_data){
522 .offset = HHI_MPLL_CNTL7,
525 .hw.init = &(struct clk_init_data){
527 .ops = &clk_regmap_gate_ops,
528 .parent_hws = (const struct clk_hw *[]) {
532 .flags = CLK_SET_RATE_PARENT,
536 static struct clk_regmap axg_mpll1_div = {
537 .data = &(struct meson_clk_mpll_data){
539 .reg_off = HHI_MPLL_CNTL8,
544 .reg_off = HHI_MPLL_CNTL8,
549 .reg_off = HHI_MPLL_CNTL8,
554 .reg_off = HHI_PLL_TOP_MISC,
558 .lock = &meson_clk_lock,
559 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
561 .hw.init = &(struct clk_init_data){
563 .ops = &meson_clk_mpll_ops,
564 .parent_hws = (const struct clk_hw *[]) {
571 static struct clk_regmap axg_mpll1 = {
572 .data = &(struct clk_regmap_gate_data){
573 .offset = HHI_MPLL_CNTL8,
576 .hw.init = &(struct clk_init_data){
578 .ops = &clk_regmap_gate_ops,
579 .parent_hws = (const struct clk_hw *[]) {
583 .flags = CLK_SET_RATE_PARENT,
587 static struct clk_regmap axg_mpll2_div = {
588 .data = &(struct meson_clk_mpll_data){
590 .reg_off = HHI_MPLL_CNTL9,
595 .reg_off = HHI_MPLL_CNTL9,
600 .reg_off = HHI_MPLL_CNTL9,
605 .reg_off = HHI_MPLL_CNTL,
610 .reg_off = HHI_PLL_TOP_MISC,
614 .lock = &meson_clk_lock,
615 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
617 .hw.init = &(struct clk_init_data){
619 .ops = &meson_clk_mpll_ops,
620 .parent_hws = (const struct clk_hw *[]) {
627 static struct clk_regmap axg_mpll2 = {
628 .data = &(struct clk_regmap_gate_data){
629 .offset = HHI_MPLL_CNTL9,
632 .hw.init = &(struct clk_init_data){
634 .ops = &clk_regmap_gate_ops,
635 .parent_hws = (const struct clk_hw *[]) {
639 .flags = CLK_SET_RATE_PARENT,
643 static struct clk_regmap axg_mpll3_div = {
644 .data = &(struct meson_clk_mpll_data){
646 .reg_off = HHI_MPLL3_CNTL0,
651 .reg_off = HHI_MPLL3_CNTL0,
656 .reg_off = HHI_MPLL3_CNTL0,
661 .reg_off = HHI_PLL_TOP_MISC,
665 .lock = &meson_clk_lock,
666 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
668 .hw.init = &(struct clk_init_data){
670 .ops = &meson_clk_mpll_ops,
671 .parent_hws = (const struct clk_hw *[]) {
678 static struct clk_regmap axg_mpll3 = {
679 .data = &(struct clk_regmap_gate_data){
680 .offset = HHI_MPLL3_CNTL0,
683 .hw.init = &(struct clk_init_data){
685 .ops = &clk_regmap_gate_ops,
686 .parent_hws = (const struct clk_hw *[]) {
690 .flags = CLK_SET_RATE_PARENT,
694 static const struct pll_params_table axg_pcie_pll_params_table[] = {
702 static const struct reg_sequence axg_pcie_init_regs[] = {
703 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa },
704 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be },
705 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e },
706 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d },
707 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 },
708 { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 },
709 { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 },
712 static struct clk_regmap axg_pcie_pll_dco = {
713 .data = &(struct meson_clk_pll_data){
715 .reg_off = HHI_PCIE_PLL_CNTL,
720 .reg_off = HHI_PCIE_PLL_CNTL,
725 .reg_off = HHI_PCIE_PLL_CNTL,
730 .reg_off = HHI_PCIE_PLL_CNTL1,
735 .reg_off = HHI_PCIE_PLL_CNTL,
740 .reg_off = HHI_PCIE_PLL_CNTL,
744 .table = axg_pcie_pll_params_table,
745 .init_regs = axg_pcie_init_regs,
746 .init_count = ARRAY_SIZE(axg_pcie_init_regs),
748 .hw.init = &(struct clk_init_data){
749 .name = "pcie_pll_dco",
750 .ops = &meson_clk_pll_ops,
751 .parent_data = &(const struct clk_parent_data) {
758 static struct clk_regmap axg_pcie_pll_od = {
759 .data = &(struct clk_regmap_div_data){
760 .offset = HHI_PCIE_PLL_CNTL,
763 .flags = CLK_DIVIDER_POWER_OF_TWO,
765 .hw.init = &(struct clk_init_data){
766 .name = "pcie_pll_od",
767 .ops = &clk_regmap_divider_ops,
768 .parent_hws = (const struct clk_hw *[]) {
772 .flags = CLK_SET_RATE_PARENT,
776 static struct clk_regmap axg_pcie_pll = {
777 .data = &(struct clk_regmap_div_data){
778 .offset = HHI_PCIE_PLL_CNTL6,
781 .flags = CLK_DIVIDER_POWER_OF_TWO,
783 .hw.init = &(struct clk_init_data){
785 .ops = &clk_regmap_divider_ops,
786 .parent_hws = (const struct clk_hw *[]) {
790 .flags = CLK_SET_RATE_PARENT,
794 static struct clk_regmap axg_pcie_mux = {
795 .data = &(struct clk_regmap_mux_data){
796 .offset = HHI_PCIE_PLL_CNTL6,
799 /* skip the parent mpll3, reserved for debug */
800 .table = (u32[]){ 1 },
802 .hw.init = &(struct clk_init_data){
804 .ops = &clk_regmap_mux_ops,
805 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_pll.hw },
807 .flags = CLK_SET_RATE_PARENT,
811 static struct clk_regmap axg_pcie_ref = {
812 .data = &(struct clk_regmap_mux_data){
813 .offset = HHI_PCIE_PLL_CNTL6,
816 /* skip the parent 0, reserved for debug */
817 .table = (u32[]){ 1 },
819 .hw.init = &(struct clk_init_data){
821 .ops = &clk_regmap_mux_ops,
822 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_mux.hw },
824 .flags = CLK_SET_RATE_PARENT,
828 static struct clk_regmap axg_pcie_cml_en0 = {
829 .data = &(struct clk_regmap_gate_data){
830 .offset = HHI_PCIE_PLL_CNTL6,
833 .hw.init = &(struct clk_init_data) {
834 .name = "pcie_cml_en0",
835 .ops = &clk_regmap_gate_ops,
836 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
838 .flags = CLK_SET_RATE_PARENT,
843 static struct clk_regmap axg_pcie_cml_en1 = {
844 .data = &(struct clk_regmap_gate_data){
845 .offset = HHI_PCIE_PLL_CNTL6,
848 .hw.init = &(struct clk_init_data) {
849 .name = "pcie_cml_en1",
850 .ops = &clk_regmap_gate_ops,
851 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
853 .flags = CLK_SET_RATE_PARENT,
857 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
858 static const struct clk_parent_data clk81_parent_data[] = {
859 { .fw_name = "xtal", },
860 { .hw = &axg_fclk_div7.hw },
861 { .hw = &axg_mpll1.hw },
862 { .hw = &axg_mpll2.hw },
863 { .hw = &axg_fclk_div4.hw },
864 { .hw = &axg_fclk_div3.hw },
865 { .hw = &axg_fclk_div5.hw },
868 static struct clk_regmap axg_mpeg_clk_sel = {
869 .data = &(struct clk_regmap_mux_data){
870 .offset = HHI_MPEG_CLK_CNTL,
873 .table = mux_table_clk81,
875 .hw.init = &(struct clk_init_data){
876 .name = "mpeg_clk_sel",
877 .ops = &clk_regmap_mux_ro_ops,
878 .parent_data = clk81_parent_data,
879 .num_parents = ARRAY_SIZE(clk81_parent_data),
883 static struct clk_regmap axg_mpeg_clk_div = {
884 .data = &(struct clk_regmap_div_data){
885 .offset = HHI_MPEG_CLK_CNTL,
889 .hw.init = &(struct clk_init_data){
890 .name = "mpeg_clk_div",
891 .ops = &clk_regmap_divider_ops,
892 .parent_hws = (const struct clk_hw *[]) {
896 .flags = CLK_SET_RATE_PARENT,
900 static struct clk_regmap axg_clk81 = {
901 .data = &(struct clk_regmap_gate_data){
902 .offset = HHI_MPEG_CLK_CNTL,
905 .hw.init = &(struct clk_init_data){
907 .ops = &clk_regmap_gate_ops,
908 .parent_hws = (const struct clk_hw *[]) {
912 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
916 static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] = {
917 { .fw_name = "xtal", },
918 { .hw = &axg_fclk_div2.hw },
919 { .hw = &axg_fclk_div3.hw },
920 { .hw = &axg_fclk_div5.hw },
921 { .hw = &axg_fclk_div7.hw },
923 * Following these parent clocks, we should also have had mpll2, mpll3
924 * and gp0_pll but these clocks are too precious to be used here. All
925 * the necessary rates for MMC and NAND operation can be acheived using
926 * xtal or fclk_div clocks
931 static struct clk_regmap axg_sd_emmc_b_clk0_sel = {
932 .data = &(struct clk_regmap_mux_data){
933 .offset = HHI_SD_EMMC_CLK_CNTL,
937 .hw.init = &(struct clk_init_data) {
938 .name = "sd_emmc_b_clk0_sel",
939 .ops = &clk_regmap_mux_ops,
940 .parent_data = axg_sd_emmc_clk0_parent_data,
941 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
942 .flags = CLK_SET_RATE_PARENT,
946 static struct clk_regmap axg_sd_emmc_b_clk0_div = {
947 .data = &(struct clk_regmap_div_data){
948 .offset = HHI_SD_EMMC_CLK_CNTL,
951 .flags = CLK_DIVIDER_ROUND_CLOSEST,
953 .hw.init = &(struct clk_init_data) {
954 .name = "sd_emmc_b_clk0_div",
955 .ops = &clk_regmap_divider_ops,
956 .parent_hws = (const struct clk_hw *[]) {
957 &axg_sd_emmc_b_clk0_sel.hw
960 .flags = CLK_SET_RATE_PARENT,
964 static struct clk_regmap axg_sd_emmc_b_clk0 = {
965 .data = &(struct clk_regmap_gate_data){
966 .offset = HHI_SD_EMMC_CLK_CNTL,
969 .hw.init = &(struct clk_init_data){
970 .name = "sd_emmc_b_clk0",
971 .ops = &clk_regmap_gate_ops,
972 .parent_hws = (const struct clk_hw *[]) {
973 &axg_sd_emmc_b_clk0_div.hw
976 .flags = CLK_SET_RATE_PARENT,
980 /* EMMC/NAND clock */
981 static struct clk_regmap axg_sd_emmc_c_clk0_sel = {
982 .data = &(struct clk_regmap_mux_data){
983 .offset = HHI_NAND_CLK_CNTL,
987 .hw.init = &(struct clk_init_data) {
988 .name = "sd_emmc_c_clk0_sel",
989 .ops = &clk_regmap_mux_ops,
990 .parent_data = axg_sd_emmc_clk0_parent_data,
991 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
992 .flags = CLK_SET_RATE_PARENT,
996 static struct clk_regmap axg_sd_emmc_c_clk0_div = {
997 .data = &(struct clk_regmap_div_data){
998 .offset = HHI_NAND_CLK_CNTL,
1001 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1003 .hw.init = &(struct clk_init_data) {
1004 .name = "sd_emmc_c_clk0_div",
1005 .ops = &clk_regmap_divider_ops,
1006 .parent_hws = (const struct clk_hw *[]) {
1007 &axg_sd_emmc_c_clk0_sel.hw
1010 .flags = CLK_SET_RATE_PARENT,
1014 static struct clk_regmap axg_sd_emmc_c_clk0 = {
1015 .data = &(struct clk_regmap_gate_data){
1016 .offset = HHI_NAND_CLK_CNTL,
1019 .hw.init = &(struct clk_init_data){
1020 .name = "sd_emmc_c_clk0",
1021 .ops = &clk_regmap_gate_ops,
1022 .parent_hws = (const struct clk_hw *[]) {
1023 &axg_sd_emmc_c_clk0_div.hw
1026 .flags = CLK_SET_RATE_PARENT,
1032 static const struct clk_hw *axg_vpu_parent_hws[] = {
1039 static struct clk_regmap axg_vpu_0_sel = {
1040 .data = &(struct clk_regmap_mux_data){
1041 .offset = HHI_VPU_CLK_CNTL,
1045 .hw.init = &(struct clk_init_data){
1046 .name = "vpu_0_sel",
1047 .ops = &clk_regmap_mux_ops,
1048 .parent_hws = axg_vpu_parent_hws,
1049 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
1050 /* We need a specific parent for VPU clock source, let it be set in DT */
1051 .flags = CLK_SET_RATE_NO_REPARENT,
1055 static struct clk_regmap axg_vpu_0_div = {
1056 .data = &(struct clk_regmap_div_data){
1057 .offset = HHI_VPU_CLK_CNTL,
1061 .hw.init = &(struct clk_init_data){
1062 .name = "vpu_0_div",
1063 .ops = &clk_regmap_divider_ops,
1064 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_0_sel.hw },
1066 .flags = CLK_SET_RATE_PARENT,
1070 static struct clk_regmap axg_vpu_0 = {
1071 .data = &(struct clk_regmap_gate_data){
1072 .offset = HHI_VPU_CLK_CNTL,
1075 .hw.init = &(struct clk_init_data) {
1077 .ops = &clk_regmap_gate_ops,
1078 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_0_div.hw },
1081 * We want to avoid CCF to disable the VPU clock if
1082 * display has been set by Bootloader
1084 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1088 static struct clk_regmap axg_vpu_1_sel = {
1089 .data = &(struct clk_regmap_mux_data){
1090 .offset = HHI_VPU_CLK_CNTL,
1094 .hw.init = &(struct clk_init_data){
1095 .name = "vpu_1_sel",
1096 .ops = &clk_regmap_mux_ops,
1097 .parent_hws = axg_vpu_parent_hws,
1098 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
1099 /* We need a specific parent for VPU clock source, let it be set in DT */
1100 .flags = CLK_SET_RATE_NO_REPARENT,
1104 static struct clk_regmap axg_vpu_1_div = {
1105 .data = &(struct clk_regmap_div_data){
1106 .offset = HHI_VPU_CLK_CNTL,
1110 .hw.init = &(struct clk_init_data){
1111 .name = "vpu_1_div",
1112 .ops = &clk_regmap_divider_ops,
1113 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_1_sel.hw },
1115 .flags = CLK_SET_RATE_PARENT,
1119 static struct clk_regmap axg_vpu_1 = {
1120 .data = &(struct clk_regmap_gate_data){
1121 .offset = HHI_VPU_CLK_CNTL,
1124 .hw.init = &(struct clk_init_data) {
1126 .ops = &clk_regmap_gate_ops,
1127 .parent_hws = (const struct clk_hw *[]) { &axg_vpu_1_div.hw },
1130 * We want to avoid CCF to disable the VPU clock if
1131 * display has been set by Bootloader
1133 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1137 static struct clk_regmap axg_vpu = {
1138 .data = &(struct clk_regmap_mux_data){
1139 .offset = HHI_VPU_CLK_CNTL,
1143 .hw.init = &(struct clk_init_data){
1145 .ops = &clk_regmap_mux_ops,
1146 .parent_hws = (const struct clk_hw *[]) {
1151 .flags = CLK_SET_RATE_NO_REPARENT,
1157 static struct clk_regmap axg_vapb_0_sel = {
1158 .data = &(struct clk_regmap_mux_data){
1159 .offset = HHI_VAPBCLK_CNTL,
1163 .hw.init = &(struct clk_init_data){
1164 .name = "vapb_0_sel",
1165 .ops = &clk_regmap_mux_ops,
1166 .parent_hws = axg_vpu_parent_hws,
1167 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
1168 .flags = CLK_SET_RATE_NO_REPARENT,
1172 static struct clk_regmap axg_vapb_0_div = {
1173 .data = &(struct clk_regmap_div_data){
1174 .offset = HHI_VAPBCLK_CNTL,
1178 .hw.init = &(struct clk_init_data){
1179 .name = "vapb_0_div",
1180 .ops = &clk_regmap_divider_ops,
1181 .parent_hws = (const struct clk_hw *[]) {
1185 .flags = CLK_SET_RATE_PARENT,
1189 static struct clk_regmap axg_vapb_0 = {
1190 .data = &(struct clk_regmap_gate_data){
1191 .offset = HHI_VAPBCLK_CNTL,
1194 .hw.init = &(struct clk_init_data) {
1196 .ops = &clk_regmap_gate_ops,
1197 .parent_hws = (const struct clk_hw *[]) {
1201 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1205 static struct clk_regmap axg_vapb_1_sel = {
1206 .data = &(struct clk_regmap_mux_data){
1207 .offset = HHI_VAPBCLK_CNTL,
1211 .hw.init = &(struct clk_init_data){
1212 .name = "vapb_1_sel",
1213 .ops = &clk_regmap_mux_ops,
1214 .parent_hws = axg_vpu_parent_hws,
1215 .num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
1216 .flags = CLK_SET_RATE_NO_REPARENT,
1220 static struct clk_regmap axg_vapb_1_div = {
1221 .data = &(struct clk_regmap_div_data){
1222 .offset = HHI_VAPBCLK_CNTL,
1226 .hw.init = &(struct clk_init_data){
1227 .name = "vapb_1_div",
1228 .ops = &clk_regmap_divider_ops,
1229 .parent_hws = (const struct clk_hw *[]) {
1233 .flags = CLK_SET_RATE_PARENT,
1237 static struct clk_regmap axg_vapb_1 = {
1238 .data = &(struct clk_regmap_gate_data){
1239 .offset = HHI_VAPBCLK_CNTL,
1242 .hw.init = &(struct clk_init_data) {
1244 .ops = &clk_regmap_gate_ops,
1245 .parent_hws = (const struct clk_hw *[]) {
1249 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1253 static struct clk_regmap axg_vapb_sel = {
1254 .data = &(struct clk_regmap_mux_data){
1255 .offset = HHI_VAPBCLK_CNTL,
1259 .hw.init = &(struct clk_init_data){
1261 .ops = &clk_regmap_mux_ops,
1262 .parent_hws = (const struct clk_hw *[]) {
1267 .flags = CLK_SET_RATE_NO_REPARENT,
1271 static struct clk_regmap axg_vapb = {
1272 .data = &(struct clk_regmap_gate_data){
1273 .offset = HHI_VAPBCLK_CNTL,
1276 .hw.init = &(struct clk_init_data) {
1278 .ops = &clk_regmap_gate_ops,
1279 .parent_hws = (const struct clk_hw *[]) { &axg_vapb_sel.hw },
1281 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1287 static const struct clk_hw *axg_vclk_parent_hws[] = {
1297 static struct clk_regmap axg_vclk_sel = {
1298 .data = &(struct clk_regmap_mux_data){
1299 .offset = HHI_VID_CLK_CNTL,
1303 .hw.init = &(struct clk_init_data){
1305 .ops = &clk_regmap_mux_ops,
1306 .parent_hws = axg_vclk_parent_hws,
1307 .num_parents = ARRAY_SIZE(axg_vclk_parent_hws),
1308 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1312 static struct clk_regmap axg_vclk2_sel = {
1313 .data = &(struct clk_regmap_mux_data){
1314 .offset = HHI_VIID_CLK_CNTL,
1318 .hw.init = &(struct clk_init_data){
1319 .name = "vclk2_sel",
1320 .ops = &clk_regmap_mux_ops,
1321 .parent_hws = axg_vclk_parent_hws,
1322 .num_parents = ARRAY_SIZE(axg_vclk_parent_hws),
1323 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1327 static struct clk_regmap axg_vclk_input = {
1328 .data = &(struct clk_regmap_gate_data){
1329 .offset = HHI_VID_CLK_DIV,
1332 .hw.init = &(struct clk_init_data) {
1333 .name = "vclk_input",
1334 .ops = &clk_regmap_gate_ops,
1335 .parent_hws = (const struct clk_hw *[]) { &axg_vclk_sel.hw },
1337 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1341 static struct clk_regmap axg_vclk2_input = {
1342 .data = &(struct clk_regmap_gate_data){
1343 .offset = HHI_VIID_CLK_DIV,
1346 .hw.init = &(struct clk_init_data) {
1347 .name = "vclk2_input",
1348 .ops = &clk_regmap_gate_ops,
1349 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2_sel.hw },
1351 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1355 static struct clk_regmap axg_vclk_div = {
1356 .data = &(struct clk_regmap_div_data){
1357 .offset = HHI_VID_CLK_DIV,
1361 .hw.init = &(struct clk_init_data){
1363 .ops = &clk_regmap_divider_ops,
1364 .parent_hws = (const struct clk_hw *[]) {
1368 .flags = CLK_GET_RATE_NOCACHE,
1372 static struct clk_regmap axg_vclk2_div = {
1373 .data = &(struct clk_regmap_div_data){
1374 .offset = HHI_VIID_CLK_DIV,
1378 .hw.init = &(struct clk_init_data){
1379 .name = "vclk2_div",
1380 .ops = &clk_regmap_divider_ops,
1381 .parent_hws = (const struct clk_hw *[]) {
1385 .flags = CLK_GET_RATE_NOCACHE,
1389 static struct clk_regmap axg_vclk = {
1390 .data = &(struct clk_regmap_gate_data){
1391 .offset = HHI_VID_CLK_CNTL,
1394 .hw.init = &(struct clk_init_data) {
1396 .ops = &clk_regmap_gate_ops,
1397 .parent_hws = (const struct clk_hw *[]) { &axg_vclk_div.hw },
1399 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1403 static struct clk_regmap axg_vclk2 = {
1404 .data = &(struct clk_regmap_gate_data){
1405 .offset = HHI_VIID_CLK_CNTL,
1408 .hw.init = &(struct clk_init_data) {
1410 .ops = &clk_regmap_gate_ops,
1411 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2_div.hw },
1413 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1417 static struct clk_regmap axg_vclk_div1 = {
1418 .data = &(struct clk_regmap_gate_data){
1419 .offset = HHI_VID_CLK_CNTL,
1422 .hw.init = &(struct clk_init_data) {
1423 .name = "vclk_div1",
1424 .ops = &clk_regmap_gate_ops,
1425 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1427 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1431 static struct clk_regmap axg_vclk_div2_en = {
1432 .data = &(struct clk_regmap_gate_data){
1433 .offset = HHI_VID_CLK_CNTL,
1436 .hw.init = &(struct clk_init_data) {
1437 .name = "vclk_div2_en",
1438 .ops = &clk_regmap_gate_ops,
1439 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1441 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1445 static struct clk_regmap axg_vclk_div4_en = {
1446 .data = &(struct clk_regmap_gate_data){
1447 .offset = HHI_VID_CLK_CNTL,
1450 .hw.init = &(struct clk_init_data) {
1451 .name = "vclk_div4_en",
1452 .ops = &clk_regmap_gate_ops,
1453 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1455 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1459 static struct clk_regmap axg_vclk_div6_en = {
1460 .data = &(struct clk_regmap_gate_data){
1461 .offset = HHI_VID_CLK_CNTL,
1464 .hw.init = &(struct clk_init_data) {
1465 .name = "vclk_div6_en",
1466 .ops = &clk_regmap_gate_ops,
1467 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1469 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1473 static struct clk_regmap axg_vclk_div12_en = {
1474 .data = &(struct clk_regmap_gate_data){
1475 .offset = HHI_VID_CLK_CNTL,
1478 .hw.init = &(struct clk_init_data) {
1479 .name = "vclk_div12_en",
1480 .ops = &clk_regmap_gate_ops,
1481 .parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1483 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1487 static struct clk_regmap axg_vclk2_div1 = {
1488 .data = &(struct clk_regmap_gate_data){
1489 .offset = HHI_VIID_CLK_CNTL,
1492 .hw.init = &(struct clk_init_data) {
1493 .name = "vclk2_div1",
1494 .ops = &clk_regmap_gate_ops,
1495 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1497 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1501 static struct clk_regmap axg_vclk2_div2_en = {
1502 .data = &(struct clk_regmap_gate_data){
1503 .offset = HHI_VIID_CLK_CNTL,
1506 .hw.init = &(struct clk_init_data) {
1507 .name = "vclk2_div2_en",
1508 .ops = &clk_regmap_gate_ops,
1509 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1511 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1515 static struct clk_regmap axg_vclk2_div4_en = {
1516 .data = &(struct clk_regmap_gate_data){
1517 .offset = HHI_VIID_CLK_CNTL,
1520 .hw.init = &(struct clk_init_data) {
1521 .name = "vclk2_div4_en",
1522 .ops = &clk_regmap_gate_ops,
1523 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1525 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1529 static struct clk_regmap axg_vclk2_div6_en = {
1530 .data = &(struct clk_regmap_gate_data){
1531 .offset = HHI_VIID_CLK_CNTL,
1534 .hw.init = &(struct clk_init_data) {
1535 .name = "vclk2_div6_en",
1536 .ops = &clk_regmap_gate_ops,
1537 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1539 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1543 static struct clk_regmap axg_vclk2_div12_en = {
1544 .data = &(struct clk_regmap_gate_data){
1545 .offset = HHI_VIID_CLK_CNTL,
1548 .hw.init = &(struct clk_init_data) {
1549 .name = "vclk2_div12_en",
1550 .ops = &clk_regmap_gate_ops,
1551 .parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1553 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1557 static struct clk_fixed_factor axg_vclk_div2 = {
1560 .hw.init = &(struct clk_init_data){
1561 .name = "vclk_div2",
1562 .ops = &clk_fixed_factor_ops,
1563 .parent_hws = (const struct clk_hw *[]) {
1564 &axg_vclk_div2_en.hw
1570 static struct clk_fixed_factor axg_vclk_div4 = {
1573 .hw.init = &(struct clk_init_data){
1574 .name = "vclk_div4",
1575 .ops = &clk_fixed_factor_ops,
1576 .parent_hws = (const struct clk_hw *[]) {
1577 &axg_vclk_div4_en.hw
1583 static struct clk_fixed_factor axg_vclk_div6 = {
1586 .hw.init = &(struct clk_init_data){
1587 .name = "vclk_div6",
1588 .ops = &clk_fixed_factor_ops,
1589 .parent_hws = (const struct clk_hw *[]) {
1590 &axg_vclk_div6_en.hw
1596 static struct clk_fixed_factor axg_vclk_div12 = {
1599 .hw.init = &(struct clk_init_data){
1600 .name = "vclk_div12",
1601 .ops = &clk_fixed_factor_ops,
1602 .parent_hws = (const struct clk_hw *[]) {
1603 &axg_vclk_div12_en.hw
1609 static struct clk_fixed_factor axg_vclk2_div2 = {
1612 .hw.init = &(struct clk_init_data){
1613 .name = "vclk2_div2",
1614 .ops = &clk_fixed_factor_ops,
1615 .parent_hws = (const struct clk_hw *[]) {
1616 &axg_vclk2_div2_en.hw
1622 static struct clk_fixed_factor axg_vclk2_div4 = {
1625 .hw.init = &(struct clk_init_data){
1626 .name = "vclk2_div4",
1627 .ops = &clk_fixed_factor_ops,
1628 .parent_hws = (const struct clk_hw *[]) {
1629 &axg_vclk2_div4_en.hw
1635 static struct clk_fixed_factor axg_vclk2_div6 = {
1638 .hw.init = &(struct clk_init_data){
1639 .name = "vclk2_div6",
1640 .ops = &clk_fixed_factor_ops,
1641 .parent_hws = (const struct clk_hw *[]) {
1642 &axg_vclk2_div6_en.hw
1648 static struct clk_fixed_factor axg_vclk2_div12 = {
1651 .hw.init = &(struct clk_init_data){
1652 .name = "vclk2_div12",
1653 .ops = &clk_fixed_factor_ops,
1654 .parent_hws = (const struct clk_hw *[]) {
1655 &axg_vclk2_div12_en.hw
1661 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1662 static const struct clk_hw *axg_cts_parent_hws[] = {
1672 &axg_vclk2_div12.hw,
1675 static struct clk_regmap axg_cts_encl_sel = {
1676 .data = &(struct clk_regmap_mux_data){
1677 .offset = HHI_VIID_CLK_DIV,
1680 .table = mux_table_cts_sel,
1682 .hw.init = &(struct clk_init_data){
1683 .name = "cts_encl_sel",
1684 .ops = &clk_regmap_mux_ops,
1685 .parent_hws = axg_cts_parent_hws,
1686 .num_parents = ARRAY_SIZE(axg_cts_parent_hws),
1687 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1691 static struct clk_regmap axg_cts_encl = {
1692 .data = &(struct clk_regmap_gate_data){
1693 .offset = HHI_VID_CLK_CNTL2,
1696 .hw.init = &(struct clk_init_data) {
1698 .ops = &clk_regmap_gate_ops,
1699 .parent_hws = (const struct clk_hw *[]) {
1700 &axg_cts_encl_sel.hw
1703 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1707 /* MIPI DSI Host Clock */
1709 static u32 mux_table_axg_vdin_meas[] = { 0, 1, 2, 3, 6, 7 };
1710 static const struct clk_parent_data axg_vdin_meas_parent_data[] = {
1711 { .fw_name = "xtal", },
1712 { .hw = &axg_fclk_div4.hw },
1713 { .hw = &axg_fclk_div3.hw },
1714 { .hw = &axg_fclk_div5.hw },
1715 { .hw = &axg_fclk_div2.hw },
1716 { .hw = &axg_fclk_div7.hw },
1719 static struct clk_regmap axg_vdin_meas_sel = {
1720 .data = &(struct clk_regmap_mux_data){
1721 .offset = HHI_VDIN_MEAS_CLK_CNTL,
1724 .flags = CLK_MUX_ROUND_CLOSEST,
1725 .table = mux_table_axg_vdin_meas,
1727 .hw.init = &(struct clk_init_data){
1728 .name = "vdin_meas_sel",
1729 .ops = &clk_regmap_mux_ops,
1730 .parent_data = axg_vdin_meas_parent_data,
1731 .num_parents = ARRAY_SIZE(axg_vdin_meas_parent_data),
1732 .flags = CLK_SET_RATE_PARENT,
1736 static struct clk_regmap axg_vdin_meas_div = {
1737 .data = &(struct clk_regmap_div_data){
1738 .offset = HHI_VDIN_MEAS_CLK_CNTL,
1742 .hw.init = &(struct clk_init_data){
1743 .name = "vdin_meas_div",
1744 .ops = &clk_regmap_divider_ops,
1745 .parent_hws = (const struct clk_hw *[]) {
1746 &axg_vdin_meas_sel.hw },
1748 .flags = CLK_SET_RATE_PARENT,
1752 static struct clk_regmap axg_vdin_meas = {
1753 .data = &(struct clk_regmap_gate_data){
1754 .offset = HHI_VDIN_MEAS_CLK_CNTL,
1757 .hw.init = &(struct clk_init_data) {
1758 .name = "vdin_meas",
1759 .ops = &clk_regmap_gate_ops,
1760 .parent_hws = (const struct clk_hw *[]) {
1761 &axg_vdin_meas_div.hw },
1763 .flags = CLK_SET_RATE_PARENT,
1767 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
1768 9, 10, 11, 13, 14, };
1769 static const struct clk_parent_data gen_clk_parent_data[] = {
1770 { .fw_name = "xtal", },
1771 { .hw = &axg_hifi_pll.hw },
1772 { .hw = &axg_mpll0.hw },
1773 { .hw = &axg_mpll1.hw },
1774 { .hw = &axg_mpll2.hw },
1775 { .hw = &axg_mpll3.hw },
1776 { .hw = &axg_fclk_div4.hw },
1777 { .hw = &axg_fclk_div3.hw },
1778 { .hw = &axg_fclk_div5.hw },
1779 { .hw = &axg_fclk_div7.hw },
1780 { .hw = &axg_gp0_pll.hw },
1783 static struct clk_regmap axg_gen_clk_sel = {
1784 .data = &(struct clk_regmap_mux_data){
1785 .offset = HHI_GEN_CLK_CNTL,
1788 .table = mux_table_gen_clk,
1790 .hw.init = &(struct clk_init_data){
1791 .name = "gen_clk_sel",
1792 .ops = &clk_regmap_mux_ops,
1794 * bits 15:12 selects from 14 possible parents:
1795 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
1796 * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
1797 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
1799 .parent_data = gen_clk_parent_data,
1800 .num_parents = ARRAY_SIZE(gen_clk_parent_data),
1804 static struct clk_regmap axg_gen_clk_div = {
1805 .data = &(struct clk_regmap_div_data){
1806 .offset = HHI_GEN_CLK_CNTL,
1810 .hw.init = &(struct clk_init_data){
1811 .name = "gen_clk_div",
1812 .ops = &clk_regmap_divider_ops,
1813 .parent_hws = (const struct clk_hw *[]) {
1817 .flags = CLK_SET_RATE_PARENT,
1821 static struct clk_regmap axg_gen_clk = {
1822 .data = &(struct clk_regmap_gate_data){
1823 .offset = HHI_GEN_CLK_CNTL,
1826 .hw.init = &(struct clk_init_data){
1828 .ops = &clk_regmap_gate_ops,
1829 .parent_hws = (const struct clk_hw *[]) {
1833 .flags = CLK_SET_RATE_PARENT,
1837 #define MESON_GATE(_name, _reg, _bit) \
1838 MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw)
1840 /* Everything Else (EE) domain gates */
1841 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
1842 static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
1843 static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
1844 static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
1845 static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
1846 static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
1847 static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
1848 static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
1849 static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
1850 static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
1851 static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
1852 static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
1853 static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
1854 static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
1855 static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
1856 static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
1857 static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
1858 static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
1859 static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
1860 static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
1862 static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
1863 static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
1864 static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
1865 static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
1866 static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
1867 static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
1868 static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
1869 static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
1870 static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
1871 static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
1872 static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
1874 static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1875 static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1876 static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
1877 static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
1878 static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
1879 static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
1880 static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
1881 static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
1883 /* Always On (AO) domain gates */
1885 static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
1886 static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
1887 static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
1888 static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
1889 static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
1891 /* Array of all clocks provided by this provider */
1893 static struct clk_hw *axg_hw_clks[] = {
1894 [CLKID_SYS_PLL] = &axg_sys_pll.hw,
1895 [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
1896 [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
1897 [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
1898 [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
1899 [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
1900 [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
1901 [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
1902 [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
1903 [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
1904 [CLKID_CLK81] = &axg_clk81.hw,
1905 [CLKID_MPLL0] = &axg_mpll0.hw,
1906 [CLKID_MPLL1] = &axg_mpll1.hw,
1907 [CLKID_MPLL2] = &axg_mpll2.hw,
1908 [CLKID_MPLL3] = &axg_mpll3.hw,
1909 [CLKID_DDR] = &axg_ddr.hw,
1910 [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
1911 [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
1912 [CLKID_ISA] = &axg_isa.hw,
1913 [CLKID_PL301] = &axg_pl301.hw,
1914 [CLKID_PERIPHS] = &axg_periphs.hw,
1915 [CLKID_SPICC0] = &axg_spicc_0.hw,
1916 [CLKID_I2C] = &axg_i2c.hw,
1917 [CLKID_RNG0] = &axg_rng0.hw,
1918 [CLKID_UART0] = &axg_uart0.hw,
1919 [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
1920 [CLKID_SPICC1] = &axg_spicc_1.hw,
1921 [CLKID_PCIE_A] = &axg_pcie_a.hw,
1922 [CLKID_PCIE_B] = &axg_pcie_b.hw,
1923 [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
1924 [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
1925 [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
1926 [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
1927 [CLKID_DMA] = &axg_dma.hw,
1928 [CLKID_SPI] = &axg_spi.hw,
1929 [CLKID_AUDIO] = &axg_audio.hw,
1930 [CLKID_ETH] = &axg_eth_core.hw,
1931 [CLKID_UART1] = &axg_uart1.hw,
1932 [CLKID_G2D] = &axg_g2d.hw,
1933 [CLKID_USB0] = &axg_usb0.hw,
1934 [CLKID_USB1] = &axg_usb1.hw,
1935 [CLKID_RESET] = &axg_reset.hw,
1936 [CLKID_USB] = &axg_usb_general.hw,
1937 [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
1938 [CLKID_EFUSE] = &axg_efuse.hw,
1939 [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
1940 [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
1941 [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
1942 [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
1943 [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
1944 [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
1945 [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
1946 [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
1947 [CLKID_GIC] = &axg_gic.hw,
1948 [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
1949 [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
1950 [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
1951 [CLKID_AO_IFACE] = &axg_ao_iface.hw,
1952 [CLKID_AO_I2C] = &axg_ao_i2c.hw,
1953 [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
1954 [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
1955 [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
1956 [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
1957 [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
1958 [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
1959 [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
1960 [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
1961 [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
1962 [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
1963 [CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
1964 [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
1965 [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
1966 [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
1967 [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
1968 [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
1969 [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
1970 [CLKID_PCIE_PLL] = &axg_pcie_pll.hw,
1971 [CLKID_PCIE_MUX] = &axg_pcie_mux.hw,
1972 [CLKID_PCIE_REF] = &axg_pcie_ref.hw,
1973 [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
1974 [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
1975 [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
1976 [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
1977 [CLKID_GEN_CLK] = &axg_gen_clk.hw,
1978 [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
1979 [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
1980 [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
1981 [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
1982 [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
1983 [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
1984 [CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw,
1985 [CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw,
1986 [CLKID_VPU_0] = &axg_vpu_0.hw,
1987 [CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw,
1988 [CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw,
1989 [CLKID_VPU_1] = &axg_vpu_1.hw,
1990 [CLKID_VPU] = &axg_vpu.hw,
1991 [CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw,
1992 [CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw,
1993 [CLKID_VAPB_0] = &axg_vapb_0.hw,
1994 [CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw,
1995 [CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw,
1996 [CLKID_VAPB_1] = &axg_vapb_1.hw,
1997 [CLKID_VAPB_SEL] = &axg_vapb_sel.hw,
1998 [CLKID_VAPB] = &axg_vapb.hw,
1999 [CLKID_VCLK] = &axg_vclk.hw,
2000 [CLKID_VCLK2] = &axg_vclk2.hw,
2001 [CLKID_VCLK_SEL] = &axg_vclk_sel.hw,
2002 [CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw,
2003 [CLKID_VCLK_INPUT] = &axg_vclk_input.hw,
2004 [CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw,
2005 [CLKID_VCLK_DIV] = &axg_vclk_div.hw,
2006 [CLKID_VCLK2_DIV] = &axg_vclk2_div.hw,
2007 [CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw,
2008 [CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw,
2009 [CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw,
2010 [CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw,
2011 [CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw,
2012 [CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw,
2013 [CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw,
2014 [CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw,
2015 [CLKID_VCLK_DIV1] = &axg_vclk_div1.hw,
2016 [CLKID_VCLK_DIV2] = &axg_vclk_div2.hw,
2017 [CLKID_VCLK_DIV4] = &axg_vclk_div4.hw,
2018 [CLKID_VCLK_DIV6] = &axg_vclk_div6.hw,
2019 [CLKID_VCLK_DIV12] = &axg_vclk_div12.hw,
2020 [CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw,
2021 [CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw,
2022 [CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw,
2023 [CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw,
2024 [CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw,
2025 [CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw,
2026 [CLKID_CTS_ENCL] = &axg_cts_encl.hw,
2027 [CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw,
2028 [CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw,
2029 [CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
2032 /* Convenience table to populate regmap in .probe */
2033 static struct clk_regmap *const axg_clk_regmaps[] = {
2072 &axg_sec_ahb_ahb3_bridge,
2079 &axg_sd_emmc_b_clk0,
2080 &axg_sd_emmc_c_clk0,
2082 &axg_sd_emmc_b_clk0_div,
2083 &axg_sd_emmc_c_clk0_div,
2085 &axg_sd_emmc_b_clk0_sel,
2086 &axg_sd_emmc_c_clk0_sel,
2151 &axg_vclk2_div12_en,
2159 static const struct meson_eeclkc_data axg_clkc_data = {
2160 .regmap_clks = axg_clk_regmaps,
2161 .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
2164 .num = ARRAY_SIZE(axg_hw_clks),
2169 static const struct of_device_id clkc_match_table[] = {
2170 { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
2173 MODULE_DEVICE_TABLE(of, clkc_match_table);
2175 static struct platform_driver axg_driver = {
2176 .probe = meson_eeclkc_probe,
2179 .of_match_table = clkc_match_table,
2183 module_platform_driver(axg_driver);
2184 MODULE_LICENSE("GPL v2");