1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2018 BayLibre, SAS.
4 * Author: Jerome Brunet <jbrunet@baylibre.com>
8 #include <linux/clk-provider.h>
9 #include <linux/init.h>
10 #include <linux/of_device.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/reset.h>
15 #include <linux/slab.h>
17 #include "axg-audio.h"
18 #include "clk-input.h"
19 #include "clk-regmap.h"
20 #include "clk-phase.h"
23 #define AUD_MST_IN_COUNT 8
24 #define AUD_SLV_SCLK_COUNT 10
25 #define AUD_SLV_LRCLK_COUNT 10
27 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) \
28 struct clk_regmap aud_##_name = { \
29 .data = &(struct clk_regmap_gate_data){ \
33 .hw.init = &(struct clk_init_data) { \
34 .name = "aud_"#_name, \
35 .ops = &clk_regmap_gate_ops, \
36 .parent_names = (const char *[]){ _pname }, \
38 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
42 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags) \
43 struct clk_regmap aud_##_name = { \
44 .data = &(struct clk_regmap_mux_data){ \
50 .hw.init = &(struct clk_init_data){ \
51 .name = "aud_"#_name, \
52 .ops = &clk_regmap_mux_ops, \
53 .parent_names = (_pnames), \
54 .num_parents = ARRAY_SIZE(_pnames), \
55 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
59 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) \
60 struct clk_regmap aud_##_name = { \
61 .data = &(struct clk_regmap_div_data){ \
67 .hw.init = &(struct clk_init_data){ \
68 .name = "aud_"#_name, \
69 .ops = &clk_regmap_divider_ops, \
70 .parent_names = (const char *[]) { _pname }, \
76 #define AUD_PCLK_GATE(_name, _bit) \
77 AUD_GATE(_name, AUDIO_CLK_GATE_EN, _bit, "audio_pclk", 0)
79 /* Audio peripheral clocks */
80 static AUD_PCLK_GATE(ddr_arb, 0);
81 static AUD_PCLK_GATE(pdm, 1);
82 static AUD_PCLK_GATE(tdmin_a, 2);
83 static AUD_PCLK_GATE(tdmin_b, 3);
84 static AUD_PCLK_GATE(tdmin_c, 4);
85 static AUD_PCLK_GATE(tdmin_lb, 5);
86 static AUD_PCLK_GATE(tdmout_a, 6);
87 static AUD_PCLK_GATE(tdmout_b, 7);
88 static AUD_PCLK_GATE(tdmout_c, 8);
89 static AUD_PCLK_GATE(frddr_a, 9);
90 static AUD_PCLK_GATE(frddr_b, 10);
91 static AUD_PCLK_GATE(frddr_c, 11);
92 static AUD_PCLK_GATE(toddr_a, 12);
93 static AUD_PCLK_GATE(toddr_b, 13);
94 static AUD_PCLK_GATE(toddr_c, 14);
95 static AUD_PCLK_GATE(loopback, 15);
96 static AUD_PCLK_GATE(spdifin, 16);
97 static AUD_PCLK_GATE(spdifout, 17);
98 static AUD_PCLK_GATE(resample, 18);
99 static AUD_PCLK_GATE(power_detect, 19);
101 /* Audio Master Clocks */
102 static const char * const mst_mux_parent_names[] = {
103 "aud_mst_in0", "aud_mst_in1", "aud_mst_in2", "aud_mst_in3",
104 "aud_mst_in4", "aud_mst_in5", "aud_mst_in6", "aud_mst_in7",
107 #define AUD_MST_MUX(_name, _reg, _flag) \
108 AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \
109 mst_mux_parent_names, CLK_SET_RATE_PARENT)
111 #define AUD_MST_MCLK_MUX(_name, _reg) \
112 AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
114 #define AUD_MST_SYS_MUX(_name, _reg) \
115 AUD_MST_MUX(_name, _reg, 0)
117 static AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
118 static AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL);
119 static AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL);
120 static AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL);
121 static AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL);
122 static AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL);
123 static AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
124 static AUD_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
125 static AUD_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
126 static AUD_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
128 #define AUD_MST_DIV(_name, _reg, _flag) \
129 AUD_DIV(_name##_div, _reg, 0, 16, _flag, \
130 "aud_"#_name"_sel", CLK_SET_RATE_PARENT) \
132 #define AUD_MST_MCLK_DIV(_name, _reg) \
133 AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
135 #define AUD_MST_SYS_DIV(_name, _reg) \
136 AUD_MST_DIV(_name, _reg, 0)
138 static AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL);
139 static AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL);
140 static AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL);
141 static AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL);
142 static AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL);
143 static AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL);
144 static AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
145 static AUD_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
146 static AUD_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
147 static AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
149 #define AUD_MST_MCLK_GATE(_name, _reg) \
150 AUD_GATE(_name, _reg, 31, "aud_"#_name"_div", \
153 static AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
154 static AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL);
155 static AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL);
156 static AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL);
157 static AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL);
158 static AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL);
159 static AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
160 static AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
161 static AUD_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
162 static AUD_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
165 #define AUD_MST_SCLK_PRE_EN(_name, _reg) \
166 AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \
167 "aud_mst_"#_name"_mclk", 0)
169 static AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
170 static AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
171 static AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
172 static AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
173 static AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
174 static AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
176 #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \
177 _hi_shift, _hi_width, _pname, _iflags) \
178 struct clk_regmap aud_##_name = { \
179 .data = &(struct meson_sclk_div_data) { \
182 .shift = (_div_shift), \
183 .width = (_div_width), \
187 .shift = (_hi_shift), \
188 .width = (_hi_width), \
191 .hw.init = &(struct clk_init_data) { \
192 .name = "aud_"#_name, \
193 .ops = &meson_sclk_div_ops, \
194 .parent_names = (const char *[]) { _pname }, \
196 .flags = (_iflags), \
200 #define AUD_MST_SCLK_DIV(_name, _reg) \
201 AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \
202 "aud_mst_"#_name"_sclk_pre_en", \
205 static AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
206 static AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
207 static AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
208 static AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
209 static AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
210 static AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
212 #define AUD_MST_SCLK_POST_EN(_name, _reg) \
213 AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \
214 "aud_mst_"#_name"_sclk_div", CLK_SET_RATE_PARENT)
216 static AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
217 static AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
218 static AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
219 static AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
220 static AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
221 static AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
223 #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \
225 struct clk_regmap aud_##_name = { \
226 .data = &(struct meson_clk_triphase_data) { \
229 .shift = (_shift0), \
234 .shift = (_shift1), \
239 .shift = (_shift2), \
243 .hw.init = &(struct clk_init_data) { \
244 .name = "aud_"#_name, \
245 .ops = &meson_clk_triphase_ops, \
246 .parent_names = (const char *[]) { _pname }, \
248 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
252 #define AUD_MST_SCLK(_name, _reg) \
253 AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \
254 "aud_mst_"#_name"_sclk_post_en", CLK_SET_RATE_PARENT)
256 static AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
257 static AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
258 static AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
259 static AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
260 static AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
261 static AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
263 #define AUD_MST_LRCLK_DIV(_name, _reg) \
264 AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \
265 "aud_mst_"#_name"_sclk_post_en", 0) \
267 static AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
268 static AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
269 static AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
270 static AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
271 static AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
272 static AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
274 #define AUD_MST_LRCLK(_name, _reg) \
275 AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \
276 "aud_mst_"#_name"_lrclk_div", CLK_SET_RATE_PARENT)
278 static AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
279 static AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
280 static AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
281 static AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
282 static AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
283 static AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
285 static const char * const tdm_sclk_parent_names[] = {
286 "aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk",
287 "aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk",
288 "aud_slv_sclk0", "aud_slv_sclk1", "aud_slv_sclk2",
289 "aud_slv_sclk3", "aud_slv_sclk4", "aud_slv_sclk5",
290 "aud_slv_sclk6", "aud_slv_sclk7", "aud_slv_sclk8",
294 #define AUD_TDM_SCLK_MUX(_name, _reg) \
295 AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \
296 CLK_MUX_ROUND_CLOSEST, \
297 tdm_sclk_parent_names, 0)
299 static AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);
300 static AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);
301 static AUD_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL);
302 static AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
303 static AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
304 static AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
305 static AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
307 #define AUD_TDM_SCLK_PRE_EN(_name, _reg) \
308 AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \
309 "aud_tdm"#_name"_sclk_sel", CLK_SET_RATE_PARENT)
311 static AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
312 static AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
313 static AUD_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
314 static AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
315 static AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
316 static AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
317 static AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
319 #define AUD_TDM_SCLK_POST_EN(_name, _reg) \
320 AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \
321 "aud_tdm"#_name"_sclk_pre_en", CLK_SET_RATE_PARENT)
323 static AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
324 static AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
325 static AUD_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
326 static AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
327 static AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
328 static AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
329 static AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
331 #define AUD_TDM_SCLK(_name, _reg) \
332 struct clk_regmap aud_tdm##_name##_sclk = { \
333 .data = &(struct meson_clk_phase_data) { \
340 .hw.init = &(struct clk_init_data) { \
341 .name = "aud_tdm"#_name"_sclk", \
342 .ops = &meson_clk_phase_ops, \
343 .parent_names = (const char *[]) \
344 { "aud_tdm"#_name"_sclk_post_en" }, \
346 .flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT, \
350 static AUD_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
351 static AUD_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
352 static AUD_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
353 static AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
354 static AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
355 static AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
356 static AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
358 static const char * const tdm_lrclk_parent_names[] = {
359 "aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk",
360 "aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk",
361 "aud_slv_lrclk0", "aud_slv_lrclk1", "aud_slv_lrclk2",
362 "aud_slv_lrclk3", "aud_slv_lrclk4", "aud_slv_lrclk5",
363 "aud_slv_lrclk6", "aud_slv_lrclk7", "aud_slv_lrclk8",
367 #define AUD_TDM_LRLCK(_name, _reg) \
368 AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \
369 CLK_MUX_ROUND_CLOSEST, \
370 tdm_lrclk_parent_names, 0)
372 static AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
373 static AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
374 static AUD_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
375 static AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
376 static AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
377 static AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
378 static AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
381 * Array of all clocks provided by this provider
382 * The input clocks of the controller will be populated at runtime
384 static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
386 [AUD_CLKID_DDR_ARB] = &aud_ddr_arb.hw,
387 [AUD_CLKID_PDM] = &aud_pdm.hw,
388 [AUD_CLKID_TDMIN_A] = &aud_tdmin_a.hw,
389 [AUD_CLKID_TDMIN_B] = &aud_tdmin_b.hw,
390 [AUD_CLKID_TDMIN_C] = &aud_tdmin_c.hw,
391 [AUD_CLKID_TDMIN_LB] = &aud_tdmin_lb.hw,
392 [AUD_CLKID_TDMOUT_A] = &aud_tdmout_a.hw,
393 [AUD_CLKID_TDMOUT_B] = &aud_tdmout_b.hw,
394 [AUD_CLKID_TDMOUT_C] = &aud_tdmout_c.hw,
395 [AUD_CLKID_FRDDR_A] = &aud_frddr_a.hw,
396 [AUD_CLKID_FRDDR_B] = &aud_frddr_b.hw,
397 [AUD_CLKID_FRDDR_C] = &aud_frddr_c.hw,
398 [AUD_CLKID_TODDR_A] = &aud_toddr_a.hw,
399 [AUD_CLKID_TODDR_B] = &aud_toddr_b.hw,
400 [AUD_CLKID_TODDR_C] = &aud_toddr_c.hw,
401 [AUD_CLKID_LOOPBACK] = &aud_loopback.hw,
402 [AUD_CLKID_SPDIFIN] = &aud_spdifin.hw,
403 [AUD_CLKID_SPDIFOUT] = &aud_spdifout.hw,
404 [AUD_CLKID_RESAMPLE] = &aud_resample.hw,
405 [AUD_CLKID_POWER_DETECT] = &aud_power_detect.hw,
406 [AUD_CLKID_MST_A_MCLK_SEL] = &aud_mst_a_mclk_sel.hw,
407 [AUD_CLKID_MST_B_MCLK_SEL] = &aud_mst_b_mclk_sel.hw,
408 [AUD_CLKID_MST_C_MCLK_SEL] = &aud_mst_c_mclk_sel.hw,
409 [AUD_CLKID_MST_D_MCLK_SEL] = &aud_mst_d_mclk_sel.hw,
410 [AUD_CLKID_MST_E_MCLK_SEL] = &aud_mst_e_mclk_sel.hw,
411 [AUD_CLKID_MST_F_MCLK_SEL] = &aud_mst_f_mclk_sel.hw,
412 [AUD_CLKID_MST_A_MCLK_DIV] = &aud_mst_a_mclk_div.hw,
413 [AUD_CLKID_MST_B_MCLK_DIV] = &aud_mst_b_mclk_div.hw,
414 [AUD_CLKID_MST_C_MCLK_DIV] = &aud_mst_c_mclk_div.hw,
415 [AUD_CLKID_MST_D_MCLK_DIV] = &aud_mst_d_mclk_div.hw,
416 [AUD_CLKID_MST_E_MCLK_DIV] = &aud_mst_e_mclk_div.hw,
417 [AUD_CLKID_MST_F_MCLK_DIV] = &aud_mst_f_mclk_div.hw,
418 [AUD_CLKID_MST_A_MCLK] = &aud_mst_a_mclk.hw,
419 [AUD_CLKID_MST_B_MCLK] = &aud_mst_b_mclk.hw,
420 [AUD_CLKID_MST_C_MCLK] = &aud_mst_c_mclk.hw,
421 [AUD_CLKID_MST_D_MCLK] = &aud_mst_d_mclk.hw,
422 [AUD_CLKID_MST_E_MCLK] = &aud_mst_e_mclk.hw,
423 [AUD_CLKID_MST_F_MCLK] = &aud_mst_f_mclk.hw,
424 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &aud_spdifout_clk_sel.hw,
425 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &aud_spdifout_clk_div.hw,
426 [AUD_CLKID_SPDIFOUT_CLK] = &aud_spdifout_clk.hw,
427 [AUD_CLKID_SPDIFIN_CLK_SEL] = &aud_spdifin_clk_sel.hw,
428 [AUD_CLKID_SPDIFIN_CLK_DIV] = &aud_spdifin_clk_div.hw,
429 [AUD_CLKID_SPDIFIN_CLK] = &aud_spdifin_clk.hw,
430 [AUD_CLKID_PDM_DCLK_SEL] = &aud_pdm_dclk_sel.hw,
431 [AUD_CLKID_PDM_DCLK_DIV] = &aud_pdm_dclk_div.hw,
432 [AUD_CLKID_PDM_DCLK] = &aud_pdm_dclk.hw,
433 [AUD_CLKID_PDM_SYSCLK_SEL] = &aud_pdm_sysclk_sel.hw,
434 [AUD_CLKID_PDM_SYSCLK_DIV] = &aud_pdm_sysclk_div.hw,
435 [AUD_CLKID_PDM_SYSCLK] = &aud_pdm_sysclk.hw,
436 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &aud_mst_a_sclk_pre_en.hw,
437 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &aud_mst_b_sclk_pre_en.hw,
438 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &aud_mst_c_sclk_pre_en.hw,
439 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &aud_mst_d_sclk_pre_en.hw,
440 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &aud_mst_e_sclk_pre_en.hw,
441 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &aud_mst_f_sclk_pre_en.hw,
442 [AUD_CLKID_MST_A_SCLK_DIV] = &aud_mst_a_sclk_div.hw,
443 [AUD_CLKID_MST_B_SCLK_DIV] = &aud_mst_b_sclk_div.hw,
444 [AUD_CLKID_MST_C_SCLK_DIV] = &aud_mst_c_sclk_div.hw,
445 [AUD_CLKID_MST_D_SCLK_DIV] = &aud_mst_d_sclk_div.hw,
446 [AUD_CLKID_MST_E_SCLK_DIV] = &aud_mst_e_sclk_div.hw,
447 [AUD_CLKID_MST_F_SCLK_DIV] = &aud_mst_f_sclk_div.hw,
448 [AUD_CLKID_MST_A_SCLK_POST_EN] = &aud_mst_a_sclk_post_en.hw,
449 [AUD_CLKID_MST_B_SCLK_POST_EN] = &aud_mst_b_sclk_post_en.hw,
450 [AUD_CLKID_MST_C_SCLK_POST_EN] = &aud_mst_c_sclk_post_en.hw,
451 [AUD_CLKID_MST_D_SCLK_POST_EN] = &aud_mst_d_sclk_post_en.hw,
452 [AUD_CLKID_MST_E_SCLK_POST_EN] = &aud_mst_e_sclk_post_en.hw,
453 [AUD_CLKID_MST_F_SCLK_POST_EN] = &aud_mst_f_sclk_post_en.hw,
454 [AUD_CLKID_MST_A_SCLK] = &aud_mst_a_sclk.hw,
455 [AUD_CLKID_MST_B_SCLK] = &aud_mst_b_sclk.hw,
456 [AUD_CLKID_MST_C_SCLK] = &aud_mst_c_sclk.hw,
457 [AUD_CLKID_MST_D_SCLK] = &aud_mst_d_sclk.hw,
458 [AUD_CLKID_MST_E_SCLK] = &aud_mst_e_sclk.hw,
459 [AUD_CLKID_MST_F_SCLK] = &aud_mst_f_sclk.hw,
460 [AUD_CLKID_MST_A_LRCLK_DIV] = &aud_mst_a_lrclk_div.hw,
461 [AUD_CLKID_MST_B_LRCLK_DIV] = &aud_mst_b_lrclk_div.hw,
462 [AUD_CLKID_MST_C_LRCLK_DIV] = &aud_mst_c_lrclk_div.hw,
463 [AUD_CLKID_MST_D_LRCLK_DIV] = &aud_mst_d_lrclk_div.hw,
464 [AUD_CLKID_MST_E_LRCLK_DIV] = &aud_mst_e_lrclk_div.hw,
465 [AUD_CLKID_MST_F_LRCLK_DIV] = &aud_mst_f_lrclk_div.hw,
466 [AUD_CLKID_MST_A_LRCLK] = &aud_mst_a_lrclk.hw,
467 [AUD_CLKID_MST_B_LRCLK] = &aud_mst_b_lrclk.hw,
468 [AUD_CLKID_MST_C_LRCLK] = &aud_mst_c_lrclk.hw,
469 [AUD_CLKID_MST_D_LRCLK] = &aud_mst_d_lrclk.hw,
470 [AUD_CLKID_MST_E_LRCLK] = &aud_mst_e_lrclk.hw,
471 [AUD_CLKID_MST_F_LRCLK] = &aud_mst_f_lrclk.hw,
472 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &aud_tdmin_a_sclk_sel.hw,
473 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &aud_tdmin_b_sclk_sel.hw,
474 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &aud_tdmin_c_sclk_sel.hw,
475 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &aud_tdmin_lb_sclk_sel.hw,
476 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &aud_tdmout_a_sclk_sel.hw,
477 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &aud_tdmout_b_sclk_sel.hw,
478 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &aud_tdmout_c_sclk_sel.hw,
479 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &aud_tdmin_a_sclk_pre_en.hw,
480 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &aud_tdmin_b_sclk_pre_en.hw,
481 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &aud_tdmin_c_sclk_pre_en.hw,
482 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &aud_tdmin_lb_sclk_pre_en.hw,
483 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &aud_tdmout_a_sclk_pre_en.hw,
484 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &aud_tdmout_b_sclk_pre_en.hw,
485 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &aud_tdmout_c_sclk_pre_en.hw,
486 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &aud_tdmin_a_sclk_post_en.hw,
487 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &aud_tdmin_b_sclk_post_en.hw,
488 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &aud_tdmin_c_sclk_post_en.hw,
489 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &aud_tdmin_lb_sclk_post_en.hw,
490 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &aud_tdmout_a_sclk_post_en.hw,
491 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &aud_tdmout_b_sclk_post_en.hw,
492 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &aud_tdmout_c_sclk_post_en.hw,
493 [AUD_CLKID_TDMIN_A_SCLK] = &aud_tdmin_a_sclk.hw,
494 [AUD_CLKID_TDMIN_B_SCLK] = &aud_tdmin_b_sclk.hw,
495 [AUD_CLKID_TDMIN_C_SCLK] = &aud_tdmin_c_sclk.hw,
496 [AUD_CLKID_TDMIN_LB_SCLK] = &aud_tdmin_lb_sclk.hw,
497 [AUD_CLKID_TDMOUT_A_SCLK] = &aud_tdmout_a_sclk.hw,
498 [AUD_CLKID_TDMOUT_B_SCLK] = &aud_tdmout_b_sclk.hw,
499 [AUD_CLKID_TDMOUT_C_SCLK] = &aud_tdmout_c_sclk.hw,
500 [AUD_CLKID_TDMIN_A_LRCLK] = &aud_tdmin_a_lrclk.hw,
501 [AUD_CLKID_TDMIN_B_LRCLK] = &aud_tdmin_b_lrclk.hw,
502 [AUD_CLKID_TDMIN_C_LRCLK] = &aud_tdmin_c_lrclk.hw,
503 [AUD_CLKID_TDMIN_LB_LRCLK] = &aud_tdmin_lb_lrclk.hw,
504 [AUD_CLKID_TDMOUT_A_LRCLK] = &aud_tdmout_a_lrclk.hw,
505 [AUD_CLKID_TDMOUT_B_LRCLK] = &aud_tdmout_b_lrclk.hw,
506 [AUD_CLKID_TDMOUT_C_LRCLK] = &aud_tdmout_c_lrclk.hw,
512 /* Convenience table to populate regmap in .probe() */
513 static struct clk_regmap *const aud_clk_regmaps[] = {
552 &aud_spdifout_clk_sel,
553 &aud_spdifout_clk_div,
555 &aud_spdifin_clk_sel,
556 &aud_spdifin_clk_div,
564 &aud_mst_a_sclk_pre_en,
565 &aud_mst_b_sclk_pre_en,
566 &aud_mst_c_sclk_pre_en,
567 &aud_mst_d_sclk_pre_en,
568 &aud_mst_e_sclk_pre_en,
569 &aud_mst_f_sclk_pre_en,
576 &aud_mst_a_sclk_post_en,
577 &aud_mst_b_sclk_post_en,
578 &aud_mst_c_sclk_post_en,
579 &aud_mst_d_sclk_post_en,
580 &aud_mst_e_sclk_post_en,
581 &aud_mst_f_sclk_post_en,
588 &aud_mst_a_lrclk_div,
589 &aud_mst_b_lrclk_div,
590 &aud_mst_c_lrclk_div,
591 &aud_mst_d_lrclk_div,
592 &aud_mst_e_lrclk_div,
593 &aud_mst_f_lrclk_div,
600 &aud_tdmin_a_sclk_sel,
601 &aud_tdmin_b_sclk_sel,
602 &aud_tdmin_c_sclk_sel,
603 &aud_tdmin_lb_sclk_sel,
604 &aud_tdmout_a_sclk_sel,
605 &aud_tdmout_b_sclk_sel,
606 &aud_tdmout_c_sclk_sel,
607 &aud_tdmin_a_sclk_pre_en,
608 &aud_tdmin_b_sclk_pre_en,
609 &aud_tdmin_c_sclk_pre_en,
610 &aud_tdmin_lb_sclk_pre_en,
611 &aud_tdmout_a_sclk_pre_en,
612 &aud_tdmout_b_sclk_pre_en,
613 &aud_tdmout_c_sclk_pre_en,
614 &aud_tdmin_a_sclk_post_en,
615 &aud_tdmin_b_sclk_post_en,
616 &aud_tdmin_c_sclk_post_en,
617 &aud_tdmin_lb_sclk_post_en,
618 &aud_tdmout_a_sclk_post_en,
619 &aud_tdmout_b_sclk_post_en,
620 &aud_tdmout_c_sclk_post_en,
637 static int devm_clk_get_enable(struct device *dev, char *id)
642 clk = devm_clk_get(dev, id);
645 if (ret != -EPROBE_DEFER)
646 dev_err(dev, "failed to get %s", id);
650 ret = clk_prepare_enable(clk);
652 dev_err(dev, "failed to enable %s", id);
656 ret = devm_add_action_or_reset(dev,
657 (void(*)(void *))clk_disable_unprepare,
660 dev_err(dev, "failed to add reset action on %s", id);
667 static int axg_register_clk_hw_input(struct device *dev,
675 clk_name = kasprintf(GFP_KERNEL, "aud_%s", name);
679 hw = meson_clk_hw_register_input(dev, name, clk_name, 0);
681 /* It is ok if an input clock is missing */
682 if (PTR_ERR(hw) == -ENOENT) {
683 dev_dbg(dev, "%s not provided", name);
686 if (err != -EPROBE_DEFER)
687 dev_err(dev, "failed to get %s clock", name);
690 axg_audio_hw_onecell_data.hws[clkid] = hw;
697 static int axg_register_clk_hw_inputs(struct device *dev,
698 const char *basename,
705 for (i = 0; i < count; i++) {
706 name = kasprintf(GFP_KERNEL, "%s%d", basename, i);
710 ret = axg_register_clk_hw_input(dev, name, clkid + i);
719 static const struct regmap_config axg_audio_regmap_cfg = {
723 .max_register = AUDIO_CLK_PDMIN_CTRL1,
726 static int axg_audio_clkc_probe(struct platform_device *pdev)
728 struct device *dev = &pdev->dev;
730 struct resource *res;
735 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
736 regs = devm_ioremap_resource(dev, res);
738 return PTR_ERR(regs);
740 map = devm_regmap_init_mmio(dev, regs, &axg_audio_regmap_cfg);
742 dev_err(dev, "failed to init regmap: %ld\n", PTR_ERR(map));
746 /* Get the mandatory peripheral clock */
747 ret = devm_clk_get_enable(dev, "pclk");
751 ret = device_reset(dev);
753 dev_err(dev, "failed to reset device\n");
757 /* Register the peripheral input clock */
758 hw = meson_clk_hw_register_input(dev, "pclk", "audio_pclk", 0);
762 axg_audio_hw_onecell_data.hws[AUD_CLKID_PCLK] = hw;
764 /* Register optional input master clocks */
765 ret = axg_register_clk_hw_inputs(dev, "mst_in",
771 /* Register optional input slave sclks */
772 ret = axg_register_clk_hw_inputs(dev, "slv_sclk",
774 AUD_CLKID_SLV_SCLK0);
778 /* Register optional input slave lrclks */
779 ret = axg_register_clk_hw_inputs(dev, "slv_lrclk",
781 AUD_CLKID_SLV_LRCLK0);
785 /* Populate regmap for the regmap backed clocks */
786 for (i = 0; i < ARRAY_SIZE(aud_clk_regmaps); i++)
787 aud_clk_regmaps[i]->map = map;
789 /* Take care to skip the registered input clocks */
790 for (i = AUD_CLKID_DDR_ARB; i < axg_audio_hw_onecell_data.num; i++) {
791 hw = axg_audio_hw_onecell_data.hws[i];
792 /* array might be sparse */
796 ret = devm_clk_hw_register(dev, hw);
798 dev_err(dev, "failed to register clock %s\n",
804 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
805 &axg_audio_hw_onecell_data);
808 static const struct of_device_id clkc_match_table[] = {
809 { .compatible = "amlogic,axg-audio-clkc" },
812 MODULE_DEVICE_TABLE(of, clkc_match_table);
814 static struct platform_driver axg_audio_driver = {
815 .probe = axg_audio_clkc_probe,
817 .name = "axg-audio-clkc",
818 .of_match_table = clkc_match_table,
821 module_platform_driver(axg_audio_driver);
823 MODULE_DESCRIPTION("Amlogic A113x Audio Clock driver");
824 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
825 MODULE_LICENSE("GPL v2");