drivers/clk/mediatek/clk-mtk.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2018 MediaTek Inc.
   4  * Author: Ryder Lee <ryder.lee@mediatek.com>
   5  */
   6
   7 #ifndef __DRV_CLK_MTK_H
   8 #define __DRV_CLK_MTK_H
   9
  10 #include <linux/bitops.h>
  11 #define CLK_XTAL                        0
  12 #define MHZ                             (1000 * 1000)
  13
  14 /* flags in struct mtk_clk_tree */
  15
  16 /* clk id == 0 doesn't mean it's xtal clk */
  17 #define CLK_BYPASS_XTAL                 BIT(0)
  18
  19 #define HAVE_RST_BAR                    BIT(0)
  20 #define CLK_DOMAIN_SCPSYS               BIT(0)
  21 #define CLK_MUX_SETCLR_UPD              BIT(1)
  22
  23 #define CLK_GATE_SETCLR                 BIT(0)
  24 #define CLK_GATE_SETCLR_INV             BIT(1)
  25 #define CLK_GATE_NO_SETCLR              BIT(2)
  26 #define CLK_GATE_NO_SETCLR_INV          BIT(3)
  27 #define CLK_GATE_MASK                   GENMASK(3, 0)
  28
  29 #define CLK_PARENT_APMIXED              BIT(4)
  30 #define CLK_PARENT_TOPCKGEN             BIT(5)
  31 #define CLK_PARENT_INFRASYS             BIT(6)
  32 #define CLK_PARENT_MASK                 GENMASK(6, 4)
  33
  34 #define ETHSYS_HIFSYS_RST_CTRL_OFS      0x34
  35
  36 /* struct mtk_pll_data - hardware-specific PLLs data */
  37 struct mtk_pll_data {
  38         const int id;
  39         u32 reg;
  40         u32 pwr_reg;
  41         u32 en_mask;
  42         u32 pd_reg;
  43         int pd_shift;
  44         u32 flags;
  45         u32 rst_bar_mask;
  46         u64 fmax;
  47         u64 fmin;
  48         int pcwbits;
  49         int pcwibits;
  50         u32 pcw_reg;
  51         int pcw_shift;
  52         u32 pcw_chg_reg;
  53 };
  54
  55 /**
  56  * struct mtk_fixed_clk - fixed clocks
  57  *
  58  * @id:         index of clocks
  59  * @parent:     index of parnet clocks
  60  * @rate:       fixed rate
  61  */
  62 struct mtk_fixed_clk {
  63         const int id;
  64         const int parent;
  65         unsigned long rate;
  66 };
  67
  68 #define FIXED_CLK(_id, _parent, _rate) {                \
  69                 .id = _id,                              \
  70                 .parent = _parent,                      \
  71                 .rate = _rate,                          \
  72         }
  73
  74 /**
  75  * struct mtk_fixed_factor - fixed multiplier and divider clocks
  76  *
  77  * @id:         index of clocks
  78  * @parent:     index of parnet clocks
  79  * @mult:       multiplier
  80  * @div:        divider
  81  * @flag:       hardware-specific flags
  82  */
  83 struct mtk_fixed_factor {
  84         const int id;
  85         const int parent;
  86         u32 mult;
  87         u32 div;
  88         u32 flags;
  89 };
  90
  91 #define FACTOR(_id, _parent, _mult, _div, _flags) {     \
  92                 .id = _id,                              \
  93                 .parent = _parent,                      \
  94                 .mult = _mult,                          \
  95                 .div = _div,                            \
  96                 .flags = _flags,                        \
  97         }
  98
  99 /**
 100  * struct mtk_composite - aggregate clock of mux, divider and gate clocks
 101  *
 102  * @id:                 index of clocks
 103  * @parent:             index of parnet clocks
 104  * @mux_reg:            hardware-specific mux register
 105  * @gate_reg:           hardware-specific gate register
 106  * @mux_mask:           mask to the mux bit field
 107  * @mux_shift:          shift to the mux bit field
 108  * @gate_shift:         shift to the gate bit field
 109  * @num_parents:        number of parent clocks
 110  * @flags:              hardware-specific flags
 111  */
 112 struct mtk_composite {
 113         const int id;
 114         const int *parent;
 115         u32 mux_reg;
 116         u32 mux_set_reg;
 117         u32 mux_clr_reg;
 118         u32 upd_reg;
 119         u32 gate_reg;
 120         u32 mux_mask;
 121         signed char mux_shift;
 122         signed char upd_shift;
 123         signed char gate_shift;
 124         signed char num_parents;
 125         u16 flags;
 126 };
 127
 128 #define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate,      \
 129                        _flags) {                                        \
 130                 .id = _id,                                              \
 131                 .mux_reg = _reg,                                        \
 132                 .mux_shift = _shift,                                    \
 133                 .mux_mask = BIT(_width) - 1,                            \
 134                 .gate_reg = _reg,                                       \
 135                 .gate_shift = _gate,                                    \
 136                 .parent = _parents,                                     \
 137                 .num_parents = ARRAY_SIZE(_parents),                    \
 138                 .flags = _flags,                                        \
 139         }
 140
 141 #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate)            \
 142         MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0)
 143
 144 #define MUX(_id, _parents, _reg, _shift, _width) {                      \
 145                 .id = _id,                                              \
 146                 .mux_reg = _reg,                                        \
 147                 .mux_shift = _shift,                                    \
 148                 .mux_mask = BIT(_width) - 1,                            \
 149                 .gate_shift = -1,                                       \
 150                 .parent = _parents,                                     \
 151                 .num_parents = ARRAY_SIZE(_parents),                    \
 152                 .flags = 0,                                             \
 153         }
 154
 155 #define MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\
 156                         _mux_clr_ofs, _shift, _width, _gate,            \
 157                         _upd_ofs, _upd, _flags) {                       \
 158                 .id = _id,                                              \
 159                 .mux_reg = _mux_ofs,                                    \
 160                 .mux_set_reg = _mux_set_ofs,                    \
 161                 .mux_clr_reg = _mux_clr_ofs,                    \
 162                 .upd_reg = _upd_ofs,                                    \
 163                 .upd_shift = _upd,                                      \
 164                 .mux_shift = _shift,                                    \
 165                 .mux_mask = BIT(_width) - 1,                            \
 166                 .gate_reg = _mux_ofs,                                   \
 167                 .gate_shift = _gate,                                    \
 168                 .parent = _parents,                                     \
 169                 .num_parents = ARRAY_SIZE(_parents),                    \
 170                 .flags = _flags,                                        \
 171         }
 172
 173 struct mtk_gate_regs {
 174         u32 sta_ofs;
 175         u32 clr_ofs;
 176         u32 set_ofs;
 177 };
 178
 179 /**
 180  * struct mtk_gate - gate clocks
 181  *
 182  * @id:         index of gate clocks
 183  * @parent:     index of parnet clocks
 184  * @regs:       hardware-specific mux register
 185  * @shift:      shift to the gate bit field
 186  * @flags:      hardware-specific flags
 187  */
 188 struct mtk_gate {
 189         const int id;
 190         const int parent;
 191         const struct mtk_gate_regs *regs;
 192         int shift;
 193         u32 flags;
 194 };
 195
 196 /* struct mtk_clk_tree - clock tree */
 197 struct mtk_clk_tree {
 198         unsigned long xtal_rate;
 199         unsigned long xtal2_rate;
 200         const int fdivs_offs;
 201         const int muxes_offs;
 202         const struct mtk_pll_data *plls;
 203         const struct mtk_fixed_clk *fclks;
 204         const struct mtk_fixed_factor *fdivs;
 205         const struct mtk_composite *muxes;
 206         u32 flags;
 207 };
 208
 209 struct mtk_clk_priv {
 210         struct udevice *parent;
 211         void __iomem *base;
 212         const struct mtk_clk_tree *tree;
 213 };
 214
 215 struct mtk_cg_priv {
 216         struct udevice *parent;
 217         void __iomem *base;
 218         const struct mtk_clk_tree *tree;
 219         const struct mtk_gate *gates;
 220 };
 221
 222 extern const struct clk_ops mtk_clk_apmixedsys_ops;
 223 extern const struct clk_ops mtk_clk_topckgen_ops;
 224 extern const struct clk_ops mtk_clk_infrasys_ops;
 225 extern const struct clk_ops mtk_clk_gate_ops;
 226
 227 int mtk_common_clk_init(struct udevice *dev,
 228                         const struct mtk_clk_tree *tree);
 229 int mtk_common_clk_gate_init(struct udevice *dev,
 230                              const struct mtk_clk_tree *tree,
 231                              const struct mtk_gate *gates);
 232
 233 #endif /* __DRV_CLK_MTK_H */