drivers/clk/mediatek/clk-mtk.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2014 MediaTek Inc.
   4  * Author: James Liao <jamesjj.liao@mediatek.com>
   5  */
   6
   7 #ifndef __DRV_CLK_MTK_H
   8 #define __DRV_CLK_MTK_H
   9
  10 #include <linux/regmap.h>
  11 #include <linux/bitops.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/platform_device.h>
  14
  15 struct clk;
  16 struct clk_onecell_data;
  17
  18 #define MAX_MUX_GATE_BIT        31
  19 #define INVALID_MUX_GATE_BIT    (MAX_MUX_GATE_BIT + 1)
  20
  21 #define MHZ (1000 * 1000)
  22
  23 struct mtk_fixed_clk {
  24         int id;
  25         const char *name;
  26         const char *parent;
  27         unsigned long rate;
  28 };
  29
  30 #define FIXED_CLK(_id, _name, _parent, _rate) {         \
  31                 .id = _id,                              \
  32                 .name = _name,                          \
  33                 .parent = _parent,                      \
  34                 .rate = _rate,                          \
  35         }
  36
  37 void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
  38                 int num, struct clk_onecell_data *clk_data);
  39
  40 struct mtk_fixed_factor {
  41         int id;
  42         const char *name;
  43         const char *parent_name;
  44         int mult;
  45         int div;
  46 };
  47
  48 #define FACTOR(_id, _name, _parent, _mult, _div) {      \
  49                 .id = _id,                              \
  50                 .name = _name,                          \
  51                 .parent_name = _parent,                 \
  52                 .mult = _mult,                          \
  53                 .div = _div,                            \
  54         }
  55
  56 void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
  57                 int num, struct clk_onecell_data *clk_data);
  58
  59 struct mtk_composite {
  60         int id;
  61         const char *name;
  62         const char * const *parent_names;
  63         const char *parent;
  64         unsigned flags;
  65
  66         uint32_t mux_reg;
  67         uint32_t divider_reg;
  68         uint32_t gate_reg;
  69
  70         signed char mux_shift;
  71         signed char mux_width;
  72         signed char gate_shift;
  73
  74         signed char divider_shift;
  75         signed char divider_width;
  76
  77         u8 mux_flags;
  78
  79         signed char num_parents;
  80 };
  81
  82 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift,            \
  83                                 _width, _gate, _flags, _muxflags) {     \
  84                 .id = _id,                                              \
  85                 .name = _name,                                          \
  86                 .mux_reg = _reg,                                        \
  87                 .mux_shift = _shift,                                    \
  88                 .mux_width = _width,                                    \
  89                 .gate_reg = _reg,                                       \
  90                 .gate_shift = _gate,                                    \
  91                 .divider_shift = -1,                                    \
  92                 .parent_names = _parents,                               \
  93                 .num_parents = ARRAY_SIZE(_parents),                    \
  94                 .flags = _flags,                                        \
  95                 .mux_flags = _muxflags,                                 \
  96         }
  97
  98 /*
  99  * In case the rate change propagation to parent clocks is undesirable,
 100  * this macro allows to specify the clock flags manually.
 101  */
 102 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width,      \
 103                         _gate, _flags)                                  \
 104                 MUX_GATE_FLAGS_2(_id, _name, _parents, _reg,            \
 105                                         _shift, _width, _gate, _flags, 0)
 106
 107 /*
 108  * Unless necessary, all MUX_GATE clocks propagate rate changes to their
 109  * parent clock by default.
 110  */
 111 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate)     \
 112         MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width,      \
 113                 _gate, CLK_SET_RATE_PARENT)
 114
 115 #define MUX(_id, _name, _parents, _reg, _shift, _width)                 \
 116         MUX_FLAGS(_id, _name, _parents, _reg,                           \
 117                   _shift, _width, CLK_SET_RATE_PARENT)
 118
 119 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \
 120                 .id = _id,                                              \
 121                 .name = _name,                                          \
 122                 .mux_reg = _reg,                                        \
 123                 .mux_shift = _shift,                                    \
 124                 .mux_width = _width,                                    \
 125                 .gate_shift = -1,                                       \
 126                 .divider_shift = -1,                                    \
 127                 .parent_names = _parents,                               \
 128                 .num_parents = ARRAY_SIZE(_parents),                    \
 129                 .flags = _flags,                                \
 130         }
 131
 132 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
 133                                         _div_width, _div_shift) {       \
 134                 .id = _id,                                              \
 135                 .parent = _parent,                                      \
 136                 .name = _name,                                          \
 137                 .divider_reg = _div_reg,                                \
 138                 .divider_shift = _div_shift,                            \
 139                 .divider_width = _div_width,                            \
 140                 .gate_reg = _gate_reg,                                  \
 141                 .gate_shift = _gate_shift,                              \
 142                 .mux_shift = -1,                                        \
 143                 .flags = 0,                                             \
 144         }
 145
 146 struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
 147                 void __iomem *base, spinlock_t *lock);
 148
 149 void mtk_clk_register_composites(const struct mtk_composite *mcs,
 150                 int num, void __iomem *base, spinlock_t *lock,
 151                 struct clk_onecell_data *clk_data);
 152
 153 struct mtk_gate_regs {
 154         u32 sta_ofs;
 155         u32 clr_ofs;
 156         u32 set_ofs;
 157 };
 158
 159 struct mtk_gate {
 160         int id;
 161         const char *name;
 162         const char *parent_name;
 163         const struct mtk_gate_regs *regs;
 164         int shift;
 165         const struct clk_ops *ops;
 166         unsigned long flags;
 167 };
 168
 169 int mtk_clk_register_gates(struct device_node *node,
 170                         const struct mtk_gate *clks, int num,
 171                         struct clk_onecell_data *clk_data);
 172
 173 int mtk_clk_register_gates_with_dev(struct device_node *node,
 174                 const struct mtk_gate *clks,
 175                 int num, struct clk_onecell_data *clk_data,
 176                 struct device *dev);
 177
 178 struct mtk_clk_divider {
 179         int id;
 180         const char *name;
 181         const char *parent_name;
 182         unsigned long flags;
 183
 184         u32 div_reg;
 185         unsigned char div_shift;
 186         unsigned char div_width;
 187         unsigned char clk_divider_flags;
 188         const struct clk_div_table *clk_div_table;
 189 };
 190
 191 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) {    \
 192                 .id = _id,                                      \
 193                 .name = _name,                                  \
 194                 .parent_name = _parent,                         \
 195                 .div_reg = _reg,                                \
 196                 .div_shift = _shift,                            \
 197                 .div_width = _width,                            \
 198 }
 199
 200 void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
 201                         int num, void __iomem *base, spinlock_t *lock,
 202                                 struct clk_onecell_data *clk_data);
 203
 204 struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
 205
 206 #define HAVE_RST_BAR    BIT(0)
 207 #define PLL_AO          BIT(1)
 208
 209 struct mtk_pll_div_table {
 210         u32 div;
 211         unsigned long freq;
 212 };
 213
 214 struct mtk_pll_data {
 215         int id;
 216         const char *name;
 217         u32 reg;
 218         u32 pwr_reg;
 219         u32 en_mask;
 220         u32 pd_reg;
 221         u32 tuner_reg;
 222         u32 tuner_en_reg;
 223         u8 tuner_en_bit;
 224         int pd_shift;
 225         unsigned int flags;
 226         const struct clk_ops *ops;
 227         u32 rst_bar_mask;
 228         unsigned long fmin;
 229         unsigned long fmax;
 230         int pcwbits;
 231         int pcwibits;
 232         u32 pcw_reg;
 233         int pcw_shift;
 234         u32 pcw_chg_reg;
 235         const struct mtk_pll_div_table *div_table;
 236         const char *parent_name;
 237         u32 en_reg;
 238         u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
 239 };
 240
 241 void mtk_clk_register_plls(struct device_node *node,
 242                 const struct mtk_pll_data *plls, int num_plls,
 243                 struct clk_onecell_data *clk_data);
 244
 245 struct clk *mtk_clk_register_ref2usb_tx(const char *name,
 246                         const char *parent_name, void __iomem *reg);
 247
 248 void mtk_register_reset_controller(struct device_node *np,
 249                         unsigned int num_regs, int regofs);
 250
 251 void mtk_register_reset_controller_set_clr(struct device_node *np,
 252         unsigned int num_regs, int regofs);
 253
 254 struct mtk_clk_desc {
 255         const struct mtk_gate *clks;
 256         size_t num_clks;
 257 };
 258
 259 int mtk_clk_simple_probe(struct platform_device *pdev);
 260
 261 #endif /* __DRV_CLK_MTK_H */