drivers/clk/mediatek/clk-mtk.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MediaTek common clock driver
   4  *
   5  * Copyright (C) 2018 MediaTek Inc.
   6  * Author: Ryder Lee <ryder.lee@mediatek.com>
   7  */
   8
   9 #include <common.h>
  10 #include <clk-uclass.h>
  11 #include <div64.h>
  12 #include <dm.h>
  13 #include <asm/io.h>
  14 #include <linux/bitops.h>
  15 #include <linux/delay.h>
  16
  17 #include "clk-mtk.h"
  18
  19 #define REG_CON0                        0
  20 #define REG_CON1                        4
  21
  22 #define CON0_BASE_EN                    BIT(0)
  23 #define CON0_PWR_ON                     BIT(0)
  24 #define CON0_ISO_EN                     BIT(1)
  25 #define CON1_PCW_CHG                    BIT(31)
  26
  27 #define POSTDIV_MASK                    0x7
  28 #define INTEGER_BITS                    7
  29
  30 /* scpsys clock off control */
  31 #define CLK_SCP_CFG0                    0x200
  32 #define CLK_SCP_CFG1                    0x204
  33 #define SCP_ARMCK_OFF_EN                GENMASK(9, 0)
  34 #define SCP_AXICK_DCM_DIS_EN            BIT(0)
  35 #define SCP_AXICK_26M_SEL_EN            BIT(4)
  36
  37 /* shared functions */
  38
  39 /*
  40  * In case the rate change propagation to parent clocks is undesirable,
  41  * this function is recursively called to find the parent to calculate
  42  * the accurate frequency.
  43  */
  44 static ulong mtk_clk_find_parent_rate(struct clk *clk, int id,
  45                                       struct udevice *pdev)
  46 {
  47         struct clk parent = { .id = id, };
  48
  49         if (pdev)
  50                 parent.dev = pdev;
  51         else
  52                 parent.dev = clk->dev;
  53
  54         return clk_get_rate(&parent);
  55 }
  56
  57 static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent,
  58                                   const struct mtk_composite *mux)
  59 {
  60         u32 val, index = 0;
  61
  62         while (mux->parent[index] != parent)
  63                 if (++index == mux->num_parents)
  64                         return -EINVAL;
  65
  66         if (mux->flags & CLK_MUX_SETCLR_UPD) {
  67                 val = (mux->mux_mask << mux->mux_shift);
  68                 writel(val, base + mux->mux_clr_reg);
  69
  70                 val = (index << mux->mux_shift);
  71                 writel(val, base + mux->mux_set_reg);
  72
  73                 if (mux->upd_shift >= 0)
  74                         writel(BIT(mux->upd_shift), base + mux->upd_reg);
  75         } else {
  76                 /* switch mux to a select parent */
  77                 val = readl(base + mux->mux_reg);
  78                 val &= ~(mux->mux_mask << mux->mux_shift);
  79
  80                 val |= index << mux->mux_shift;
  81                 writel(val, base + mux->mux_reg);
  82         }
  83
  84         return 0;
  85 }
  86
  87 /* apmixedsys functions */
  88
  89 static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll,
  90                                            u32 fin, u32 pcw, int postdiv)
  91 {
  92         int pcwbits = pll->pcwbits;
  93         int pcwfbits;
  94         int ibits;
  95         u64 vco;
  96         u8 c = 0;
  97
  98         /* The fractional part of the PLL divider. */
  99         ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
 100         pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0;
 101
 102         vco = (u64)fin * pcw;
 103
 104         if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
 105                 c = 1;
 106
 107         vco >>= pcwfbits;
 108
 109         if (c)
 110                 vco++;
 111
 112         return ((unsigned long)vco + postdiv - 1) / postdiv;
 113 }
 114
 115 /**
 116  * MediaTek PLLs are configured through their pcw value. The pcw value
 117  * describes a divider in the PLL feedback loop which consists of 7 bits
 118  * for the integer part and the remaining bits (if present) for the
 119  * fractional part. Also they have a 3 bit power-of-two post divider.
 120  */
 121 static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv)
 122 {
 123         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
 124         const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
 125         u32 val, chg;
 126
 127         /* set postdiv */
 128         val = readl(priv->base + pll->pd_reg);
 129         val &= ~(POSTDIV_MASK << pll->pd_shift);
 130         val |= (ffs(postdiv) - 1) << pll->pd_shift;
 131
 132         /* postdiv and pcw need to set at the same time if on same register */
 133         if (pll->pd_reg != pll->pcw_reg) {
 134                 writel(val, priv->base + pll->pd_reg);
 135                 val = readl(priv->base + pll->pcw_reg);
 136         }
 137
 138         /* set pcw */
 139         val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);
 140         val |= pcw << pll->pcw_shift;
 141
 142         if (pll->pcw_chg_reg) {
 143                 chg = readl(priv->base + pll->pcw_chg_reg);
 144                 chg |= CON1_PCW_CHG;
 145                 writel(val, priv->base + pll->pcw_reg);
 146                 writel(chg, priv->base + pll->pcw_chg_reg);
 147         } else {
 148                 val |= CON1_PCW_CHG;
 149                 writel(val, priv->base + pll->pcw_reg);
 150         }
 151
 152         udelay(20);
 153 }
 154
 155 /**
 156  * mtk_pll_calc_values - calculate good values for a given input frequency.
 157  * @clk:        The clk
 158  * @pcw:        The pcw value (output)
 159  * @postdiv:    The post divider (output)
 160  * @freq:       The desired target frequency
 161  */
 162 static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv,
 163                                 u32 freq)
 164 {
 165         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
 166         const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
 167         unsigned long fmin = pll->fmin ? pll->fmin : 1000 * MHZ;
 168         u64 _pcw;
 169         int ibits;
 170         u32 val;
 171
 172         if (freq > pll->fmax)
 173                 freq = pll->fmax;
 174
 175         for (val = 0; val < 5; val++) {
 176                 *postdiv = 1 << val;
 177                 if ((u64)freq * *postdiv >= fmin)
 178                         break;
 179         }
 180
 181         /* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */
 182         ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
 183         _pcw = ((u64)freq << val) << (pll->pcwbits - ibits);
 184         do_div(_pcw, priv->tree->xtal2_rate);
 185
 186         *pcw = (u32)_pcw;
 187 }
 188
 189 static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate)
 190 {
 191         u32 pcw = 0;
 192         u32 postdiv;
 193
 194         mtk_pll_calc_values(clk, &pcw, &postdiv, rate);
 195         mtk_pll_set_rate_regs(clk, pcw, postdiv);
 196
 197         return 0;
 198 }
 199
 200 static ulong mtk_apmixedsys_get_rate(struct clk *clk)
 201 {
 202         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
 203         const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
 204         u32 postdiv;
 205         u32 pcw;
 206
 207         postdiv = (readl(priv->base + pll->pd_reg) >> pll->pd_shift) &
 208                    POSTDIV_MASK;
 209         postdiv = 1 << postdiv;
 210
 211         pcw = readl(priv->base + pll->pcw_reg) >> pll->pcw_shift;
 212         pcw &= GENMASK(pll->pcwbits - 1, 0);
 213
 214         return __mtk_pll_recalc_rate(pll, priv->tree->xtal2_rate,
 215                                      pcw, postdiv);
 216 }
 217
 218 static int mtk_apmixedsys_enable(struct clk *clk)
 219 {
 220         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
 221         const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
 222         u32 r;
 223
 224         r = readl(priv->base + pll->pwr_reg) | CON0_PWR_ON;
 225         writel(r, priv->base + pll->pwr_reg);
 226         udelay(1);
 227
 228         r = readl(priv->base + pll->pwr_reg) & ~CON0_ISO_EN;
 229         writel(r, priv->base + pll->pwr_reg);
 230         udelay(1);
 231
 232         r = readl(priv->base + pll->reg + REG_CON0);
 233         r |= pll->en_mask;
 234         writel(r, priv->base + pll->reg + REG_CON0);
 235
 236         udelay(20);
 237
 238         if (pll->flags & HAVE_RST_BAR) {
 239                 r = readl(priv->base + pll->reg + REG_CON0);
 240                 r |= pll->rst_bar_mask;
 241                 writel(r, priv->base + pll->reg + REG_CON0);
 242         }
 243
 244         return 0;
 245 }
 246
 247 static int mtk_apmixedsys_disable(struct clk *clk)
 248 {
 249         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
 250         const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
 251         u32 r;
 252
 253         if (pll->flags & HAVE_RST_BAR) {
 254                 r = readl(priv->base + pll->reg + REG_CON0);
 255                 r &= ~pll->rst_bar_mask;
 256                 writel(r, priv->base + pll->reg + REG_CON0);
 257         }
 258
 259         r = readl(priv->base + pll->reg + REG_CON0);
 260         r &= ~CON0_BASE_EN;
 261         writel(r, priv->base + pll->reg + REG_CON0);
 262
 263         r = readl(priv->base + pll->pwr_reg) | CON0_ISO_EN;
 264         writel(r, priv->base + pll->pwr_reg);
 265
 266         r = readl(priv->base + pll->pwr_reg) & ~CON0_PWR_ON;
 267         writel(r, priv->base + pll->pwr_reg);
 268
 269         return 0;
 270 }
 271
 272 /* topckgen functions */
 273
 274 static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv,
 275                                     ulong parent_rate)
 276 {
 277         u64 rate = parent_rate * fdiv->mult;
 278
 279         do_div(rate, fdiv->div);
 280
 281         return rate;
 282 }
 283
 284 static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
 285 {
 286         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
 287         const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off];
 288         ulong rate;
 289
 290         switch (fdiv->flags & CLK_PARENT_MASK) {
 291         case CLK_PARENT_APMIXED:
 292                 rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
 293                                                 priv->parent);
 294                 break;
 295         case CLK_PARENT_TOPCKGEN:
 296                 rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
 297                 break;
 298
 299         default:
 300                 rate = priv->tree->xtal_rate;
 301         }
 302
 303         return mtk_factor_recalc_rate(fdiv, rate);
 304 }
 305
 306 static ulong mtk_infrasys_get_factor_rate(struct clk *clk, u32 off)
 307 {
 308         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
 309         const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off];
 310         ulong rate;
 311
 312         switch (fdiv->flags & CLK_PARENT_MASK) {
 313         case CLK_PARENT_TOPCKGEN:
 314                 rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
 315                                                 priv->parent);
 316                 break;
 317         default:
 318                 rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
 319         }
 320
 321         return mtk_factor_recalc_rate(fdiv, rate);
 322 }
 323
 324 static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
 325 {
 326         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
 327         const struct mtk_composite *mux = &priv->tree->muxes[off];
 328         u32 index;
 329
 330         index = readl(priv->base + mux->mux_reg);
 331         index &= mux->mux_mask << mux->mux_shift;
 332         index = index >> mux->mux_shift;
 333
 334         if (mux->parent[index] > 0 ||
 335             (mux->parent[index] == CLK_XTAL &&
 336              priv->tree->flags & CLK_BYPASS_XTAL)) {
 337                 switch (mux->flags & CLK_PARENT_MASK) {
 338                 case CLK_PARENT_APMIXED:
 339                         return mtk_clk_find_parent_rate(clk, mux->parent[index],
 340                                                         priv->parent);
 341                         break;
 342                 default:
 343                         return mtk_clk_find_parent_rate(clk, mux->parent[index],
 344                                                         NULL);
 345                         break;
 346                 }
 347         }
 348
 349         return priv->tree->xtal_rate;
 350 }
 351
 352 static ulong mtk_infrasys_get_mux_rate(struct clk *clk, u32 off)
 353 {
 354         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
 355         const struct mtk_composite *mux = &priv->tree->muxes[off];
 356         u32 index;
 357
 358         index = readl(priv->base + mux->mux_reg);
 359         index &= mux->mux_mask << mux->mux_shift;
 360         index = index >> mux->mux_shift;
 361
 362         if (mux->parent[index] > 0 ||
 363             (mux->parent[index] == CLK_XTAL &&
 364              priv->tree->flags & CLK_BYPASS_XTAL)) {
 365                 switch (mux->flags & CLK_PARENT_MASK) {
 366                 case CLK_PARENT_TOPCKGEN:
 367                         return mtk_clk_find_parent_rate(clk, mux->parent[index],
 368                                                         priv->parent);
 369                         break;
 370                 default:
 371                         return mtk_clk_find_parent_rate(clk, mux->parent[index],
 372                                                         NULL);
 373                         break;
 374                 }
 375         }
 376         return 0;
 377 }
 378
 379 static ulong mtk_topckgen_get_rate(struct clk *clk)
 380 {
 381         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
 382
 383         if (clk->id < priv->tree->fdivs_offs)
 384                 return priv->tree->fclks[clk->id].rate;
 385         else if (clk->id < priv->tree->muxes_offs)
 386                 return mtk_topckgen_get_factor_rate(clk, clk->id -
 387                                                     priv->tree->fdivs_offs);
 388         else
 389                 return mtk_topckgen_get_mux_rate(clk, clk->id -
 390                                                  priv->tree->muxes_offs);
 391 }
 392
 393 static ulong mtk_infrasys_get_rate(struct clk *clk)
 394 {
 395         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
 396
 397         ulong rate;
 398
 399         if (clk->id < priv->tree->fdivs_offs) {
 400                 rate = priv->tree->fclks[clk->id].rate;
 401         } else if (clk->id < priv->tree->muxes_offs) {
 402                 rate = mtk_infrasys_get_factor_rate(clk, clk->id -
 403                                                     priv->tree->fdivs_offs);
 404         } else {
 405                 rate = mtk_infrasys_get_mux_rate(clk, clk->id -
 406                                                  priv->tree->muxes_offs);
 407         }
 408
 409         return rate;
 410 }
 411
 412 static int mtk_clk_mux_enable(struct clk *clk)
 413 {
 414         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
 415         const struct mtk_composite *mux;
 416         u32 val;
 417
 418         if (clk->id < priv->tree->muxes_offs)
 419                 return 0;
 420
 421         mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs];
 422         if (mux->gate_shift < 0)
 423                 return 0;
 424
 425         /* enable clock gate */
 426         if (mux->flags & CLK_MUX_SETCLR_UPD) {
 427                 val = BIT(mux->gate_shift);
 428                 writel(val, priv->base + mux->mux_clr_reg);
 429         } else {
 430                 val = readl(priv->base + mux->gate_reg);
 431                 val &= ~BIT(mux->gate_shift);
 432                 writel(val, priv->base + mux->gate_reg);
 433         }
 434
 435         if (mux->flags & CLK_DOMAIN_SCPSYS) {
 436                 /* enable scpsys clock off control */
 437                 writel(SCP_ARMCK_OFF_EN, priv->base + CLK_SCP_CFG0);
 438                 writel(SCP_AXICK_DCM_DIS_EN | SCP_AXICK_26M_SEL_EN,
 439                        priv->base + CLK_SCP_CFG1);
 440         }
 441
 442         return 0;
 443 }
 444
 445 static int mtk_clk_mux_disable(struct clk *clk)
 446 {
 447         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
 448         const struct mtk_composite *mux;
 449         u32 val;
 450
 451         if (clk->id < priv->tree->muxes_offs)
 452                 return 0;
 453
 454         mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs];
 455         if (mux->gate_shift < 0)
 456                 return 0;
 457
 458         /* disable clock gate */
 459         if (mux->flags & CLK_MUX_SETCLR_UPD) {
 460                 val = BIT(mux->gate_shift);
 461                 writel(val, priv->base + mux->mux_set_reg);
 462         } else {
 463                 val = readl(priv->base + mux->gate_reg);
 464                 val |= BIT(mux->gate_shift);
 465                 writel(val, priv->base + mux->gate_reg);
 466         }
 467
 468         return 0;
 469 }
 470
 471 static int mtk_common_clk_set_parent(struct clk *clk, struct clk *parent)
 472 {
 473         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
 474
 475         if (clk->id < priv->tree->muxes_offs)
 476                 return 0;
 477
 478         return mtk_clk_mux_set_parent(priv->base, parent->id,
 479                         &priv->tree->muxes[clk->id - priv->tree->muxes_offs]);
 480 }
 481
 482 /* CG functions */
 483
 484 static int mtk_clk_gate_enable(struct clk *clk)
 485 {
 486         struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
 487         const struct mtk_gate *gate = &priv->gates[clk->id];
 488         u32 bit = BIT(gate->shift);
 489
 490         switch (gate->flags & CLK_GATE_MASK) {
 491         case CLK_GATE_SETCLR:
 492                 writel(bit, priv->base + gate->regs->clr_ofs);
 493                 break;
 494         case CLK_GATE_SETCLR_INV:
 495                 writel(bit, priv->base + gate->regs->set_ofs);
 496                 break;
 497         case CLK_GATE_NO_SETCLR:
 498                 clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0);
 499                 break;
 500         case CLK_GATE_NO_SETCLR_INV:
 501                 clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
 502                 break;
 503
 504         default:
 505                 return -EINVAL;
 506         }
 507
 508         return 0;
 509 }
 510
 511 static int mtk_clk_gate_disable(struct clk *clk)
 512 {
 513         struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
 514         const struct mtk_gate *gate = &priv->gates[clk->id];
 515         u32 bit = BIT(gate->shift);
 516
 517         switch (gate->flags & CLK_GATE_MASK) {
 518         case CLK_GATE_SETCLR:
 519                 writel(bit, priv->base + gate->regs->set_ofs);
 520                 break;
 521         case CLK_GATE_SETCLR_INV:
 522                 writel(bit, priv->base + gate->regs->clr_ofs);
 523                 break;
 524         case CLK_GATE_NO_SETCLR:
 525                 clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
 526                 break;
 527         case CLK_GATE_NO_SETCLR_INV:
 528                 clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0);
 529                 break;
 530
 531         default:
 532                 return -EINVAL;
 533         }
 534
 535         return 0;
 536 }
 537
 538 static ulong mtk_clk_gate_get_rate(struct clk *clk)
 539 {
 540         struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
 541         const struct mtk_gate *gate = &priv->gates[clk->id];
 542
 543         return mtk_clk_find_parent_rate(clk, gate->parent, priv->parent);
 544 }
 545
 546 const struct clk_ops mtk_clk_apmixedsys_ops = {
 547         .enable = mtk_apmixedsys_enable,
 548         .disable = mtk_apmixedsys_disable,
 549         .set_rate = mtk_apmixedsys_set_rate,
 550         .get_rate = mtk_apmixedsys_get_rate,
 551 };
 552
 553 const struct clk_ops mtk_clk_topckgen_ops = {
 554         .enable = mtk_clk_mux_enable,
 555         .disable = mtk_clk_mux_disable,
 556         .get_rate = mtk_topckgen_get_rate,
 557         .set_parent = mtk_common_clk_set_parent,
 558 };
 559
 560 const struct clk_ops mtk_clk_infrasys_ops = {
 561         .enable = mtk_clk_mux_enable,
 562         .disable = mtk_clk_mux_disable,
 563         .get_rate = mtk_infrasys_get_rate,
 564         .set_parent = mtk_common_clk_set_parent,
 565 };
 566
 567 const struct clk_ops mtk_clk_gate_ops = {
 568         .enable = mtk_clk_gate_enable,
 569         .disable = mtk_clk_gate_disable,
 570         .get_rate = mtk_clk_gate_get_rate,
 571 };
 572
 573 int mtk_common_clk_init(struct udevice *dev,
 574                         const struct mtk_clk_tree *tree)
 575 {
 576         struct mtk_clk_priv *priv = dev_get_priv(dev);
 577         struct udevice *parent;
 578         int ret;
 579
 580         priv->base = dev_read_addr_ptr(dev);
 581         if (!priv->base)
 582                 return -ENOENT;
 583
 584         ret = uclass_get_device_by_phandle(UCLASS_CLK, dev, "clock-parent", &parent);
 585         if (ret || !parent) {
 586                 ret = uclass_get_device_by_driver(UCLASS_CLK,
 587                                 DM_DRIVER_GET(mtk_clk_apmixedsys), &parent);
 588                 if (ret || !parent)
 589                         return -ENOENT;
 590         }
 591
 592         priv->parent = parent;
 593         priv->tree = tree;
 594
 595         return 0;
 596 }
 597
 598 int mtk_common_clk_gate_init(struct udevice *dev,
 599                              const struct mtk_clk_tree *tree,
 600                              const struct mtk_gate *gates)
 601 {
 602         struct mtk_cg_priv *priv = dev_get_priv(dev);
 603         struct udevice *parent;
 604         int ret;
 605
 606         priv->base = dev_read_addr_ptr(dev);
 607         if (!priv->base)
 608                 return -ENOENT;
 609
 610         ret = uclass_get_device_by_phandle(UCLASS_CLK, dev, "clock-parent", &parent);
 611         if (ret || !parent) {
 612                 ret = uclass_get_device_by_driver(UCLASS_CLK,
 613                                 DM_DRIVER_GET(mtk_clk_topckgen), &parent);
 614                 if (ret || !parent)
 615                         return -ENOENT;
 616         }
 617
 618         priv->parent = parent;
 619         priv->tree = tree;
 620         priv->gates = gates;
 621
 622         return 0;
 623 }