drivers/clk/mediatek/clk-mt8516.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MediaTek clock driver for MT8516 SoC
   4  *
   5  * Copyright (C) 2018 BayLibre, SAS
   6  * Author: Fabien Parent <fparent@baylibre.com>
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <asm/io.h>
  12 #include <dt-bindings/clock/mt8516-clk.h>
  13 #include <linux/bitops.h>
  14
  15 #include "clk-mtk.h"
  16
  17 #define MT8516_PLL_FMAX         (1502UL * MHZ)
  18 #define MT8516_CON0_RST_BAR     BIT(27)
  19
  20 /* apmixedsys */
  21 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,   \
  22             _pd_shift, _pcw_reg, _pcw_shift) {                          \
  23                 .id = _id,                                              \
  24                 .reg = _reg,                                            \
  25                 .pwr_reg = _pwr_reg,                                    \
  26                 .en_mask = _en_mask,                                    \
  27                 .rst_bar_mask = MT8516_CON0_RST_BAR,                    \
  28                 .fmax = MT8516_PLL_FMAX,                                \
  29                 .flags = _flags,                                        \
  30                 .pcwbits = _pcwbits,                                    \
  31                 .pd_reg = _pd_reg,                                      \
  32                 .pd_shift = _pd_shift,                                  \
  33                 .pcw_reg = _pcw_reg,                                    \
  34                 .pcw_shift = _pcw_shift,                                \
  35         }
  36
  37 static const struct mtk_pll_data apmixed_plls[] = {
  38         PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 0,
  39                 21, 0x0104, 24, 0x0104, 0),
  40         PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
  41                 HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
  42         PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
  43                 HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
  44         PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 0,
  45                 21, 0x0164, 24, 0x0164, 0),
  46         PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, 0,
  47                 31, 0x0180, 1, 0x0184, 0),
  48         PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001, 0,
  49                 31, 0x01A0, 1, 0x01A4, 0),
  50 };
  51
  52 /* topckgen */
  53 #define FACTOR0(_id, _parent, _mult, _div)      \
  54         FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
  55
  56 #define FACTOR1(_id, _parent, _mult, _div)      \
  57         FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
  58
  59 #define FACTOR2(_id, _parent, _mult, _div)      \
  60         FACTOR(_id, _parent, _mult, _div, 0)
  61
  62 static const struct mtk_fixed_clk top_fixed_clks[] = {
  63         FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
  64         FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, CLK_TOP_CLK_NULL, 26000000),
  65         FIXED_CLK(CLK_TOP_MEMPLL, CLK_TOP_CLK26M, 800000000),
  66 };
  67
  68 static const struct mtk_fixed_factor top_fixed_divs[] = {
  69         FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
  70         FACTOR0(CLK_TOP_MAINPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
  71         FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
  72         FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
  73         FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
  74         FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
  75         FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
  76         FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
  77         FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
  78         FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
  79         FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
  80         FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
  81         FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
  82         FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
  83         FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
  84         FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
  85         FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
  86         FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4),
  87         FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8),
  88         FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16),
  89         FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
  90         FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6),
  91         FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12),
  92         FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24),
  93         FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
  94         FACTOR0(CLK_TOP_UNIVPLL_D20, CLK_APMIXED_UNIVPLL, 1, 20),
  95         FACTOR0(CLK_TOP_MMPLL380M, CLK_APMIXED_MMPLL, 1, 1),
  96         FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
  97         FACTOR0(CLK_TOP_MMPLL_200M, CLK_APMIXED_MMPLL, 1, 3),
  98         FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26),
  99         FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
 100         FACTOR1(CLK_TOP_APLL1_D2, CLK_TOP_APLL1, 1, 2),
 101         FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_RG_APLL1_D2_EN, 1, 2),
 102         FACTOR1(CLK_TOP_APLL1_D8, CLK_TOP_RG_APLL1_D4_EN, 1, 2),
 103         FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
 104         FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
 105         FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_RG_APLL2_D2_EN, 1, 2),
 106         FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_RG_APLL2_D4_EN, 1, 2),
 107         FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
 108         FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2),
 109         FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AHB_INFRA_SEL, 1, 2),
 110         FACTOR1(CLK_TOP_NFI1X, CLK_TOP_NFI2X_PAD_SEL, 1, 2),
 111         FACTOR1(CLK_TOP_ETH_D2, CLK_TOP_ETH_SEL, 1, 2),
 112 };
 113
 114 static const int uart0_parents[] = {
 115         CLK_TOP_CLK26M,
 116         CLK_TOP_UNIVPLL_D24,
 117 };
 118
 119 static const int gfmux_emi1x_parents[] = {
 120         CLK_TOP_CLK26M,
 121         CLK_TOP_DMPLL,
 122 };
 123
 124 static const int emi_ddrphy_parents[] = {
 125         CLK_TOP_GFMUX_EMI1X_SEL,
 126         CLK_TOP_GFMUX_EMI1X_SEL,
 127 };
 128
 129 static const int ahb_infra_parents[] = {
 130         CLK_TOP_CLK_NULL,
 131         CLK_TOP_CLK26M,
 132         CLK_TOP_MAINPLL_D11,
 133         CLK_TOP_CLK_NULL,
 134         CLK_TOP_MAINPLL_D12,
 135         CLK_TOP_CLK_NULL,
 136         CLK_TOP_CLK_NULL,
 137         CLK_TOP_CLK_NULL,
 138         CLK_TOP_CLK_NULL,
 139         CLK_TOP_CLK_NULL,
 140         CLK_TOP_CLK_NULL,
 141         CLK_TOP_CLK_NULL,
 142         CLK_TOP_MAINPLL_D10,
 143 };
 144
 145 static const int csw_mux_mfg_parents[] = {
 146         CLK_TOP_CLK_NULL,
 147         CLK_TOP_CLK_NULL,
 148         CLK_TOP_UNIVPLL_D3,
 149         CLK_TOP_UNIVPLL_D2,
 150         CLK_TOP_CLK26M,
 151         CLK_TOP_MAINPLL_D4,
 152         CLK_TOP_UNIVPLL_D24,
 153         CLK_TOP_MMPLL380M,
 154 };
 155
 156 static const int msdc0_parents[] = {
 157         CLK_TOP_CLK26M,
 158         CLK_TOP_UNIVPLL_D6,
 159         CLK_TOP_MAINPLL_D8,
 160         CLK_TOP_UNIVPLL_D8,
 161         CLK_TOP_MAINPLL_D16,
 162         CLK_TOP_MMPLL_200M,
 163         CLK_TOP_MAINPLL_D12,
 164         CLK_TOP_MMPLL_D2,
 165 };
 166
 167 static const int pwm_mm_parents[] = {
 168         CLK_TOP_CLK26M,
 169         CLK_TOP_UNIVPLL_D12,
 170 };
 171
 172 static const int uart1_parents[] = {
 173         CLK_TOP_CLK26M,
 174         CLK_TOP_UNIVPLL_D24,
 175 };
 176
 177 static const int msdc1_parents[] = {
 178         CLK_TOP_CLK26M,
 179         CLK_TOP_UNIVPLL_D6,
 180         CLK_TOP_MAINPLL_D8,
 181         CLK_TOP_UNIVPLL_D8,
 182         CLK_TOP_MAINPLL_D16,
 183         CLK_TOP_MMPLL_200M,
 184         CLK_TOP_MAINPLL_D12,
 185         CLK_TOP_MMPLL_D2,
 186 };
 187
 188 static const int spm_52m_parents[] = {
 189         CLK_TOP_CLK26M,
 190         CLK_TOP_UNIVPLL_D24,
 191 };
 192
 193 static const int pmicspi_parents[] = {
 194         CLK_TOP_UNIVPLL_D20,
 195         CLK_TOP_USB_PHY48M,
 196         CLK_TOP_UNIVPLL_D16,
 197         CLK_TOP_CLK26M,
 198 };
 199
 200 static const int qaxi_aud26m_parents[] = {
 201         CLK_TOP_CLK26M,
 202         CLK_TOP_AHB_INFRA_SEL,
 203 };
 204
 205 static const int aud_intbus_parents[] = {
 206         CLK_TOP_CLK_NULL,
 207         CLK_TOP_CLK26M,
 208         CLK_TOP_MAINPLL_D22,
 209         CLK_TOP_CLK_NULL,
 210         CLK_TOP_MAINPLL_D11,
 211 };
 212
 213 static const int nfi2x_pad_parents[] = {
 214         CLK_TOP_CLK_NULL,
 215         CLK_TOP_CLK_NULL,
 216         CLK_TOP_CLK_NULL,
 217         CLK_TOP_CLK_NULL,
 218         CLK_TOP_CLK_NULL,
 219         CLK_TOP_CLK_NULL,
 220         CLK_TOP_CLK_NULL,
 221         CLK_TOP_CLK_NULL,
 222         CLK_TOP_CLK26M,
 223         CLK_TOP_CLK_NULL,
 224         CLK_TOP_CLK_NULL,
 225         CLK_TOP_CLK_NULL,
 226         CLK_TOP_CLK_NULL,
 227         CLK_TOP_CLK_NULL,
 228         CLK_TOP_CLK_NULL,
 229         CLK_TOP_CLK_NULL,
 230         CLK_TOP_CLK_NULL,
 231         CLK_TOP_MAINPLL_D12,
 232         CLK_TOP_MAINPLL_D8,
 233         CLK_TOP_CLK_NULL,
 234         CLK_TOP_MAINPLL_D6,
 235         CLK_TOP_CLK_NULL,
 236         CLK_TOP_CLK_NULL,
 237         CLK_TOP_CLK_NULL,
 238         CLK_TOP_CLK_NULL,
 239         CLK_TOP_CLK_NULL,
 240         CLK_TOP_CLK_NULL,
 241         CLK_TOP_CLK_NULL,
 242         CLK_TOP_CLK_NULL,
 243         CLK_TOP_CLK_NULL,
 244         CLK_TOP_CLK_NULL,
 245         CLK_TOP_CLK_NULL,
 246         CLK_TOP_MAINPLL_D4,
 247         CLK_TOP_CLK_NULL,
 248         CLK_TOP_CLK_NULL,
 249         CLK_TOP_CLK_NULL,
 250         CLK_TOP_CLK_NULL,
 251         CLK_TOP_CLK_NULL,
 252         CLK_TOP_CLK_NULL,
 253         CLK_TOP_CLK_NULL,
 254         CLK_TOP_CLK_NULL,
 255         CLK_TOP_CLK_NULL,
 256         CLK_TOP_CLK_NULL,
 257         CLK_TOP_CLK_NULL,
 258         CLK_TOP_CLK_NULL,
 259         CLK_TOP_CLK_NULL,
 260         CLK_TOP_CLK_NULL,
 261         CLK_TOP_CLK_NULL,
 262         CLK_TOP_CLK_NULL,
 263         CLK_TOP_CLK_NULL,
 264         CLK_TOP_CLK_NULL,
 265         CLK_TOP_CLK_NULL,
 266         CLK_TOP_CLK_NULL,
 267         CLK_TOP_CLK_NULL,
 268         CLK_TOP_CLK_NULL,
 269         CLK_TOP_CLK_NULL,
 270         CLK_TOP_CLK_NULL,
 271         CLK_TOP_CLK_NULL,
 272         CLK_TOP_CLK_NULL,
 273         CLK_TOP_CLK_NULL,
 274         CLK_TOP_CLK_NULL,
 275         CLK_TOP_CLK_NULL,
 276         CLK_TOP_CLK_NULL,
 277         CLK_TOP_CLK_NULL,
 278         CLK_TOP_CLK_NULL,
 279         CLK_TOP_CLK_NULL,
 280         CLK_TOP_CLK_NULL,
 281         CLK_TOP_CLK_NULL,
 282         CLK_TOP_CLK_NULL,
 283         CLK_TOP_CLK_NULL,
 284         CLK_TOP_CLK_NULL,
 285         CLK_TOP_CLK_NULL,
 286         CLK_TOP_CLK_NULL,
 287         CLK_TOP_CLK_NULL,
 288         CLK_TOP_CLK_NULL,
 289         CLK_TOP_CLK_NULL,
 290         CLK_TOP_CLK_NULL,
 291         CLK_TOP_CLK_NULL,
 292         CLK_TOP_CLK_NULL,
 293         CLK_TOP_CLK_NULL,
 294         CLK_TOP_CLK_NULL,
 295         CLK_TOP_MAINPLL_D10,
 296         CLK_TOP_MAINPLL_D7,
 297         CLK_TOP_CLK_NULL,
 298         CLK_TOP_MAINPLL_D5
 299 };
 300
 301 static const int nfi1x_pad_parents[] = {
 302         CLK_TOP_AHB_INFRA_SEL,
 303         CLK_TOP_NFI1X,
 304 };
 305
 306 static const int mfg_mm_parents[] = {
 307         CLK_TOP_CLK_NULL,
 308         CLK_TOP_CLK_NULL,
 309         CLK_TOP_CLK_NULL,
 310         CLK_TOP_CLK_NULL,
 311         CLK_TOP_CLK_NULL,
 312         CLK_TOP_CLK_NULL,
 313         CLK_TOP_CLK_NULL,
 314         CLK_TOP_CLK_NULL,
 315         CLK_TOP_CSW_MUX_MFG_SEL,
 316         CLK_TOP_CLK_NULL,
 317         CLK_TOP_CLK_NULL,
 318         CLK_TOP_CLK_NULL,
 319         CLK_TOP_CLK_NULL,
 320         CLK_TOP_CLK_NULL,
 321         CLK_TOP_CLK_NULL,
 322         CLK_TOP_CLK_NULL,
 323         CLK_TOP_MAINPLL_D3,
 324         CLK_TOP_CLK_NULL,
 325         CLK_TOP_CLK_NULL,
 326         CLK_TOP_CLK_NULL,
 327         CLK_TOP_CLK_NULL,
 328         CLK_TOP_CLK_NULL,
 329         CLK_TOP_CLK_NULL,
 330         CLK_TOP_CLK_NULL,
 331         CLK_TOP_CLK_NULL,
 332         CLK_TOP_CLK_NULL,
 333         CLK_TOP_CLK_NULL,
 334         CLK_TOP_CLK_NULL,
 335         CLK_TOP_CLK_NULL,
 336         CLK_TOP_CLK_NULL,
 337         CLK_TOP_CLK_NULL,
 338         CLK_TOP_CLK_NULL,
 339         CLK_TOP_CLK_NULL,
 340         CLK_TOP_MAINPLL_D5,
 341         CLK_TOP_MAINPLL_D7,
 342         CLK_TOP_CLK_NULL,
 343         CLK_TOP_MAINPLL_D14
 344 };
 345
 346 static const int ddrphycfg_parents[] = {
 347         CLK_TOP_CLK26M,
 348         CLK_TOP_MAINPLL_D16
 349 };
 350
 351 static const int usb_78m_parents[] = {
 352         CLK_TOP_CLK_NULL,
 353         CLK_TOP_CLK26M,
 354         CLK_TOP_UNIVPLL_D16,
 355         CLK_TOP_CLK_NULL,
 356         CLK_TOP_MAINPLL_D20,
 357 };
 358
 359 static const int spinor_parents[] = {
 360         CLK_TOP_CLK26M_D2,
 361         CLK_TOP_CLK26M,
 362         CLK_TOP_MAINPLL_D40,
 363         CLK_TOP_UNIVPLL_D24,
 364         CLK_TOP_UNIVPLL_D20,
 365         CLK_TOP_MAINPLL_D20,
 366         CLK_TOP_MAINPLL_D16,
 367         CLK_TOP_UNIVPLL_D12
 368 };
 369
 370 static const int msdc2_parents[] = {
 371         CLK_TOP_CLK26M,
 372         CLK_TOP_UNIVPLL_D6,
 373         CLK_TOP_MAINPLL_D8,
 374         CLK_TOP_UNIVPLL_D8,
 375         CLK_TOP_MAINPLL_D16,
 376         CLK_TOP_MMPLL_200M,
 377         CLK_TOP_MAINPLL_D12,
 378         CLK_TOP_MMPLL_D2
 379 };
 380
 381 static const int eth_parents[] = {
 382         CLK_TOP_CLK26M,
 383         CLK_TOP_MAINPLL_D40,
 384         CLK_TOP_UNIVPLL_D24,
 385         CLK_TOP_UNIVPLL_D20,
 386         CLK_TOP_MAINPLL_D20
 387 };
 388
 389 static const int axi_mfg_in_parents[] = {
 390         CLK_TOP_CLK26M,
 391         CLK_TOP_MAINPLL_D11,
 392         CLK_TOP_UNIVPLL_D24,
 393         CLK_TOP_MMPLL380M,
 394 };
 395
 396 static const int slow_mfg_parents[] = {
 397         CLK_TOP_CLK26M,
 398         CLK_TOP_UNIVPLL_D12,
 399         CLK_TOP_UNIVPLL_D24
 400 };
 401
 402 static const int aud1_parents[] = {
 403         CLK_TOP_CLK26M,
 404         CLK_TOP_APLL1
 405 };
 406
 407 static const int aud2_parents[] = {
 408         CLK_TOP_CLK26M,
 409         CLK_TOP_APLL2
 410 };
 411
 412 static const int aud_engen1_parents[] = {
 413         CLK_TOP_CLK26M,
 414         CLK_TOP_RG_APLL1_D2_EN,
 415         CLK_TOP_RG_APLL1_D4_EN,
 416         CLK_TOP_RG_APLL1_D8_EN
 417 };
 418
 419 static const int aud_engen2_parents[] = {
 420         CLK_TOP_CLK26M,
 421         CLK_TOP_RG_APLL2_D2_EN,
 422         CLK_TOP_RG_APLL2_D4_EN,
 423         CLK_TOP_RG_APLL2_D8_EN
 424 };
 425
 426 static const int i2c_parents[] = {
 427         CLK_TOP_CLK26M,
 428         CLK_TOP_UNIVPLL_D20,
 429         CLK_TOP_UNIVPLL_D16,
 430         CLK_TOP_UNIVPLL_D12
 431 };
 432
 433 static const int aud_i2s0_m_parents[] = {
 434         CLK_TOP_RG_AUD1,
 435         CLK_TOP_RG_AUD2
 436 };
 437
 438 static const int pwm_parents[] = {
 439         CLK_TOP_CLK26M,
 440         CLK_TOP_UNIVPLL_D12
 441 };
 442
 443 static const int spi_parents[] = {
 444         CLK_TOP_CLK26M,
 445         CLK_TOP_UNIVPLL_D12,
 446         CLK_TOP_UNIVPLL_D8,
 447         CLK_TOP_UNIVPLL_D6
 448 };
 449
 450 static const int aud_spdifin_parents[] = {
 451         CLK_TOP_CLK26M,
 452         CLK_TOP_UNIVPLL_D2
 453 };
 454
 455 static const int uart2_parents[] = {
 456         CLK_TOP_CLK26M,
 457         CLK_TOP_UNIVPLL_D24
 458 };
 459
 460 static const int bsi_parents[] = {
 461         CLK_TOP_CLK26M,
 462         CLK_TOP_MAINPLL_D10,
 463         CLK_TOP_MAINPLL_D12,
 464         CLK_TOP_MAINPLL_D20
 465 };
 466
 467 static const int dbg_atclk_parents[] = {
 468         CLK_TOP_CLK_NULL,
 469         CLK_TOP_CLK26M,
 470         CLK_TOP_MAINPLL_D5,
 471         CLK_TOP_CLK_NULL,
 472         CLK_TOP_UNIVPLL_D5
 473 };
 474
 475 static const int csw_nfiecc_parents[] = {
 476         CLK_TOP_CLK_NULL,
 477         CLK_TOP_MAINPLL_D7,
 478         CLK_TOP_MAINPLL_D6,
 479         CLK_TOP_CLK_NULL,
 480         CLK_TOP_MAINPLL_D5
 481 };
 482
 483 static const int nfiecc_parents[] = {
 484         CLK_TOP_CLK_NULL,
 485         CLK_TOP_NFI2X_PAD_SEL,
 486         CLK_TOP_MAINPLL_D4,
 487         CLK_TOP_CLK_NULL,
 488         CLK_TOP_CSW_NFIECC_SEL,
 489 };
 490
 491 static const struct mtk_composite top_muxes[] = {
 492         /* CLK_MUX_SEL0 */
 493         MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
 494         MUX(CLK_TOP_GFMUX_EMI1X_SEL, gfmux_emi1x_parents, 0x000, 1, 1),
 495         MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1),
 496         MUX(CLK_TOP_AHB_INFRA_SEL, ahb_infra_parents, 0x000, 4, 4),
 497         MUX(CLK_TOP_CSW_MUX_MFG_SEL, csw_mux_mfg_parents, 0x000, 8, 3),
 498         MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0x000, 11, 3),
 499         MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1),
 500         MUX(CLK_TOP_UART1_SEL, uart1_parents, 0x000, 19, 1),
 501         MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 20, 3),
 502         MUX(CLK_TOP_SPM_52M_SEL, spm_52m_parents, 0x000, 23, 1),
 503         MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 24, 2),
 504         MUX(CLK_TOP_QAXI_AUD26M_SEL, qaxi_aud26m_parents, 0x000, 26, 1),
 505         MUX(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x000, 27, 3),
 506         /* CLK_MUX_SEL1 */
 507         MUX(CLK_TOP_NFI2X_PAD_SEL, nfi2x_pad_parents, 0x004, 0, 7),
 508         MUX(CLK_TOP_NFI1X_PAD_SEL, nfi1x_pad_parents, 0x004, 7, 1),
 509         MUX(CLK_TOP_MFG_MM_SEL, mfg_mm_parents, 0x004, 8, 6),
 510         MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
 511         MUX(CLK_TOP_USB_78M_SEL, usb_78m_parents, 0x004, 20, 3),
 512         /* CLK_MUX_SEL8 */
 513         MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3),
 514         MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0x040, 3, 3),
 515         MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
 516         MUX(CLK_TOP_AXI_MFG_IN_SEL, axi_mfg_in_parents, 0x040, 18, 2),
 517         MUX(CLK_TOP_SLOW_MFG_SEL, slow_mfg_parents, 0x040, 20, 2),
 518         MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
 519         MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
 520         MUX(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x040, 24, 2),
 521         MUX(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x040, 26, 2),
 522         MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 2),
 523         /* CLK_MUX_SEL9 */
 524         MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1),
 525         MUX(CLK_TOP_AUD_I2S1_M_SEL, aud_i2s0_m_parents, 0x044, 13, 1),
 526         MUX(CLK_TOP_AUD_I2S2_M_SEL, aud_i2s0_m_parents, 0x044, 14, 1),
 527         MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1),
 528         MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1),
 529         MUX(CLK_TOP_AUD_I2S5_M_SEL, aud_i2s0_m_parents, 0x044, 17, 1),
 530         MUX(CLK_TOP_AUD_SPDIF_B_SEL, aud_i2s0_m_parents, 0x044, 18, 1),
 531         /* CLK_MUX_SEL13 */
 532         MUX(CLK_TOP_PWM_SEL, pwm_parents, 0x07c, 0, 1),
 533         MUX(CLK_TOP_SPI_SEL, spi_parents, 0x07c, 1, 2),
 534         MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 3, 1),
 535         MUX(CLK_TOP_UART2_SEL, uart2_parents, 0x07c, 4, 1),
 536         MUX(CLK_TOP_BSI_SEL, bsi_parents, 0x07c, 5, 2),
 537         MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3),
 538         MUX(CLK_TOP_CSW_NFIECC_SEL, csw_nfiecc_parents, 0x07c, 10, 3),
 539         MUX(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x07c, 13, 3),
 540 };
 541
 542 static const struct mtk_gate_regs top0_cg_regs = {
 543         .set_ofs = 0x50,
 544         .clr_ofs = 0x80,
 545         .sta_ofs = 0x20,
 546 };
 547
 548 static const struct mtk_gate_regs top1_cg_regs = {
 549         .set_ofs = 0x54,
 550         .clr_ofs = 0x84,
 551         .sta_ofs = 0x24,
 552 };
 553
 554 static const struct mtk_gate_regs top2_cg_regs = {
 555         .set_ofs = 0x6c,
 556         .clr_ofs = 0x9c,
 557         .sta_ofs = 0x3c,
 558 };
 559
 560 static const struct mtk_gate_regs top3_cg_regs = {
 561         .set_ofs = 0xa0,
 562         .clr_ofs = 0xb0,
 563         .sta_ofs = 0x70,
 564 };
 565
 566 static const struct mtk_gate_regs top4_cg_regs = {
 567         .set_ofs = 0xa4,
 568         .clr_ofs = 0xb4,
 569         .sta_ofs = 0x74,
 570 };
 571
 572 static const struct mtk_gate_regs top5_cg_regs = {
 573         .set_ofs = 0x44,
 574         .clr_ofs = 0x44,
 575         .sta_ofs = 0x44,
 576 };
 577
 578 #define GATE_TOP0(_id, _parent, _shift) {                       \
 579                 .id = _id,                                      \
 580                 .parent = _parent,                              \
 581                 .regs = &top0_cg_regs,                          \
 582                 .shift = _shift,                                \
 583                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
 584         }
 585
 586 #define GATE_TOP1(_id, _parent, _shift) {                       \
 587                 .id = _id,                                      \
 588                 .parent = _parent,                              \
 589                 .regs = &top1_cg_regs,                          \
 590                 .shift = _shift,                                \
 591                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
 592         }
 593
 594 #define GATE_TOP2(_id, _parent, _shift) {                       \
 595                 .id = _id,                                      \
 596                 .parent = _parent,                              \
 597                 .regs = &top2_cg_regs,                          \
 598                 .shift = _shift,                                \
 599                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
 600         }
 601
 602 #define GATE_TOP2_I(_id, _parent, _shift) {                             \
 603                 .id = _id,                                              \
 604                 .parent = _parent,                                      \
 605                 .regs = &top2_cg_regs,                                  \
 606                 .shift = _shift,                                        \
 607                 .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN,     \
 608         }
 609
 610 #define GATE_TOP3(_id, _parent, _shift) {                       \
 611                 .id = _id,                                      \
 612                 .parent = _parent,                              \
 613                 .regs = &top3_cg_regs,                          \
 614                 .shift = _shift,                                \
 615                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
 616         }
 617
 618 #define GATE_TOP4_I(_id, _parent, _shift) {                             \
 619                 .id = _id,                                              \
 620                 .parent = _parent,                                      \
 621                 .regs = &top4_cg_regs,                                  \
 622                 .shift = _shift,                                        \
 623                 .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN,     \
 624         }
 625
 626 #define GATE_TOP5(_id, _parent, _shift) {                               \
 627                 .id = _id,                                              \
 628                 .parent = _parent,                                      \
 629                 .regs = &top5_cg_regs,                                  \
 630                 .shift = _shift,                                        \
 631                 .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN,      \
 632         }
 633
 634 static const struct mtk_gate top_clks[] = {
 635         /* TOP0 */
 636         GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
 637         GATE_TOP0(CLK_TOP_MFG_MM, CLK_TOP_MFG_MM_SEL, 2),
 638         GATE_TOP0(CLK_TOP_SPM_52M, CLK_TOP_SPM_52M_SEL, 3),
 639         /* TOP1 */
 640         GATE_TOP1(CLK_TOP_THEM, CLK_TOP_AHB_INFRA_SEL, 1),
 641         GATE_TOP1(CLK_TOP_APDMA, CLK_TOP_AHB_INFRA_SEL, 2),
 642         GATE_TOP1(CLK_TOP_I2C0, CLK_IFR_I2C0_SEL, 3),
 643         GATE_TOP1(CLK_TOP_I2C1, CLK_IFR_I2C1_SEL, 4),
 644         GATE_TOP1(CLK_TOP_AUXADC1, CLK_TOP_AHB_INFRA_SEL, 5),
 645         GATE_TOP1(CLK_TOP_NFI, CLK_TOP_NFI1X_PAD_SEL, 6),
 646         GATE_TOP1(CLK_TOP_NFIECC, CLK_TOP_RG_NFIECC, 7),
 647         GATE_TOP1(CLK_TOP_DEBUGSYS, CLK_TOP_RG_DBG_ATCLK, 8),
 648         GATE_TOP1(CLK_TOP_PWM, CLK_TOP_AHB_INFRA_SEL, 9),
 649         GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
 650         GATE_TOP1(CLK_TOP_UART1, CLK_TOP_UART1_SEL, 11),
 651         GATE_TOP1(CLK_TOP_BTIF, CLK_TOP_AHB_INFRA_SEL, 12),
 652         GATE_TOP1(CLK_TOP_USB, CLK_TOP_USB_78M, 13),
 653         GATE_TOP1(CLK_TOP_FLASHIF_26M, CLK_TOP_CLK26M, 14),
 654         GATE_TOP1(CLK_TOP_AUXADC2, CLK_TOP_AHB_INFRA_SEL, 15),
 655         GATE_TOP1(CLK_TOP_I2C2, CLK_IFR_I2C2_SEL, 16),
 656         GATE_TOP1(CLK_TOP_MSDC0, CLK_TOP_MSDC0_SEL, 17),
 657         GATE_TOP1(CLK_TOP_MSDC1, CLK_TOP_MSDC1_SEL, 18),
 658         GATE_TOP1(CLK_TOP_NFI2X, CLK_TOP_NFI2X_PAD_SEL, 19),
 659         GATE_TOP1(CLK_TOP_PMICWRAP_AP, CLK_TOP_CLK26M, 20),
 660         GATE_TOP1(CLK_TOP_SEJ, CLK_TOP_AHB_INFRA_SEL, 21),
 661         GATE_TOP1(CLK_TOP_MEMSLP_DLYER, CLK_TOP_CLK26M, 22),
 662         GATE_TOP1(CLK_TOP_SPI, CLK_TOP_SPI_SEL, 23),
 663         GATE_TOP1(CLK_TOP_APXGPT, CLK_TOP_CLK26M, 24),
 664         GATE_TOP1(CLK_TOP_AUDIO, CLK_TOP_CLK26M, 25),
 665         GATE_TOP1(CLK_TOP_PMICWRAP_MD, CLK_TOP_CLK26M, 27),
 666         GATE_TOP1(CLK_TOP_PMICWRAP_CONN, CLK_TOP_CLK26M, 28),
 667         GATE_TOP1(CLK_TOP_PMICWRAP_26M, CLK_TOP_CLK26M, 29),
 668         GATE_TOP1(CLK_TOP_AUX_ADC, CLK_TOP_CLK26M, 30),
 669         GATE_TOP1(CLK_TOP_AUX_TP, CLK_TOP_CLK26M, 31),
 670         /* TOP2 */
 671         GATE_TOP2(CLK_TOP_MSDC2, CLK_TOP_AHB_INFRA_SEL, 0),
 672         GATE_TOP2(CLK_TOP_RBIST, CLK_TOP_UNIVPLL_D12, 1),
 673         GATE_TOP2(CLK_TOP_NFI_BUS, CLK_TOP_AHB_INFRA_SEL, 2),
 674         GATE_TOP2(CLK_TOP_GCE, CLK_TOP_AHB_INFRA_SEL, 4),
 675         GATE_TOP2(CLK_TOP_TRNG, CLK_TOP_AHB_INFRA_SEL, 5),
 676         GATE_TOP2(CLK_TOP_SEJ_13M, CLK_TOP_CLK26M, 6),
 677         GATE_TOP2(CLK_TOP_AES, CLK_TOP_AHB_INFRA_SEL, 7),
 678         GATE_TOP2(CLK_TOP_PWM_B, CLK_TOP_RG_PWM_INFRA, 8),
 679         GATE_TOP2(CLK_TOP_PWM1_FB, CLK_TOP_RG_PWM_INFRA, 9),
 680         GATE_TOP2(CLK_TOP_PWM2_FB, CLK_TOP_RG_PWM_INFRA, 10),
 681         GATE_TOP2(CLK_TOP_PWM3_FB, CLK_TOP_RG_PWM_INFRA, 11),
 682         GATE_TOP2(CLK_TOP_PWM4_FB, CLK_TOP_RG_PWM_INFRA, 12),
 683         GATE_TOP2(CLK_TOP_PWM5_FB, CLK_TOP_RG_PWM_INFRA, 13),
 684         GATE_TOP2(CLK_TOP_USB_1P, CLK_TOP_USB_78M, 14),
 685         GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, CLK_TOP_AHB_INFRA_SEL, 15),
 686         GATE_TOP2(CLK_TOP_66M_ETH, CLK_TOP_AHB_INFRA_D2, 19),
 687         GATE_TOP2(CLK_TOP_133M_ETH, CLK_TOP_AHB_INFRA_SEL, 20),
 688         GATE_TOP2(CLK_TOP_FETH_25M, CLK_IFR_ETH_25M_SEL, 21),
 689         GATE_TOP2(CLK_TOP_FETH_50M, CLK_TOP_RG_ETH, 22),
 690         GATE_TOP2(CLK_TOP_FLASHIF_AXI, CLK_TOP_AHB_INFRA_SEL, 23),
 691         GATE_TOP2(CLK_TOP_USBIF, CLK_TOP_AHB_INFRA_SEL, 24),
 692         GATE_TOP2(CLK_TOP_UART2, CLK_TOP_RG_UART2, 25),
 693         GATE_TOP2(CLK_TOP_BSI, CLK_TOP_AHB_INFRA_SEL, 26),
 694         GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, CLK_TOP_MSDC0, 28),
 695         GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, CLK_TOP_MSDC1, 29),
 696         GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, CLK_TOP_RG_MSDC2, 30),
 697         GATE_TOP2(CLK_TOP_USB_78M, CLK_TOP_USB_78M_SEL, 31),
 698         /* TOP3 */
 699         GATE_TOP3(CLK_TOP_RG_SPINOR, CLK_TOP_SPINOR_SEL, 0),
 700         GATE_TOP3(CLK_TOP_RG_MSDC2, CLK_TOP_MSDC2_SEL, 1),
 701         GATE_TOP3(CLK_TOP_RG_ETH, CLK_TOP_ETH_SEL, 2),
 702         GATE_TOP3(CLK_TOP_RG_AXI_MFG, CLK_TOP_AXI_MFG_IN_SEL, 6),
 703         GATE_TOP3(CLK_TOP_RG_SLOW_MFG, CLK_TOP_SLOW_MFG_SEL, 7),
 704         GATE_TOP3(CLK_TOP_RG_AUD1, CLK_TOP_AUD1_SEL, 8),
 705         GATE_TOP3(CLK_TOP_RG_AUD2, CLK_TOP_AUD2_SEL, 9),
 706         GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, CLK_TOP_AUD_ENGEN1_SEL, 10),
 707         GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, CLK_TOP_AUD_ENGEN2_SEL, 11),
 708         GATE_TOP3(CLK_TOP_RG_I2C, CLK_TOP_I2C_SEL, 12),
 709         GATE_TOP3(CLK_TOP_RG_PWM_INFRA, CLK_TOP_PWM_SEL, 13),
 710         GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, CLK_TOP_AUD_SPDIFIN_SEL, 14),
 711         GATE_TOP3(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
 712         GATE_TOP3(CLK_TOP_RG_BSI, CLK_TOP_BSI_SEL, 16),
 713         GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, CLK_TOP_DBG_ATCLK_SEL, 17),
 714         GATE_TOP3(CLK_TOP_RG_NFIECC, CLK_TOP_NFIECC_SEL, 18),
 715         /* TOP4 */
 716         GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, CLK_TOP_APLL1_D2, 8),
 717         GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, CLK_TOP_APLL1_D4, 9),
 718         GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, CLK_TOP_APLL1_D8, 10),
 719         GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, CLK_TOP_APLL2_D2, 11),
 720         GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, CLK_TOP_APLL2_D4, 12),
 721         GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, CLK_TOP_APLL2_D8, 13),
 722         /* TOP5 */
 723         GATE_TOP5(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
 724         GATE_TOP5(CLK_TOP_APLL12_DIV1, CLK_TOP_APLL12_CK_DIV1, 1),
 725         GATE_TOP5(CLK_TOP_APLL12_DIV2, CLK_TOP_APLL12_CK_DIV2, 2),
 726         GATE_TOP5(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3),
 727         GATE_TOP5(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4),
 728         GATE_TOP5(CLK_TOP_APLL12_DIV4B, CLK_TOP_APLL12_CK_DIV4B, 5),
 729         GATE_TOP5(CLK_TOP_APLL12_DIV5, CLK_TOP_APLL12_CK_DIV5, 6),
 730         GATE_TOP5(CLK_TOP_APLL12_DIV5B, CLK_TOP_APLL12_CK_DIV5B, 7),
 731         GATE_TOP5(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
 732 };
 733
 734 static const struct mtk_clk_tree mt8516_clk_tree = {
 735         .xtal_rate = 26 * MHZ,
 736         .xtal2_rate = 26 * MHZ,
 737         .fdivs_offs = CLK_TOP_DMPLL,
 738         .muxes_offs = CLK_TOP_UART0_SEL,
 739         .plls = apmixed_plls,
 740         .fclks = top_fixed_clks,
 741         .fdivs = top_fixed_divs,
 742         .muxes = top_muxes,
 743 };
 744
 745 static int mt8516_apmixedsys_probe(struct udevice *dev)
 746 {
 747         return mtk_common_clk_init(dev, &mt8516_clk_tree);
 748 }
 749
 750 static int mt8516_topckgen_probe(struct udevice *dev)
 751 {
 752         return mtk_common_clk_init(dev, &mt8516_clk_tree);
 753 }
 754
 755 static int mt8516_topckgen_cg_probe(struct udevice *dev)
 756 {
 757         return mtk_common_clk_gate_init(dev, &mt8516_clk_tree, top_clks);
 758 }
 759
 760 static const struct udevice_id mt8516_apmixed_compat[] = {
 761         { .compatible = "mediatek,mt8516-apmixedsys", },
 762         { }
 763 };
 764
 765 static const struct udevice_id mt8516_topckgen_compat[] = {
 766         { .compatible = "mediatek,mt8516-topckgen", },
 767         { }
 768 };
 769
 770 static const struct udevice_id mt8516_topckgen_cg_compat[] = {
 771         { .compatible = "mediatek,mt8516-topckgen-cg", },
 772         { }
 773 };
 774
 775 U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
 776         .name = "mt8516-apmixedsys",
 777         .id = UCLASS_CLK,
 778         .of_match = mt8516_apmixed_compat,
 779         .probe = mt8516_apmixedsys_probe,
 780         .priv_auto      = sizeof(struct mtk_clk_priv),
 781         .ops = &mtk_clk_apmixedsys_ops,
 782         .flags = DM_FLAG_PRE_RELOC,
 783 };
 784
 785 U_BOOT_DRIVER(mtk_clk_topckgen) = {
 786         .name = "mt8516-topckgen",
 787         .id = UCLASS_CLK,
 788         .of_match = mt8516_topckgen_compat,
 789         .probe = mt8516_topckgen_probe,
 790         .priv_auto      = sizeof(struct mtk_clk_priv),
 791         .ops = &mtk_clk_topckgen_ops,
 792         .flags = DM_FLAG_PRE_RELOC,
 793 };
 794
 795 U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
 796         .name = "mt8516-topckgen-cg",
 797         .id = UCLASS_CLK,
 798         .of_match = mt8516_topckgen_cg_compat,
 799         .probe = mt8516_topckgen_cg_probe,
 800         .priv_auto      = sizeof(struct mtk_cg_priv),
 801         .ops = &mtk_clk_gate_ops,
 802         .flags = DM_FLAG_PRE_RELOC,
 803 };