1 // SPDX-License-Identifier: GPL-2.0-only
3 // Copyright (c) 2021 MediaTek Inc.
4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
6 #include <linux/clk-provider.h>
7 #include <linux/of_device.h>
8 #include <linux/platform_device.h>
13 #include <dt-bindings/clock/mt8192-clk.h>
15 static const struct mtk_gate_regs ipe_cg_regs = {
21 #define GATE_IPE(_id, _name, _parent, _shift) \
22 GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
24 static const struct mtk_gate ipe_clks[] = {
25 GATE_IPE(CLK_IPE_LARB19, "ipe_larb19", "ipe_sel", 0),
26 GATE_IPE(CLK_IPE_LARB20, "ipe_larb20", "ipe_sel", 1),
27 GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "ipe_sel", 2),
28 GATE_IPE(CLK_IPE_FD, "ipe_fd", "ipe_sel", 3),
29 GATE_IPE(CLK_IPE_FE, "ipe_fe", "ipe_sel", 4),
30 GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "ipe_sel", 5),
31 GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "ipe_sel", 6),
32 GATE_IPE(CLK_IPE_GALS, "ipe_gals", "ipe_sel", 8),
35 static const struct mtk_clk_desc ipe_desc = {
37 .num_clks = ARRAY_SIZE(ipe_clks),
40 static const struct of_device_id of_match_clk_mt8192_ipe[] = {
42 .compatible = "mediatek,mt8192-ipesys",
49 static struct platform_driver clk_mt8192_ipe_drv = {
50 .probe = mtk_clk_simple_probe,
52 .name = "clk-mt8192-ipe",
53 .of_match_table = of_match_clk_mt8192_ipe,
57 builtin_platform_driver(clk_mt8192_ipe_drv);