1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2018 MediaTek Inc.
4 // Author: Weiyi Lu <weiyi.lu@mediatek.com>
6 #include <linux/delay.h>
7 #include <linux/mfd/syscon.h>
9 #include <linux/of_address.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12 #include <linux/slab.h>
19 #include <dt-bindings/clock/mt8183-clk.h>
21 /* Infra global controller reset set register */
22 #define INFRA_RST0_SET_OFFSET 0x120
24 static DEFINE_SPINLOCK(mt8183_clk_lock);
26 static const struct mtk_fixed_clk top_fixed_clks[] = {
27 FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
28 FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000),
29 FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000),
32 static const struct mtk_fixed_factor top_early_divs[] = {
33 FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2),
36 static const struct mtk_fixed_factor top_divs[] = {
37 FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1,
39 FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1,
41 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
43 FACTOR(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1,
45 FACTOR(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1,
47 FACTOR(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1,
49 FACTOR(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1,
51 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1,
53 FACTOR(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1,
55 FACTOR(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1,
57 FACTOR(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1,
59 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1,
61 FACTOR(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1,
63 FACTOR(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1,
65 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1,
67 FACTOR(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1,
69 FACTOR(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1,
71 FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1,
73 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
75 FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1,
77 FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1,
79 FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1,
81 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1,
83 FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1,
85 FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1,
87 FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1,
89 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1,
91 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1,
93 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1,
95 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1,
97 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1,
99 FACTOR(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1,
101 FACTOR(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1,
103 FACTOR(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1,
105 FACTOR(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1,
107 FACTOR(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1,
109 FACTOR(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1,
111 FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1,
113 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1,
115 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1,
117 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1,
119 FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1,
121 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1,
123 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1,
125 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1,
127 FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1,
129 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
131 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1,
133 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1,
135 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1,
137 FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1,
139 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1,
141 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1,
143 FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1,
145 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1,
147 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1,
149 FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1,
151 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1,
153 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1,
155 FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1,
157 FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1,
159 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1,
161 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1,
163 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1,
165 FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1,
167 FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1,
169 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1,
171 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1,
173 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1,
175 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1,
177 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1,
179 FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1,
183 static const char * const axi_parents[] = {
190 static const char * const mm_parents[] = {
199 static const char * const img_parents[] = {
210 static const char * const cam_parents[] = {
223 static const char * const dsp_parents[] = {
235 static const char * const dsp1_parents[] = {
247 static const char * const dsp2_parents[] = {
259 static const char * const ipu_if_parents[] = {
271 static const char * const mfg_parents[] = {
278 static const char * const f52m_mfg_parents[] = {
285 static const char * const camtg_parents[] = {
296 static const char * const camtg2_parents[] = {
307 static const char * const camtg3_parents[] = {
318 static const char * const camtg4_parents[] = {
329 static const char * const uart_parents[] = {
334 static const char * const spi_parents[] = {
341 static const char * const msdc50_hclk_parents[] = {
347 static const char * const msdc50_0_parents[] = {
356 static const char * const msdc30_1_parents[] = {
364 static const char * const msdc30_2_parents[] = {
372 static const char * const audio_parents[] = {
379 static const char * const aud_intbus_parents[] = {
385 static const char * const pmicspi_parents[] = {
391 static const char * const fpwrap_ulposc_parents[] = {
398 static const char * const atb_parents[] = {
404 static const char * const dpi0_parents[] = {
416 static const char * const scam_parents[] = {
421 static const char * const disppwm_parents[] = {
429 static const char * const usb_top_parents[] = {
437 static const char * const ssusb_top_xhci_parents[] = {
444 static const char * const spm_parents[] = {
449 static const char * const i2c_parents[] = {
455 static const char * const scp_parents[] = {
465 static const char * const seninf_parents[] = {
472 static const char * const dxcc_parents[] = {
479 static const char * const aud_engen1_parents[] = {
486 static const char * const aud_engen2_parents[] = {
493 static const char * const faes_ufsfde_parents[] = {
502 static const char * const fufs_parents[] = {
509 static const char * const aud_1_parents[] = {
514 static const char * const aud_2_parents[] = {
521 * axi_sel is the main bus clock of whole SOC.
522 * spm_sel is the clock of the always-on co-processor.
524 static const struct mtk_mux top_muxes[] = {
526 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel",
528 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL),
529 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
531 0x44, 0x48, 8, 3, 15, 0x004, 1),
532 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
534 0x44, 0x48, 16, 3, 23, 0x004, 2),
535 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel",
537 0x44, 0x48, 24, 4, 31, 0x004, 3),
539 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel",
541 0x54, 0x58, 0, 4, 7, 0x004, 4),
542 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel",
544 0x54, 0x58, 8, 4, 15, 0x004, 5),
545 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel",
547 0x54, 0x58, 16, 4, 23, 0x004, 6),
548 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel",
549 ipu_if_parents, 0x50,
550 0x54, 0x58, 24, 4, 31, 0x004, 7),
552 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel",
554 0x64, 0x68, 0, 2, 7, 0x004, 8),
555 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel",
556 f52m_mfg_parents, 0x60,
557 0x64, 0x68, 8, 2, 15, 0x004, 9),
558 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel",
560 0x64, 0x68, 16, 3, 23, 0x004, 10),
561 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel",
562 camtg2_parents, 0x60,
563 0x64, 0x68, 24, 3, 31, 0x004, 11),
565 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel",
566 camtg3_parents, 0x70,
567 0x74, 0x78, 0, 3, 7, 0x004, 12),
568 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel",
569 camtg4_parents, 0x70,
570 0x74, 0x78, 8, 3, 15, 0x004, 13),
571 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel",
573 0x74, 0x78, 16, 1, 23, 0x004, 14),
574 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel",
576 0x74, 0x78, 24, 2, 31, 0x004, 15),
578 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel",
579 msdc50_hclk_parents, 0x80,
580 0x84, 0x88, 0, 2, 7, 0x004, 16),
581 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel",
582 msdc50_0_parents, 0x80,
583 0x84, 0x88, 8, 3, 15, 0x004, 17),
584 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel",
585 msdc30_1_parents, 0x80,
586 0x84, 0x88, 16, 3, 23, 0x004, 18),
587 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel",
588 msdc30_2_parents, 0x80,
589 0x84, 0x88, 24, 3, 31, 0x004, 19),
591 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel",
593 0x94, 0x98, 0, 2, 7, 0x004, 20),
594 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel",
595 aud_intbus_parents, 0x90,
596 0x94, 0x98, 8, 2, 15, 0x004, 21),
597 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel",
598 pmicspi_parents, 0x90,
599 0x94, 0x98, 16, 2, 23, 0x004, 22),
600 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
601 fpwrap_ulposc_parents, 0x90,
602 0x94, 0x98, 24, 2, 31, 0x004, 23),
604 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel",
606 0xa4, 0xa8, 0, 2, 7, 0x004, 24),
607 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel",
609 0xa4, 0xa8, 16, 4, 23, 0x004, 26),
610 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel",
612 0xa4, 0xa8, 24, 1, 31, 0x004, 27),
614 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel",
615 disppwm_parents, 0xb0,
616 0xb4, 0xb8, 0, 3, 7, 0x004, 28),
617 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel",
618 usb_top_parents, 0xb0,
619 0xb4, 0xb8, 8, 2, 15, 0x004, 29),
620 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
621 ssusb_top_xhci_parents, 0xb0,
622 0xb4, 0xb8, 16, 2, 23, 0x004, 30),
623 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel",
625 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL),
627 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel",
629 0xc4, 0xc8, 0, 2, 7, 0x008, 1),
630 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel",
632 0xc4, 0xc8, 8, 3, 15, 0x008, 2),
633 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel",
634 seninf_parents, 0xc0,
635 0xc4, 0xc8, 16, 2, 23, 0x008, 3),
636 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel",
638 0xc4, 0xc8, 24, 2, 31, 0x008, 4),
640 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel",
641 aud_engen1_parents, 0xd0,
642 0xd4, 0xd8, 0, 2, 7, 0x008, 5),
643 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel",
644 aud_engen2_parents, 0xd0,
645 0xd4, 0xd8, 8, 2, 15, 0x008, 6),
646 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel",
647 faes_ufsfde_parents, 0xd0,
648 0xd4, 0xd8, 16, 3, 23, 0x008, 7),
649 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel",
651 0xd4, 0xd8, 24, 2, 31, 0x008, 8),
653 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel",
655 0xe4, 0xe8, 0, 1, 7, 0x008, 9),
656 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel",
658 0xe4, 0xe8, 8, 1, 15, 0x008, 10),
661 static const char * const apll_i2s0_parents[] = {
666 static const char * const apll_i2s1_parents[] = {
671 static const char * const apll_i2s2_parents[] = {
676 static const char * const apll_i2s3_parents[] = {
681 static const char * const apll_i2s4_parents[] = {
686 static const char * const apll_i2s5_parents[] = {
691 static struct mtk_composite top_aud_muxes[] = {
692 MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents,
694 MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents,
696 MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents,
698 MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents,
700 MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents,
702 MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents,
706 static const char * const mcu_mp0_parents[] = {
713 static const char * const mcu_mp2_parents[] = {
720 static const char * const mcu_bus_parents[] = {
727 static struct mtk_composite mcu_muxes[] = {
728 /* mp0_pll_divider_cfg */
729 MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2),
730 /* mp2_pll_divider_cfg */
731 MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2),
732 /* bus_pll_divider_cfg */
733 MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2),
736 static struct mtk_composite top_aud_divs[] = {
737 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel",
738 0x320, 2, 0x324, 8, 0),
739 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel",
740 0x320, 3, 0x324, 8, 8),
741 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel",
742 0x320, 4, 0x324, 8, 16),
743 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel",
744 0x320, 5, 0x324, 8, 24),
745 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel",
746 0x320, 6, 0x328, 8, 0),
747 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4",
748 0x320, 7, 0x328, 8, 8),
751 static const struct mtk_gate_regs top_cg_regs = {
757 #define GATE_TOP(_id, _name, _parent, _shift) \
758 GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \
759 &mtk_clk_gate_ops_no_setclr_inv)
761 static const struct mtk_gate top_clks[] = {
763 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4),
764 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5),
767 static const struct mtk_gate_regs infra0_cg_regs = {
773 static const struct mtk_gate_regs infra1_cg_regs = {
779 static const struct mtk_gate_regs infra2_cg_regs = {
785 static const struct mtk_gate_regs infra3_cg_regs = {
791 #define GATE_INFRA0(_id, _name, _parent, _shift) \
792 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \
793 &mtk_clk_gate_ops_setclr)
795 #define GATE_INFRA1(_id, _name, _parent, _shift) \
796 GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \
797 &mtk_clk_gate_ops_setclr)
799 #define GATE_INFRA2(_id, _name, _parent, _shift) \
800 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \
801 &mtk_clk_gate_ops_setclr)
803 #define GATE_INFRA3(_id, _name, _parent, _shift) \
804 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \
805 &mtk_clk_gate_ops_setclr)
807 static const struct mtk_gate infra_clks[] = {
809 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr",
811 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap",
813 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md",
815 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn",
817 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp",
819 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej",
821 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt",
823 GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb",
825 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce",
827 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm",
829 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0",
831 GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1",
833 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2",
835 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3",
837 GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk",
839 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1",
841 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2",
843 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3",
845 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4",
847 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
849 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
851 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
853 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
855 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
857 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
859 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
861 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif",
864 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0",
866 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0",
867 "msdc50_hclk_sel", 2),
868 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1",
870 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2",
872 GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck",
874 GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc",
876 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu",
878 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng",
880 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc",
882 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum",
884 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap",
886 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md",
888 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md",
890 GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck",
892 GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck",
894 GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma",
896 GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu",
898 GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc",
900 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap",
902 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys",
904 GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio",
906 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md",
908 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core",
910 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao",
912 GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk",
914 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
917 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx",
919 GATE_INFRA2(CLK_INFRA_USB, "infra_usb",
921 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm",
923 GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk",
925 GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk",
927 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1",
929 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4",
931 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share",
933 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2",
935 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3",
937 GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck",
938 "ssusb_top_xhci_sel", 11),
939 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick",
941 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck",
943 GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
945 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
947 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
949 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
951 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm",
953 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter",
955 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm",
957 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter",
959 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm",
961 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4",
963 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5",
965 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma",
967 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs",
969 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde",
970 "faes_ufsfde_sel", 29),
971 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick",
974 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self",
976 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self",
978 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
980 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
982 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
984 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0",
985 "msdc50_hclk_sel", 7),
986 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0",
987 "msdc50_hclk_sel", 8),
988 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap",
990 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md",
992 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap",
994 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md",
996 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m",
998 GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk",
1000 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7",
1002 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8",
1004 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc",
1005 "msdc50_0_sel", 24),
1008 static const struct mtk_gate_regs peri_cg_regs = {
1014 #define GATE_PERI(_id, _name, _parent, _shift) \
1015 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \
1016 &mtk_clk_gate_ops_no_setclr_inv)
1018 static const struct mtk_gate peri_clks[] = {
1019 GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31),
1022 static const struct mtk_gate_regs apmixed_cg_regs = {
1028 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
1029 GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
1030 _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
1032 #define GATE_APMIXED(_id, _name, _parent, _shift) \
1033 GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
1037 * apmixed_appll26m is the toppest clock gate of all PLLs.
1039 static const struct mtk_gate apmixed_clks[] = {
1041 GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m",
1043 GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m",
1044 "f_f26m_ck", 5, CLK_IS_CRITICAL),
1045 GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m",
1047 GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m",
1049 GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m",
1051 GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m",
1053 GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m",
1055 GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m",
1057 GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
1059 GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m",
1061 GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m",
1065 #define MT8183_PLL_FMAX (3800UL * MHZ)
1066 #define MT8183_PLL_FMIN (1500UL * MHZ)
1068 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1069 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
1070 _pd_shift, _tuner_reg, _tuner_en_reg, \
1071 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1072 _pcw_chg_reg, _div_table) { \
1076 .pwr_reg = _pwr_reg, \
1077 .en_mask = _en_mask, \
1079 .rst_bar_mask = _rst_bar_mask, \
1080 .fmax = MT8183_PLL_FMAX, \
1081 .fmin = MT8183_PLL_FMIN, \
1082 .pcwbits = _pcwbits, \
1083 .pcwibits = _pcwibits, \
1084 .pd_reg = _pd_reg, \
1085 .pd_shift = _pd_shift, \
1086 .tuner_reg = _tuner_reg, \
1087 .tuner_en_reg = _tuner_en_reg, \
1088 .tuner_en_bit = _tuner_en_bit, \
1089 .pcw_reg = _pcw_reg, \
1090 .pcw_shift = _pcw_shift, \
1091 .pcw_chg_reg = _pcw_chg_reg, \
1092 .div_table = _div_table, \
1095 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1096 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
1097 _pd_shift, _tuner_reg, _tuner_en_reg, \
1098 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1100 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1101 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
1102 _pd_shift, _tuner_reg, _tuner_en_reg, \
1103 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1106 static const struct mtk_pll_div_table armpll_div_table[] = {
1107 { .div = 0, .freq = MT8183_PLL_FMAX },
1108 { .div = 1, .freq = 1500 * MHZ },
1109 { .div = 2, .freq = 750 * MHZ },
1110 { .div = 3, .freq = 375 * MHZ },
1111 { .div = 4, .freq = 187500000 },
1115 static const struct mtk_pll_div_table mfgpll_div_table[] = {
1116 { .div = 0, .freq = MT8183_PLL_FMAX },
1117 { .div = 1, .freq = 1600 * MHZ },
1118 { .div = 2, .freq = 800 * MHZ },
1119 { .div = 3, .freq = 400 * MHZ },
1120 { .div = 4, .freq = 200 * MHZ },
1124 static const struct mtk_pll_data plls[] = {
1125 PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0x00000001,
1126 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0,
1127 0x0204, 0, 0, armpll_div_table),
1128 PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0x00000001,
1129 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0,
1130 0x0214, 0, 0, armpll_div_table),
1131 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0x00000001,
1132 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0,
1134 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0x00000001,
1135 HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0,
1137 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0x00000001,
1138 HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0,
1140 PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000001,
1141 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0,
1143 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000001,
1144 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0),
1145 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0x00000001,
1146 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0),
1147 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0x00000001,
1148 HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0,
1150 PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000001,
1151 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0),
1152 PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0x00000001,
1153 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
1156 static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
1158 struct clk_onecell_data *clk_data;
1159 struct device_node *node = pdev->dev.of_node;
1161 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1163 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1165 mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks),
1168 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1171 static struct clk_onecell_data *top_clk_data;
1173 static void clk_mt8183_top_init_early(struct device_node *node)
1177 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1179 for (i = 0; i < CLK_TOP_NR_CLK; i++)
1180 top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
1182 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
1185 of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
1188 CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen",
1189 clk_mt8183_top_init_early);
1191 static int clk_mt8183_top_probe(struct platform_device *pdev)
1194 struct device_node *node = pdev->dev.of_node;
1196 base = devm_platform_ioremap_resource(pdev, 0);
1198 return PTR_ERR(base);
1200 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1203 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
1206 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1208 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
1209 node, &mt8183_clk_lock, top_clk_data);
1211 mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
1212 base, &mt8183_clk_lock, top_clk_data);
1214 mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
1215 base, &mt8183_clk_lock, top_clk_data);
1217 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
1220 return of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
1223 static int clk_mt8183_infra_probe(struct platform_device *pdev)
1225 struct clk_onecell_data *clk_data;
1226 struct device_node *node = pdev->dev.of_node;
1229 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1231 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1234 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1237 "%s(): could not register clock provider: %d\n",
1242 mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET);
1247 static int clk_mt8183_peri_probe(struct platform_device *pdev)
1249 struct clk_onecell_data *clk_data;
1250 struct device_node *node = pdev->dev.of_node;
1252 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
1254 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
1257 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1260 static int clk_mt8183_mcu_probe(struct platform_device *pdev)
1262 struct clk_onecell_data *clk_data;
1263 struct device_node *node = pdev->dev.of_node;
1266 base = devm_platform_ioremap_resource(pdev, 0);
1268 return PTR_ERR(base);
1270 clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
1272 mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
1273 &mt8183_clk_lock, clk_data);
1275 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1278 static const struct of_device_id of_match_clk_mt8183[] = {
1280 .compatible = "mediatek,mt8183-apmixedsys",
1281 .data = clk_mt8183_apmixed_probe,
1283 .compatible = "mediatek,mt8183-topckgen",
1284 .data = clk_mt8183_top_probe,
1286 .compatible = "mediatek,mt8183-infracfg",
1287 .data = clk_mt8183_infra_probe,
1289 .compatible = "mediatek,mt8183-pericfg",
1290 .data = clk_mt8183_peri_probe,
1292 .compatible = "mediatek,mt8183-mcucfg",
1293 .data = clk_mt8183_mcu_probe,
1299 static int clk_mt8183_probe(struct platform_device *pdev)
1301 int (*clk_probe)(struct platform_device *pdev);
1304 clk_probe = of_device_get_match_data(&pdev->dev);
1308 r = clk_probe(pdev);
1311 "could not register clock provider: %s: %d\n",
1317 static struct platform_driver clk_mt8183_drv = {
1318 .probe = clk_mt8183_probe,
1320 .name = "clk-mt8183",
1321 .of_match_table = of_match_clk_mt8183,
1325 static int __init clk_mt8183_init(void)
1327 return platform_driver_register(&clk_mt8183_drv);
1330 arch_initcall(clk_mt8183_init);