drivers/clk/mediatek/clk-mt7988.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MediaTek clock driver for MT7988 SoC
   4  *
   5  * Copyright (C) 2022 MediaTek Inc.
   6  * Author: Sam Shih <sam.shih@mediatek.com>
   7  */
   8
   9 #include <dm.h>
  10 #include <log.h>
  11 #include <asm/arch-mediatek/reset.h>
  12 #include <asm/io.h>
  13 #include <dt-bindings/clock/mt7988-clk.h>
  14 #include <linux/bitops.h>
  15
  16 #include "clk-mtk.h"
  17
  18 #define MT7988_CLK_PDN          0x250
  19 #define MT7988_CLK_PDN_EN_WRITE BIT(31)
  20
  21 #define MT7988_ETHDMA_RST_CTRL_OFS      0x34
  22 #define MT7988_ETHWARP_RST_CTRL_OFS     0x8
  23
  24 #define XTAL_FACTOR(_id, _name, _parent, _mult, _div)                          \
  25         FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL)
  26
  27 #define PLL_FACTOR(_id, _name, _parent, _mult, _div)                           \
  28         FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
  29
  30 #define TOP_FACTOR(_id, _name, _parent, _mult, _div)                           \
  31         FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
  32
  33 #define INFRA_FACTOR(_id, _name, _parent, _mult, _div)                         \
  34         FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS)
  35
  36 /* FIXED PLLS */
  37 static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
  38         FIXED_CLK(CK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000),
  39         FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
  40         FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000),
  41         FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
  42         FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
  43         FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
  44         FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
  45         FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
  46         FIXED_CLK(CK_APMIXED_ARM_B, CLK_XTAL, 1500000000),
  47         FIXED_CLK(CK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000),
  48         FIXED_CLK(CK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000),
  49         FIXED_CLK(CK_APMIXED_MSDCPLL, CLK_XTAL, 400000000),
  50 };
  51
  52 /* TOPCKGEN FIXED DIV */
  53 static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
  54         XTAL_FACTOR(CK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1),
  55         PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
  56         PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
  57         PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
  58         PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
  59         PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
  60         PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
  61         PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1),
  62         PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
  63         PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15),
  64         PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
  65         PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12),
  66         PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
  67         PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
  68                    1),
  69         PLL_FACTOR(CK_TOP_CB_APLL2_D4, "cb_apll2_d4", CK_APMIXED_APLL2, 1, 4),
  70         PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
  71         PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
  72         PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
  73         PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
  74         PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8),
  75         PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
  76         PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
  77         PLL_FACTOR(CK_TOP_NET1_D8_D8, "net1_d8_d8", CK_APMIXED_NET1PLL, 1, 64),
  78         PLL_FACTOR(CK_TOP_NET1_D8_D16, "net1_d8_d16", CK_APMIXED_NET1PLL, 1,
  79                    128),
  80         PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
  81                    1),
  82         PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2),
  83         PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
  84         PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
  85         PLL_FACTOR(CK_TOP_NET2_D4_D8, "net2_d4_d8", CK_APMIXED_NET2PLL, 1, 32),
  86         PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6),
  87         PLL_FACTOR(CK_TOP_CB_NET2_D8, "cb_net2_d8", CK_APMIXED_NET2PLL, 1, 8),
  88         PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m",
  89                    CK_APMIXED_WEDMCUPLL, 1, 1),
  90         PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
  91         PLL_FACTOR(CK_TOP_CB_NETSYS_850M, "cb_netsys_850m",
  92                    CK_APMIXED_NETSYSPLL, 1, 1),
  93         PLL_FACTOR(CK_TOP_CB_MSDC_400M, "cb_msdc_400m", CK_APMIXED_MSDCPLL, 1,
  94                    1),
  95         TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2),
  96         TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
  97                    1250),
  98         TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
  99                    1220),
 100         TOP_FACTOR(CK_TOP_INFRA_F32K, "csw_infra_f32k", CK_TOP_CB_RTC_32P7K, 1,
 101                    1),
 102         XTAL_FACTOR(CK_TOP_CKSQ_SRC, "cksq_src", CLK_XTAL, 1, 1),
 103         TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
 104         TOP_FACTOR(CK_TOP_NETSYS_GSW, "netsys_gsw", CK_TOP_NETSYS_GSW_SEL, 1,
 105                    1),
 106         TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
 107                    CK_TOP_NETSYS_MCU_SEL, 1, 1),
 108         TOP_FACTOR(CK_TOP_EIP197, "eip197", CK_TOP_EIP197_SEL, 1, 1),
 109         TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
 110         TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1),
 111         TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1),
 112         TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1),
 113         TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
 114         TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
 115         TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
 116         TOP_FACTOR(CK_TOP_USB_SYS, "usb_sys", CK_TOP_USB_SYS_SEL, 1, 1),
 117         TOP_FACTOR(CK_TOP_USB_SYS_P1, "usb_sys_p1", CK_TOP_USB_SYS_P1_SEL, 1,
 118                    1),
 119         TOP_FACTOR(CK_TOP_USB_XHCI, "usb_xhci", CK_TOP_USB_XHCI_SEL, 1, 1),
 120         TOP_FACTOR(CK_TOP_USB_XHCI_P1, "usb_xhci_p1", CK_TOP_USB_XHCI_P1_SEL, 1,
 121                    1),
 122         TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1,
 123                    1),
 124         TOP_FACTOR(CK_TOP_USB_FRMCNT_P1, "usb_frmcnt_p1",
 125                    CK_TOP_USB_FRMCNT_P1_SEL, 1, 1),
 126         TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_AUD_SEL, 1, 1),
 127         TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
 128         TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
 129         TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1),
 130         TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
 131         TOP_FACTOR(CK_TOP_INFRA_F26M, "csw_infra_f26m", CK_TOP_INFRA_F26M_SEL,
 132                    1, 1),
 133         TOP_FACTOR(CK_TOP_USB_REF, "usb_ref", CK_TOP_CKSQ_SRC, 1, 1),
 134         TOP_FACTOR(CK_TOP_USB_CK_P1, "usb_ck_p1", CK_TOP_CKSQ_SRC, 1, 1),
 135 };
 136
 137 /* TOPCKGEN MUX PARENTS */
 138 static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2,
 139                                       CK_TOP_CB_MM_D2 };
 140
 141 static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
 142                                            CK_TOP_CB_NET1_D5,
 143                                            CK_TOP_NET1_D5_D2 };
 144
 145 static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
 146                                          CK_TOP_CB_NET2_800M,
 147                                          CK_TOP_CB_MM_720M };
 148
 149 static const int netsys_gsw_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D4,
 150                                           CK_TOP_CB_NET1_D5 };
 151
 152 static const int eth_gmii_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
 153
 154 static const int netsys_mcu_parents[] = {
 155         CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M, CK_TOP_CB_MM_720M,
 156         CK_TOP_CB_NET1_D4,  CK_TOP_CB_NET1_D5,   CK_TOP_CB_M_416M
 157 };
 158
 159 static const int eip197_parents[] = {
 160         CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NETSYS_850M, CK_TOP_CB_NET2_800M,
 161         CK_TOP_CB_MM_720M,  CK_TOP_CB_NET1_D4,     CK_TOP_CB_NET1_D5
 162 };
 163
 164 static const int axi_infra_parents[] = { CK_TOP_CB_CKSQ_40M,
 165                                          CK_TOP_NET1_D8_D2 };
 166
 167 static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
 168                                     CK_TOP_M_D8_D2 };
 169
 170 static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D2,
 171                                          CK_TOP_CB_MM_D4 };
 172
 173 static const int emmc_400m_parents[] = {
 174         CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MSDC_400M, CK_TOP_CB_MM_D2,
 175         CK_TOP_CB_M_D2,     CK_TOP_CB_MM_D4,     CK_TOP_NET1_D8_D2
 176 };
 177
 178 static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
 179                                    CK_TOP_CB_MM_D4,    CK_TOP_NET1_D8_D2,
 180                                    CK_TOP_CB_NET2_D6,  CK_TOP_NET1_D5_D4,
 181                                    CK_TOP_CB_M_D4,     CK_TOP_NET1_D8_D4 };
 182
 183 static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4,
 184                                      CK_TOP_NET1_D8_D2,  CK_TOP_CB_NET2_D6,
 185                                      CK_TOP_CB_M_D4,     CK_TOP_CB_MM_D8,
 186                                      CK_TOP_NET1_D8_D4,  CK_TOP_CB_M_D8 };
 187
 188 static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M,
 189                                       CK_TOP_NET1_D5_D4,  CK_TOP_CB_M_D4,
 190                                       CK_TOP_CB_MM_D8,    CK_TOP_NET1_D8_D4,
 191                                       CK_TOP_MM_D6_D2,    CK_TOP_CB_M_D8 };
 192
 193 static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
 194                                    CK_TOP_NET1_D5_D4,  CK_TOP_CB_M_D4,
 195                                    CK_TOP_M_D8_D2,     CK_TOP_CB_RTC_32K };
 196
 197 static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
 198                                    CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
 199
 200 static const int pcie_mbist_250m_parents[] = { CK_TOP_CB_CKSQ_40M,
 201                                                CK_TOP_NET1_D5_D2 };
 202
 203 static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
 204                                            CK_TOP_CB_NET2_D6, CK_TOP_CB_MM_D8,
 205                                            CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
 206
 207 static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M,
 208                                           CK_TOP_CB_MM_D3_D5 };
 209
 210 static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M };
 211
 212 static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_D4 };
 213
 214 static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
 215                                      CK_TOP_M_D8_D2 };
 216
 217 static const int sspxtp_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 };
 218
 219 static const int usxgmii_sbus_0_parents[] = { CK_TOP_CB_CKSQ_40M,
 220                                               CK_TOP_NET1_D8_D4 };
 221
 222 static const int sgm_0_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M };
 223
 224 static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 };
 225
 226 static const int eth_refck_50m_parents[] = { CK_TOP_CB_CKSQ_40M,
 227                                              CK_TOP_NET2_D4_D4 };
 228
 229 static const int eth_sys_200m_parents[] = { CK_TOP_CB_CKSQ_40M,
 230                                             CK_TOP_CB_NET2_D4 };
 231
 232 static const int eth_xgmii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET1_D8_D8,
 233                                          CK_TOP_NET1_D8_D16 };
 234
 235 static const int bus_tops_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,
 236                                         CK_TOP_CB_NET2_D2 };
 237
 238 static const int npu_tops_parents[] = { CK_TOP_CB_CKSQ_40M,
 239                                         CK_TOP_CB_NET2_800M };
 240
 241 static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
 242                                           CK_TOP_CB_WEDMCU_208M };
 243
 244 static const int da_xtp_glb_p0_parents[] = { CK_TOP_CB_CKSQ_40M,
 245                                              CK_TOP_CB_NET2_D8 };
 246
 247 static const int mcusys_backup_625m_parents[] = { CK_TOP_CB_CKSQ_40M,
 248                                                   CK_TOP_CB_NET1_D4 };
 249
 250 static const int macsec_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M,
 251                                       CK_TOP_CB_NET1_D8 };
 252
 253 static const int netsys_tops_400m_parents[] = { CK_TOP_CB_CKSQ_40M,
 254                                                 CK_TOP_CB_NET2_D2 };
 255
 256 static const int eth_mii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET2_D4_D8 };
 257
 258 #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs,    \
 259                 _shift, _width, _gate, _upd_ofs, _upd)                         \
 260         {                                                                      \
 261                 .id = _id, .mux_reg = _mux_ofs, .mux_set_reg = _mux_set_ofs,   \
 262                 .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs,              \
 263                 .upd_shift = _upd, .mux_shift = _shift,                        \
 264                 .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs,             \
 265                 .gate_shift = _gate, .parent = _parents,                       \
 266                 .num_parents = ARRAY_SIZE(_parents),                           \
 267                 .flags = CLK_MUX_SETCLR_UPD,                                   \
 268         }
 269
 270 /* TOPCKGEN MUX_GATE */
 271 static const struct mtk_composite topckgen_mtk_muxes[] = {
 272         TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8,
 273                 0, 2, 7, 0x1c0, 0),
 274         TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
 275                 0x0, 0x4, 0x8, 8, 2, 15, 0x1c0, 1),
 276         TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0,
 277                 0x4, 0x8, 16, 2, 23, 0x1c0, 2),
 278         TOP_MUX(CK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents,
 279                 0x0, 0x4, 0x8, 24, 2, 31, 0x1c0, 3),
 280         TOP_MUX(CK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10,
 281                 0x14, 0x18, 0, 1, 7, 0x1c0, 4),
 282         TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
 283                 0x10, 0x14, 0x18, 8, 3, 15, 0x1c0, 5),
 284         TOP_MUX(CK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
 285                 netsys_mcu_parents, 0x10, 0x14, 0x18, 16, 3, 23, 0x1c0, 6),
 286         TOP_MUX(CK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14,
 287                 0x18, 24, 3, 31, 0x1c0, 7),
 288         TOP_MUX(CK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20,
 289                 0x24, 0x28, 0, 1, 7, 0x1c0, 8),
 290         TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8,
 291                 2, 15, 0x1c0, 9),
 292         TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20,
 293                 0x24, 0x28, 16, 2, 23, 0x1c0, 10),
 294         TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
 295                 0x24, 0x28, 24, 3, 31, 0x1c0, 11),
 296         TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3,
 297                 7, 0x1c0, 12),
 298         TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34,
 299                 0x38, 8, 3, 15, 0x1c0, 13),
 300         TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38,
 301                 16, 3, 23, 0x1c0, 14),
 302         TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34,
 303                 0x38, 24, 3, 31, 0x1c0, 15),
 304         TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3,
 305                 7, 0x1c0, 16),
 306         TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2,
 307                 15, 0x1c0, 17),
 308         TOP_MUX(CK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
 309                 pcie_mbist_250m_parents, 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0,
 310                 18),
 311         TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
 312                 0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19),
 313         TOP_MUX(CK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel",
 314                 pextp_tl_ck_parents, 0x50, 0x54, 0x58, 0, 3, 7, 0x1c0, 20),
 315         TOP_MUX(CK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel",
 316                 pextp_tl_ck_parents, 0x50, 0x54, 0x58, 8, 3, 15, 0x1c0, 21),
 317         TOP_MUX(CK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel",
 318                 pextp_tl_ck_parents, 0x50, 0x54, 0x58, 16, 3, 23, 0x1c0, 22),
 319         TOP_MUX(CK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54,
 320                 0x58, 24, 1, 31, 0x1c0, 23),
 321         TOP_MUX(CK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60,
 322                 0x64, 0x68, 0, 1, 7, 0x1c0, 24),
 323         TOP_MUX(CK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60,
 324                 0x64, 0x68, 8, 1, 15, 0x1c0, 25),
 325         TOP_MUX(CK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents,
 326                 0x60, 0x64, 0x68, 16, 1, 23, 0x1c0, 26),
 327         TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
 328                 0x60, 0x64, 0x68, 24, 1, 31, 0x1c0, 27),
 329         TOP_MUX(CK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
 330                 usb_frmcnt_parents, 0x70, 0x74, 0x78, 0, 1, 7, 0x1c0, 28),
 331         TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1,
 332                 15, 0x1c0, 29),
 333         TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78,
 334                 16, 1, 23, 0x1c0, 30),
 335         TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78,
 336                 24, 2, 31, 0x1c4, 0),
 337         TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84,
 338                 0x88, 0, 1, 7, 0x1c4, 1),
 339         TOP_MUX(CK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84,
 340                 0x88, 8, 1, 15, 0x1c4, 2),
 341         TOP_MUX(CK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84,
 342                 0x88, 16, 1, 23, 0x1c4, 3),
 343         TOP_MUX(CK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
 344                 usxgmii_sbus_0_parents, 0x80, 0x84, 0x88, 24, 1, 31, 0x1c4, 4),
 345         TOP_MUX(CK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
 346                 usxgmii_sbus_0_parents, 0x90, 0x94, 0x98, 0, 1, 7, 0x1c4, 5),
 347         TOP_MUX(CK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98,
 348                 8, 1, 15, 0x1c4, 6),
 349         TOP_MUX(CK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
 350                 0x90, 0x94, 0x98, 16, 1, 23, 0x1c4, 7),
 351         TOP_MUX(CK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98,
 352                 24, 1, 31, 0x1c4, 8),
 353         TOP_MUX(CK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
 354                 0xa0, 0xa4, 0xa8, 0, 1, 7, 0x1c4, 9),
 355         TOP_MUX(CK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
 356                 0xa0, 0xa4, 0xa8, 8, 1, 15, 0x1c4, 10),
 357         TOP_MUX(CK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
 358                 0xa0, 0xa4, 0xa8, 16, 1, 23, 0x1c4, 11),
 359         TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4,
 360                 0xa8, 24, 1, 31, 0x1c4, 12),
 361         TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4,
 362                 0xb8, 0, 1, 7, 0x1c4, 13),
 363         TOP_MUX(CK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
 364                 eth_refck_50m_parents, 0xb0, 0xb4, 0xb8, 8, 1, 15, 0x1c4, 14),
 365         TOP_MUX(CK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
 366                 eth_sys_200m_parents, 0xb0, 0xb4, 0xb8, 16, 1, 23, 0x1c4, 15),
 367         TOP_MUX(CK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents,
 368                 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x1c4, 16),
 369         TOP_MUX(CK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0,
 370                 0xc4, 0xc8, 0, 2, 7, 0x1c4, 17),
 371         TOP_MUX(CK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0,
 372                 0xc4, 0xc8, 8, 2, 15, 0x1c4, 18),
 373         TOP_MUX(CK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0,
 374                 0xc4, 0xc8, 16, 1, 23, 0x1c4, 19),
 375         TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8,
 376                 24, 1, 31, 0x1c4, 20),
 377         TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
 378                 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x1c4, 21),
 379         TOP_MUX(CK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
 380                 0xd0, 0xd4, 0xd8, 8, 1, 15, 0x1c4, 22),
 381         TOP_MUX(CK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4,
 382                 0xd8, 16, 1, 23, 0x1c4, 23),
 383         TOP_MUX(CK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4,
 384                 0xd8, 24, 1, 31, 0x1c4, 24),
 385         TOP_MUX(CK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4,
 386                 0xe8, 0, 1, 7, 0x1c4, 25),
 387         TOP_MUX(CK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4,
 388                 0xe8, 8, 1, 15, 0x1c4, 26),
 389         TOP_MUX(CK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
 390                 da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 16, 1, 23, 0x1c4, 27),
 391         TOP_MUX(CK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
 392                 da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 24, 1, 31, 0x1c4, 28),
 393         TOP_MUX(CK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
 394                 da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x1c4, 29),
 395         TOP_MUX(CK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
 396                 da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 8, 1, 15, 0x1c4, 30),
 397         TOP_MUX(CK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16,
 398                 1, 23, 0x1c8, 0),
 399         TOP_MUX(CK_TOP_DA_SELM_XTAL_SEL, "da_selm_xtal_sel", sspxtp_parents,
 400                 0xf0, 0xf4, 0xf8, 24, 1, 31, 0x1c8, 1),
 401         TOP_MUX(CK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104,
 402                 0x108, 0, 1, 7, 0x1c8, 2),
 403         TOP_MUX(CK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents,
 404                 0x100, 0x104, 0x108, 8, 1, 15, 0x1c8, 3),
 405         TOP_MUX(CK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
 406                 mcusys_backup_625m_parents, 0x100, 0x104, 0x108, 16, 1, 23,
 407                 0x1c8, 4),
 408         TOP_MUX(CK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
 409                 pcie_mbist_250m_parents, 0x100, 0x104, 0x108, 24, 1, 31, 0x1c8,
 410                 5),
 411         TOP_MUX(CK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114,
 412                 0x118, 0, 2, 7, 0x1c8, 6),
 413         TOP_MUX(CK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
 414                 netsys_tops_400m_parents, 0x110, 0x114, 0x118, 8, 1, 15, 0x1c8,
 415                 7),
 416         TOP_MUX(CK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
 417                 pcie_mbist_250m_parents, 0x110, 0x114, 0x118, 16, 1, 23, 0x1c8,
 418                 8),
 419         TOP_MUX(CK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents,
 420                 0x110, 0x114, 0x118, 24, 2, 31, 0x1c8, 9),
 421         TOP_MUX(CK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120,
 422                 0x124, 0x128, 0, 1, 7, 0x1c8, 10),
 423         TOP_MUX(CK_TOP_CK_NPU_SEL_CM_TOPS_SEL, "ck_npu_sel_cm_tops_sel",
 424                 netsys_2x_parents, 0x120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
 425 };
 426
 427 /* INFRA FIXED DIV */
 428 static const struct mtk_fixed_factor infracfg_mtk_fixed_factor[] = {
 429         TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_INFRA_F26M_SEL, 1,
 430                    1),
 431         TOP_FACTOR(CK_INFRA_PWM_O, "infra_pwm_o", CK_TOP_PWM_SEL, 1, 1),
 432         TOP_FACTOR(CK_INFRA_PCIE_OCC_P0, "infra_pcie_ck_occ_p0",
 433                    CK_TOP_PEXTP_TL_SEL, 1, 1),
 434         TOP_FACTOR(CK_INFRA_PCIE_OCC_P1, "infra_pcie_ck_occ_p1",
 435                    CK_TOP_PEXTP_TL_P1_SEL, 1, 1),
 436         TOP_FACTOR(CK_INFRA_PCIE_OCC_P2, "infra_pcie_ck_occ_p2",
 437                    CK_TOP_PEXTP_TL_P2_SEL, 1, 1),
 438         TOP_FACTOR(CK_INFRA_PCIE_OCC_P3, "infra_pcie_ck_occ_p3",
 439                    CK_TOP_PEXTP_TL_P3_SEL, 1, 1),
 440         TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
 441         INFRA_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_INFRA_133M_HCK,
 442                      1, 1),
 443         INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
 444                      1),
 445         TOP_FACTOR(CK_INFRA_FAUD_L_O, "infra_faud_l_o", CK_TOP_AUD_L, 1, 1),
 446         TOP_FACTOR(CK_INFRA_FAUD_AUD_O, "infra_faud_aud_o", CK_TOP_A1SYS, 1, 1),
 447         TOP_FACTOR(CK_INFRA_FAUD_EG2_O, "infra_faud_eg2_o", CK_TOP_A_TUNER, 1,
 448                    1),
 449         TOP_FACTOR(CK_INFRA_I2C_O, "infra_i2c_o", CK_TOP_I2C_BCK, 1, 1),
 450         TOP_FACTOR(CK_INFRA_UART_O0, "infra_uart_o0", CK_TOP_UART_SEL, 1, 1),
 451         TOP_FACTOR(CK_INFRA_UART_O1, "infra_uart_o1", CK_TOP_UART_SEL, 1, 1),
 452         TOP_FACTOR(CK_INFRA_UART_O2, "infra_uart_o2", CK_TOP_UART_SEL, 1, 1),
 453         TOP_FACTOR(CK_INFRA_NFI_O, "infra_nfi_o", CK_TOP_NFI1X, 1, 1),
 454         TOP_FACTOR(CK_INFRA_SPINFI_O, "infra_spinfi_o", CK_TOP_SPINFI_BCK, 1,
 455                    1),
 456         TOP_FACTOR(CK_INFRA_SPI0_O, "infra_spi0_o", CK_TOP_SPI, 1, 1),
 457         TOP_FACTOR(CK_INFRA_SPI1_O, "infra_spi1_o", CK_TOP_SPIM_MST, 1, 1),
 458         INFRA_FACTOR(CK_INFRA_LB_MUX_FRTC, "infra_lb_mux_frtc", CK_INFRA_FRTC,
 459                      1, 1),
 460         TOP_FACTOR(CK_INFRA_FRTC, "infra_frtc", CK_TOP_CB_RTC_32K, 1, 1),
 461         TOP_FACTOR(CK_INFRA_FMSDC400_O, "infra_fmsdc400_o", CK_TOP_EMMC_400M, 1,
 462                    1),
 463         TOP_FACTOR(CK_INFRA_FMSDC2_HCK_OCC, "infra_fmsdc2_hck_occ",
 464                    CK_TOP_EMMC_250M, 1, 1),
 465         TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
 466         TOP_FACTOR(CK_INFRA_USB_O, "infra_usb_o", CK_TOP_USB_REF, 1, 1),
 467         TOP_FACTOR(CK_INFRA_USB_O_P1, "infra_usb_o_p1", CK_TOP_USB_CK_P1, 1, 1),
 468         TOP_FACTOR(CK_INFRA_USB_FRMCNT_O, "infra_usb_frmcnt_o",
 469                    CK_TOP_USB_FRMCNT, 1, 1),
 470         TOP_FACTOR(CK_INFRA_USB_FRMCNT_O_P1, "infra_usb_frmcnt_o_p1",
 471                    CK_TOP_USB_FRMCNT_P1, 1, 1),
 472         TOP_FACTOR(CK_INFRA_USB_XHCI_O, "infra_usb_xhci_o", CK_TOP_USB_XHCI, 1,
 473                    1),
 474         TOP_FACTOR(CK_INFRA_USB_XHCI_O_P1, "infra_usb_xhci_o_p1",
 475                    CK_TOP_USB_XHCI_P1, 1, 1),
 476         XTAL_FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", CLK_XTAL, 1, 1),
 477         XTAL_FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", CLK_XTAL, 1,
 478                     1),
 479         XTAL_FACTOR(CK_INFRA_USB_UTMI_O, "infra_usb_utmi_o", CLK_XTAL, 1, 1),
 480         XTAL_FACTOR(CK_INFRA_USB_UTMI_O_P1, "infra_usb_utmi_o_p1", CLK_XTAL, 1,
 481                     1),
 482         XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P0, "infra_pcie_pipe_ck_occ_p0",
 483                     CLK_XTAL, 1, 1),
 484         XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P1, "infra_pcie_pipe_ck_occ_p1",
 485                     CLK_XTAL, 1, 1),
 486         XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P2, "infra_pcie_pipe_ck_occ_p2",
 487                     CLK_XTAL, 1, 1),
 488         XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P3, "infra_pcie_pipe_ck_occ_p3",
 489                     CLK_XTAL, 1, 1),
 490         TOP_FACTOR(CK_INFRA_F26M_O0, "infra_f26m_o0", CK_TOP_INFRA_F26M, 1, 1),
 491         TOP_FACTOR(CK_INFRA_F26M_O1, "infra_f26m_o1", CK_TOP_INFRA_F26M, 1, 1),
 492         TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1),
 493         TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI, 1, 1),
 494         TOP_FACTOR(CK_INFRA_PERI_66M_O, "infra_peri_66m_o", CK_TOP_SYSAXI, 1,
 495                    1),
 496         TOP_FACTOR(CK_INFRA_USB_SYS_O, "infra_usb_sys_o", CK_TOP_USB_SYS, 1, 1),
 497         TOP_FACTOR(CK_INFRA_USB_SYS_O_P1, "infra_usb_sys_o_p1",
 498                    CK_TOP_USB_SYS_P1, 1, 1),
 499 };
 500
 501 /* INFRASYS MUX PARENTS */
 502 static const int infra_mux_uart0_parents[] = { CK_INFRA_CK_F26M,
 503                                                CK_INFRA_UART_O0 };
 504
 505 static const int infra_mux_uart1_parents[] = { CK_INFRA_CK_F26M,
 506                                                CK_INFRA_UART_O1 };
 507
 508 static const int infra_mux_uart2_parents[] = { CK_INFRA_CK_F26M,
 509                                                CK_INFRA_UART_O2 };
 510
 511 static const int infra_mux_spi0_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI0_O };
 512
 513 static const int infra_mux_spi1_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI1_O };
 514
 515 static const int infra_pwm_bck_parents[] = { CK_TOP_INFRA_F32K,
 516                                              CK_INFRA_CK_F26M, CK_INFRA_66M_MCK,
 517                                              CK_INFRA_PWM_O };
 518
 519 static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = {
 520         CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
 521         CK_INFRA_PCIE_OCC_P0
 522 };
 523
 524 static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = {
 525         CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
 526         CK_INFRA_PCIE_OCC_P1
 527 };
 528
 529 static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = {
 530         CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
 531         CK_INFRA_PCIE_OCC_P2
 532 };
 533
 534 static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
 535         CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
 536         CK_INFRA_PCIE_OCC_P3
 537 };
 538
 539 #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width)                  \
 540         {                                                                      \
 541                 .id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0,   \
 542                 .mux_clr_reg = _reg + 0x4, .mux_shift = _shift,                \
 543                 .mux_mask = BIT(_width) - 1, .parent = _parents,               \
 544                 .num_parents = ARRAY_SIZE(_parents),                           \
 545                 .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS,             \
 546         }
 547
 548 /* INFRA MUX */
 549 static const struct mtk_composite infracfg_mtk_mux[] = {
 550         INFRA_MUX(CK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
 551                   infra_mux_uart0_parents, 0x10, 0, 1),
 552         INFRA_MUX(CK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
 553                   infra_mux_uart1_parents, 0x10, 1, 1),
 554         INFRA_MUX(CK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
 555                   infra_mux_uart2_parents, 0x10, 2, 1),
 556         INFRA_MUX(CK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
 557                   infra_mux_spi0_parents, 0x10, 4, 1),
 558         INFRA_MUX(CK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
 559                   infra_mux_spi1_parents, 0x10, 5, 1),
 560         INFRA_MUX(CK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
 561                   infra_mux_spi0_parents, 0x10, 6, 1),
 562         INFRA_MUX(CK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents,
 563                   0x10, 14, 2),
 564         INFRA_MUX(CK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
 565                   infra_pwm_bck_parents, 0x10, 16, 2),
 566         INFRA_MUX(CK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
 567                   infra_pwm_bck_parents, 0x10, 18, 2),
 568         INFRA_MUX(CK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
 569                   infra_pwm_bck_parents, 0x10, 20, 2),
 570         INFRA_MUX(CK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
 571                   infra_pwm_bck_parents, 0x10, 22, 2),
 572         INFRA_MUX(CK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
 573                   infra_pwm_bck_parents, 0x10, 24, 2),
 574         INFRA_MUX(CK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
 575                   infra_pwm_bck_parents, 0x10, 26, 2),
 576         INFRA_MUX(CK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
 577                   infra_pwm_bck_parents, 0x10, 28, 2),
 578         INFRA_MUX(CK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
 579                   infra_pwm_bck_parents, 0x10, 30, 2),
 580         INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
 581                   "infra_pcie_gfmux_tl_o_p0_sel",
 582                   infra_pcie_gfmux_tl_ck_o_p0_parents, 0x20, 0, 2),
 583         INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
 584                   "infra_pcie_gfmux_tl_o_p1_sel",
 585                   infra_pcie_gfmux_tl_ck_o_p1_parents, 0x20, 2, 2),
 586         INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
 587                   "infra_pcie_gfmux_tl_o_p2_sel",
 588                   infra_pcie_gfmux_tl_ck_o_p2_parents, 0x20, 4, 2),
 589         INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
 590                   "infra_pcie_gfmux_tl_o_p3_sel",
 591                   infra_pcie_gfmux_tl_ck_o_p3_parents, 0x20, 6, 2),
 592 };
 593
 594 static const struct mtk_gate_regs infra_0_cg_regs = {
 595         .set_ofs = 0x10,
 596         .clr_ofs = 0x14,
 597         .sta_ofs = 0x18,
 598 };
 599
 600 static const struct mtk_gate_regs infra_1_cg_regs = {
 601         .set_ofs = 0x40,
 602         .clr_ofs = 0x44,
 603         .sta_ofs = 0x48,
 604 };
 605
 606 static const struct mtk_gate_regs infra_2_cg_regs = {
 607         .set_ofs = 0x50,
 608         .clr_ofs = 0x54,
 609         .sta_ofs = 0x58,
 610 };
 611
 612 static const struct mtk_gate_regs infra_3_cg_regs = {
 613         .set_ofs = 0x60,
 614         .clr_ofs = 0x64,
 615         .sta_ofs = 0x68,
 616 };
 617
 618 #define GATE_INFRA0(_id, _name, _parent, _shift)                               \
 619         {                                                                      \
 620                 .id = _id, .parent = _parent, .regs = &infra_0_cg_regs,        \
 621                 .shift = _shift,                                               \
 622                 .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
 623         }
 624
 625 #define GATE_INFRA1(_id, _name, _parent, _shift)                               \
 626         {                                                                      \
 627                 .id = _id, .parent = _parent, .regs = &infra_1_cg_regs,        \
 628                 .shift = _shift,                                               \
 629                 .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
 630         }
 631
 632 #define GATE_INFRA2(_id, _name, _parent, _shift)                               \
 633         {                                                                      \
 634                 .id = _id, .parent = _parent, .regs = &infra_2_cg_regs,        \
 635                 .shift = _shift,                                               \
 636                 .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
 637         }
 638
 639 #define GATE_INFRA3(_id, _name, _parent, _shift)                               \
 640         {                                                                      \
 641                 .id = _id, .parent = _parent, .regs = &infra_3_cg_regs,        \
 642                 .shift = _shift,                                               \
 643                 .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS,                \
 644         }
 645
 646 /* INFRA GATE */
 647 static const struct mtk_gate infracfg_mtk_gates[] = {
 648         GATE_INFRA1(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
 649                     CK_INFRA_66M_MCK, 0),
 650         GATE_INFRA1(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
 651                     CK_INFRA_66M_MCK, 1),
 652         GATE_INFRA1(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
 653                     CK_INFRA_PWM_SEL, 2),
 654         GATE_INFRA1(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
 655                     CK_INFRA_PWM_CK1_SEL, 3),
 656         GATE_INFRA1(CK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
 657                     CK_INFRA_PWM_CK2_SEL, 4),
 658         GATE_INFRA1(CK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
 659                     CK_INFRA_PWM_CK3_SEL, 5),
 660         GATE_INFRA1(CK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
 661                     CK_INFRA_PWM_CK4_SEL, 6),
 662         GATE_INFRA1(CK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
 663                     CK_INFRA_PWM_CK5_SEL, 7),
 664         GATE_INFRA1(CK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
 665                     CK_INFRA_PWM_CK6_SEL, 8),
 666         GATE_INFRA1(CK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
 667                     CK_INFRA_PWM_CK7_SEL, 9),
 668         GATE_INFRA1(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
 669                     CK_INFRA_PWM_CK8_SEL, 10),
 670         GATE_INFRA1(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
 671                     CK_INFRA_133M_MCK, 12),
 672         GATE_INFRA1(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
 673                     CK_INFRA_66M_PHCK, 13),
 674         GATE_INFRA1(CK_INFRA_AUD_26M, "infra_f_faud_26m", CK_INFRA_CK_F26M, 14),
 675         GATE_INFRA1(CK_INFRA_AUD_L, "infra_f_faud_l", CK_INFRA_FAUD_L_O, 15),
 676         GATE_INFRA1(CK_INFRA_AUD_AUD, "infra_f_aud_aud", CK_INFRA_FAUD_AUD_O,
 677                     16),
 678         GATE_INFRA1(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", CK_INFRA_FAUD_EG2_O,
 679                     18),
 680         GATE_INFRA1(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CK_INFRA_CK_F26M,
 681                     19),
 682         GATE_INFRA1(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
 683                     CK_INFRA_133M_MCK, 20),
 684         GATE_INFRA1(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
 685                     CK_INFRA_66M_MCK, 21),
 686         GATE_INFRA1(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
 687                     CK_INFRA_66M_MCK, 29),
 688         GATE_INFRA1(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
 689                     CK_INFRA_CK_F26M, 30),
 690         GATE_INFRA1(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_INFRA_PERI_66M_O,
 691                     31),
 692         GATE_INFRA2(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
 693                     CK_INFRA_CK_F26M, 0),
 694         GATE_INFRA2(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_INFRA_I2C_O, 1),
 695         GATE_INFRA2(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
 696                     CK_INFRA_66M_MCK, 3),
 697         GATE_INFRA2(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
 698                     CK_INFRA_66M_MCK, 4),
 699         GATE_INFRA2(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
 700                     CK_INFRA_66M_MCK, 5),
 701         GATE_INFRA2(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
 702                     CK_INFRA_MUX_UART0_SEL, 3),
 703         GATE_INFRA2(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
 704                     CK_INFRA_MUX_UART1_SEL, 4),
 705         GATE_INFRA2(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
 706                     CK_INFRA_MUX_UART2_SEL, 5),
 707         GATE_INFRA2(CK_INFRA_NFI, "infra_f_fnfi", CK_INFRA_NFI_O, 9),
 708         GATE_INFRA2(CK_INFRA_SPINFI, "infra_f_fspinfi", CK_INFRA_SPINFI_O, 10),
 709         GATE_INFRA2(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
 710                     CK_INFRA_66M_MCK, 11),
 711         GATE_INFRA2(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
 712                     CK_INFRA_MUX_SPI0_SEL, 12),
 713         GATE_INFRA2(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
 714                     CK_INFRA_MUX_SPI1_SEL, 13),
 715         GATE_INFRA2(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
 716                     CK_INFRA_MUX_SPI2_SEL, 14),
 717         GATE_INFRA2(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
 718                     CK_INFRA_66M_MCK, 15),
 719         GATE_INFRA2(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
 720                     CK_INFRA_66M_MCK, 16),
 721         GATE_INFRA2(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
 722                     CK_INFRA_66M_MCK, 17),
 723         GATE_INFRA2(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
 724                     CK_INFRA_66M_MCK, 18),
 725         GATE_INFRA2(CK_INFRA_RTC, "infra_f_frtc", CK_INFRA_LB_MUX_FRTC, 19),
 726         GATE_INFRA2(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
 727                     CK_INFRA_F26M_O1, 20),
 728         GATE_INFRA2(CK_INFRA_RC_ADC, "infra_f_frc_adc", CK_INFRA_26M_ADC_BCK,
 729                     21),
 730         GATE_INFRA2(CK_INFRA_MSDC400, "infra_f_fmsdc400", CK_INFRA_FMSDC400_O,
 731                     22),
 732         GATE_INFRA2(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
 733                     CK_INFRA_FMSDC2_HCK_OCC, 23),
 734         GATE_INFRA2(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
 735                     CK_INFRA_PERI_133M, 24),
 736         GATE_INFRA2(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
 737                     CK_INFRA_66M_PHCK, 25),
 738         GATE_INFRA2(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
 739                     CK_INFRA_133M_MCK, 26),
 740         GATE_INFRA2(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CK_INFRA_NFI_O,
 741                     27),
 742         GATE_INFRA2(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
 743                     CK_INFRA_133M_MCK, 29),
 744         GATE_INFRA2(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
 745                     CK_INFRA_66M_PHCK, 31),
 746         GATE_INFRA3(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
 747                     CK_INFRA_133M_PHCK, 0),
 748         GATE_INFRA3(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
 749                     CK_INFRA_133M_PHCK, 1),
 750         GATE_INFRA3(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck",
 751                     CK_INFRA_66M_PHCK, 2),
 752         GATE_INFRA3(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
 753                     CK_INFRA_66M_PHCK, 3),
 754         GATE_INFRA3(CK_INFRA_USB_SYS, "infra_usb_sys", CK_INFRA_USB_SYS_O, 4),
 755         GATE_INFRA3(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
 756                     CK_INFRA_USB_SYS_O_P1, 5),
 757         GATE_INFRA3(CK_INFRA_USB_REF, "infra_usb_ref", CK_INFRA_USB_O, 6),
 758         GATE_INFRA3(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CK_INFRA_USB_O_P1,
 759                     7),
 760         GATE_INFRA3(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
 761                     CK_INFRA_USB_FRMCNT_O, 8),
 762         GATE_INFRA3(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
 763                     CK_INFRA_USB_FRMCNT_O_P1, 9),
 764         GATE_INFRA3(CK_INFRA_USB_PIPE, "infra_usb_pipe", CK_INFRA_USB_PIPE_O,
 765                     10),
 766         GATE_INFRA3(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
 767                     CK_INFRA_USB_PIPE_O_P1, 11),
 768         GATE_INFRA3(CK_INFRA_USB_UTMI, "infra_usb_utmi", CK_INFRA_USB_UTMI_O,
 769                     12),
 770         GATE_INFRA3(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
 771                     CK_INFRA_USB_UTMI_O_P1, 13),
 772         GATE_INFRA3(CK_INFRA_USB_XHCI, "infra_usb_xhci", CK_INFRA_USB_XHCI_O,
 773                     14),
 774         GATE_INFRA3(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
 775                     CK_INFRA_USB_XHCI_O_P1, 15),
 776         GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
 777                     CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20),
 778         GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
 779                     CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21),
 780         GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
 781                     CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22),
 782         GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
 783                     CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23),
 784         GATE_INFRA3(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
 785                     CK_INFRA_PCIE_PIPE_OCC_P0, 24),
 786         GATE_INFRA3(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
 787                     CK_INFRA_PCIE_PIPE_OCC_P1, 25),
 788         GATE_INFRA3(CK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
 789                     CK_INFRA_PCIE_PIPE_OCC_P2, 26),
 790         GATE_INFRA3(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
 791                     CK_INFRA_PCIE_PIPE_OCC_P3, 27),
 792         GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
 793                     CK_INFRA_133M_PHCK, 28),
 794         GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
 795                     CK_INFRA_133M_PHCK, 29),
 796         GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
 797                     CK_INFRA_133M_PHCK, 30),
 798         GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
 799                     CK_INFRA_133M_PHCK, 31),
 800         GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P0,
 801                     "infra_pcie_peri_ck_26m_ck_p0", CK_INFRA_F26M_O0, 7),
 802         GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1,
 803                     "infra_pcie_peri_ck_26m_ck_p1", CK_INFRA_F26M_O0, 8),
 804         GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P2,
 805                     "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_F26M_O0, 9),
 806         GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P3,
 807                     "infra_pcie_peri_ck_26m_ck_p3", CK_INFRA_F26M_O0, 10),
 808 };
 809
 810 static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
 811         .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls),
 812         .fclks = apmixedsys_mtk_plls,
 813         .xtal_rate = 40 * MHZ,
 814 };
 815
 816 static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
 817         .fdivs_offs = CK_TOP_CB_CKSQ_40M,
 818         .muxes_offs = CK_TOP_NETSYS_SEL,
 819         .fdivs = topckgen_mtk_fixed_factors,
 820         .muxes = topckgen_mtk_muxes,
 821         .flags = CLK_BYPASS_XTAL,
 822         .xtal_rate = 40 * MHZ,
 823 };
 824
 825 static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
 826         .fdivs_offs = CK_INFRA_CK_F26M,
 827         .muxes_offs = CK_INFRA_MUX_UART0_SEL,
 828         .fdivs = infracfg_mtk_fixed_factor,
 829         .muxes = infracfg_mtk_mux,
 830         .flags = CLK_BYPASS_XTAL,
 831         .xtal_rate = 40 * MHZ,
 832 };
 833
 834 static const struct udevice_id mt7988_fixed_pll_compat[] = {
 835         { .compatible = "mediatek,mt7988-fixed-plls" },
 836         {}
 837 };
 838
 839 static const struct udevice_id mt7988_topckgen_compat[] = {
 840         { .compatible = "mediatek,mt7988-topckgen" },
 841         {}
 842 };
 843
 844 static int mt7988_fixed_pll_probe(struct udevice *dev)
 845 {
 846         return mtk_common_clk_init(dev, &mt7988_fixed_pll_clk_tree);
 847 }
 848
 849 static int mt7988_topckgen_probe(struct udevice *dev)
 850 {
 851         struct mtk_clk_priv *priv = dev_get_priv(dev);
 852
 853         priv->base = dev_read_addr_ptr(dev);
 854         if (!priv->base)
 855                 return -ENOENT;
 856
 857         writel(MT7988_CLK_PDN_EN_WRITE, priv->base + MT7988_CLK_PDN);
 858         return mtk_common_clk_init(dev, &mt7988_topckgen_clk_tree);
 859 }
 860
 861 U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
 862         .name = "mt7988-clock-fixed-pll",
 863         .id = UCLASS_CLK,
 864         .of_match = mt7988_fixed_pll_compat,
 865         .probe = mt7988_fixed_pll_probe,
 866         .priv_auto = sizeof(struct mtk_clk_priv),
 867         .ops = &mtk_clk_topckgen_ops,
 868         .flags = DM_FLAG_PRE_RELOC,
 869 };
 870
 871 U_BOOT_DRIVER(mtk_clk_topckgen) = {
 872         .name = "mt7988-clock-topckgen",
 873         .id = UCLASS_CLK,
 874         .of_match = mt7988_topckgen_compat,
 875         .probe = mt7988_topckgen_probe,
 876         .priv_auto = sizeof(struct mtk_clk_priv),
 877         .ops = &mtk_clk_topckgen_ops,
 878         .flags = DM_FLAG_PRE_RELOC,
 879 };
 880
 881 static const struct udevice_id mt7988_infracfg_compat[] = {
 882         { .compatible = "mediatek,mt7988-infracfg" },
 883         {}
 884 };
 885
 886 static const struct udevice_id mt7988_infracfg_ao_cgs_compat[] = {
 887         { .compatible = "mediatek,mt7988-infracfg_ao_cgs" },
 888         {}
 889 };
 890
 891 static int mt7988_infracfg_probe(struct udevice *dev)
 892 {
 893         return mtk_common_clk_init(dev, &mt7988_infracfg_clk_tree);
 894 }
 895
 896 static int mt7988_infracfg_ao_cgs_probe(struct udevice *dev)
 897 {
 898         return mtk_common_clk_gate_init(dev, &mt7988_infracfg_clk_tree,
 899                                         infracfg_mtk_gates);
 900 }
 901
 902 U_BOOT_DRIVER(mtk_clk_infracfg) = {
 903         .name = "mt7988-clock-infracfg",
 904         .id = UCLASS_CLK,
 905         .of_match = mt7988_infracfg_compat,
 906         .probe = mt7988_infracfg_probe,
 907         .priv_auto = sizeof(struct mtk_clk_priv),
 908         .ops = &mtk_clk_infrasys_ops,
 909         .flags = DM_FLAG_PRE_RELOC,
 910 };
 911
 912 U_BOOT_DRIVER(mtk_clk_infracfg_ao_cgs) = {
 913         .name = "mt7988-clock-infracfg_ao_cgs",
 914         .id = UCLASS_CLK,
 915         .of_match = mt7988_infracfg_ao_cgs_compat,
 916         .probe = mt7988_infracfg_ao_cgs_probe,
 917         .priv_auto = sizeof(struct mtk_cg_priv),
 918         .ops = &mtk_clk_gate_ops,
 919         .flags = DM_FLAG_PRE_RELOC,
 920 };
 921
 922 /* ETHDMA */
 923
 924 static const struct mtk_gate_regs ethdma_cg_regs = {
 925         .set_ofs = 0x30,
 926         .clr_ofs = 0x30,
 927         .sta_ofs = 0x30,
 928 };
 929
 930 #define GATE_ETHDMA(_id, _name, _parent, _shift)                               \
 931         {                                                                      \
 932                 .id = _id, .parent = _parent, .regs = &ethdma_cg_regs,         \
 933                 .shift = _shift,                                               \
 934                 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,         \
 935         }
 936
 937 static const struct mtk_gate ethdma_mtk_gate[] = {
 938         GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", CK_TOP_NETSYS_2X, 6),
 939 };
 940
 941 static int mt7988_ethdma_probe(struct udevice *dev)
 942 {
 943         return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
 944                                         ethdma_mtk_gate);
 945 }
 946
 947 static int mt7988_ethdma_bind(struct udevice *dev)
 948 {
 949         int ret = 0;
 950
 951         if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
 952                 ret = mediatek_reset_bind(dev, MT7988_ETHDMA_RST_CTRL_OFS, 1);
 953                 if (ret)
 954                         debug("Warning: failed to bind reset controller\n");
 955         }
 956
 957         return ret;
 958 }
 959
 960 static const struct udevice_id mt7988_ethdma_compat[] = {
 961         {
 962                 .compatible = "mediatek,mt7988-ethdma",
 963         },
 964         {}
 965 };
 966
 967 U_BOOT_DRIVER(mtk_clk_ethdma) = {
 968         .name = "mt7988-clock-ethdma",
 969         .id = UCLASS_CLK,
 970         .of_match = mt7988_ethdma_compat,
 971         .probe = mt7988_ethdma_probe,
 972         .bind = mt7988_ethdma_bind,
 973         .priv_auto = sizeof(struct mtk_cg_priv),
 974         .ops = &mtk_clk_gate_ops,
 975 };
 976
 977 /* SGMIISYS_0 */
 978
 979 static const struct mtk_gate_regs sgmii0_cg_regs = {
 980         .set_ofs = 0xE4,
 981         .clr_ofs = 0xE4,
 982         .sta_ofs = 0xE4,
 983 };
 984
 985 #define GATE_SGMII0(_id, _name, _parent, _shift)                               \
 986         {                                                                      \
 987                 .id = _id, .parent = _parent, .regs = &sgmii0_cg_regs,         \
 988                 .shift = _shift,                                               \
 989                 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,         \
 990         }
 991
 992 static const struct mtk_gate sgmiisys_0_mtk_gate[] = {
 993         /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
 994         GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", CK_TOP_CB_CKSQ_40M, 2),
 995         /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
 996         GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", CK_TOP_CB_CKSQ_40M, 3),
 997 };
 998
 999 static int mt7988_sgmiisys_0_probe(struct udevice *dev)
1000 {
1001         return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
1002                                         sgmiisys_0_mtk_gate);
1003 }
1004
1005 static const struct udevice_id mt7988_sgmiisys_0_compat[] = {
1006         {
1007                 .compatible = "mediatek,mt7988-sgmiisys_0",
1008         },
1009         {}
1010 };
1011
1012 U_BOOT_DRIVER(mtk_clk_sgmiisys_0) = {
1013         .name = "mt7988-clock-sgmiisys_0",
1014         .id = UCLASS_CLK,
1015         .of_match = mt7988_sgmiisys_0_compat,
1016         .probe = mt7988_sgmiisys_0_probe,
1017         .priv_auto = sizeof(struct mtk_cg_priv),
1018         .ops = &mtk_clk_gate_ops,
1019 };
1020
1021 /* SGMIISYS_1 */
1022
1023 static const struct mtk_gate_regs sgmii1_cg_regs = {
1024         .set_ofs = 0xE4,
1025         .clr_ofs = 0xE4,
1026         .sta_ofs = 0xE4,
1027 };
1028
1029 #define GATE_SGMII1(_id, _name, _parent, _shift)                               \
1030         {                                                                      \
1031                 .id = _id, .parent = _parent, .regs = &sgmii1_cg_regs,         \
1032                 .shift = _shift,                                               \
1033                 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,         \
1034         }
1035
1036 static const struct mtk_gate sgmiisys_1_mtk_gate[] = {
1037         /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
1038         GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", CK_TOP_CB_CKSQ_40M, 2),
1039         /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
1040         GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", CK_TOP_CB_CKSQ_40M, 3),
1041 };
1042
1043 static int mt7988_sgmiisys_1_probe(struct udevice *dev)
1044 {
1045         return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
1046                                         sgmiisys_1_mtk_gate);
1047 }
1048
1049 static const struct udevice_id mt7988_sgmiisys_1_compat[] = {
1050         {
1051                 .compatible = "mediatek,mt7988-sgmiisys_1",
1052         },
1053         {}
1054 };
1055
1056 U_BOOT_DRIVER(mtk_clk_sgmiisys_1) = {
1057         .name = "mt7988-clock-sgmiisys_1",
1058         .id = UCLASS_CLK,
1059         .of_match = mt7988_sgmiisys_1_compat,
1060         .probe = mt7988_sgmiisys_1_probe,
1061         .priv_auto = sizeof(struct mtk_cg_priv),
1062         .ops = &mtk_clk_gate_ops,
1063 };
1064
1065 /* ETHWARP */
1066
1067 static const struct mtk_gate_regs ethwarp_cg_regs = {
1068         .set_ofs = 0x14,
1069         .clr_ofs = 0x14,
1070         .sta_ofs = 0x14,
1071 };
1072
1073 #define GATE_ETHWARP(_id, _name, _parent, _shift)                              \
1074         {                                                                      \
1075                 .id = _id, .parent = _parent, .regs = &ethwarp_cg_regs,        \
1076                 .shift = _shift,                                               \
1077                 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,         \
1078         }
1079
1080 static const struct mtk_gate ethwarp_mtk_gate[] = {
1081         GATE_ETHWARP(CK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
1082                      CK_TOP_NETSYS_WED_MCU, 13),
1083         GATE_ETHWARP(CK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
1084                      CK_TOP_NETSYS_WED_MCU, 14),
1085         GATE_ETHWARP(CK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
1086                      CK_TOP_NETSYS_WED_MCU, 15),
1087 };
1088
1089 static int mt7988_ethwarp_probe(struct udevice *dev)
1090 {
1091         return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
1092                                         ethwarp_mtk_gate);
1093 }
1094
1095 static int mt7988_ethwarp_bind(struct udevice *dev)
1096 {
1097         int ret = 0;
1098
1099         if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
1100                 ret = mediatek_reset_bind(dev, MT7988_ETHWARP_RST_CTRL_OFS, 2);
1101                 if (ret)
1102                         debug("Warning: failed to bind reset controller\n");
1103         }
1104
1105         return ret;
1106 }
1107
1108 static const struct udevice_id mt7988_ethwarp_compat[] = {
1109         {
1110                 .compatible = "mediatek,mt7988-ethwarp",
1111         },
1112         {}
1113 };
1114
1115 U_BOOT_DRIVER(mtk_clk_ethwarp) = {
1116         .name = "mt7988-clock-ethwarp",
1117         .id = UCLASS_CLK,
1118         .of_match = mt7988_ethwarp_compat,
1119         .probe = mt7988_ethwarp_probe,
1120         .bind = mt7988_ethwarp_bind,
1121         .priv_auto = sizeof(struct mtk_cg_priv),
1122         .ops = &mtk_clk_gate_ops,
1123 };