drivers/clk/mediatek/clk-mt7629.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MediaTek clock driver for MT7629 SoC
   4  *
   5  * Copyright (C) 2018 MediaTek Inc.
   6  * Author: Ryder Lee <ryder.lee@mediatek.com>
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <log.h>
  12 #include <asm/arch-mediatek/reset.h>
  13 #include <asm/io.h>
  14 #include <dt-bindings/clock/mt7629-clk.h>
  15
  16 #include "clk-mtk.h"
  17
  18 #define MT7629_CLKSQ_STB_CON0           0x20
  19 #define MT7629_PLL_ISO_CON0             0x2c
  20 #define MT7629_PLL_FMAX                 (2500UL * MHZ)
  21 #define MT7629_CON0_RST_BAR             BIT(24)
  22
  23 #define MCU_AXI_DIV                     0x640
  24 #define AXI_DIV_MSK                     GENMASK(4, 0)
  25 #define AXI_DIV_SEL(x)                  (x)
  26
  27 #define MCU_BUS_MUX                     0x7c0
  28 #define MCU_BUS_MSK                     GENMASK(10, 9)
  29 #define MCU_BUS_SEL(x)                  ((x) << 9)
  30
  31 /* apmixedsys */
  32 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,   \
  33             _pd_shift, _pcw_reg, _pcw_shift) {                          \
  34                 .id = _id,                                              \
  35                 .reg = _reg,                                            \
  36                 .pwr_reg = _pwr_reg,                                    \
  37                 .en_mask = _en_mask,                                    \
  38                 .rst_bar_mask = MT7629_CON0_RST_BAR,                    \
  39                 .fmax = MT7629_PLL_FMAX,                                \
  40                 .flags = _flags,                                        \
  41                 .pcwbits = _pcwbits,                                    \
  42                 .pd_reg = _pd_reg,                                      \
  43                 .pd_shift = _pd_shift,                                  \
  44                 .pcw_reg = _pcw_reg,                                    \
  45                 .pcw_shift = _pcw_shift,                                \
  46         }
  47
  48 static const struct mtk_pll_data apmixed_plls[] = {
  49         PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
  50             21, 0x204, 24, 0x204, 0),
  51         PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
  52             21, 0x214, 24, 0x214, 0),
  53         PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
  54             7, 0x224, 24, 0x224, 14),
  55         PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
  56             21, 0x300, 1, 0x304, 0),
  57         PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
  58             21, 0x314, 1, 0x318, 0),
  59         PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
  60             21, 0x358, 1, 0x35c, 0),
  61 };
  62
  63 /* topckgen */
  64 #define FACTOR0(_id, _parent, _mult, _div)                      \
  65         FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
  66
  67 #define FACTOR1(_id, _parent, _mult, _div)                      \
  68         FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
  69
  70 #define FACTOR2(_id, _parent, _mult, _div)                      \
  71         FACTOR(_id, _parent, _mult, _div, 0)
  72
  73 static const struct mtk_fixed_clk top_fixed_clks[] = {
  74         FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000),
  75         FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000),
  76         FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000),
  77         FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000),
  78         FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000),
  79         FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000),
  80         FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333),
  81         FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000),
  82         FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000),
  83         FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000),
  84 };
  85
  86 static const struct mtk_fixed_factor top_fixed_divs[] = {
  87         FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4),
  88         FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
  89         FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125),
  90         FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
  91         FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1),
  92         FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1),
  93         FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024),
  94         FACTOR2(CLK_TOP_PWM_QTR_26M, CLK_XTAL, 1, 1),
  95         FACTOR2(CLK_TOP_CPUM_TCK_IN, CLK_XTAL, 1, 1),
  96         FACTOR2(CLK_TOP_TO_USB3_DA_TOP, CLK_XTAL, 1, 1),
  97         FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1),
  98         FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
  99         FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_MEMPLL, 1, 4),
 100         FACTOR1(CLK_TOP_DMPLL_D8, CLK_TOP_MEMPLL, 1, 8),
 101         FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
 102         FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
 103         FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
 104         FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
 105         FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32),
 106         FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6),
 107         FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
 108         FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
 109         FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
 110         FACTOR0(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10),
 111         FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20),
 112         FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
 113         FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
 114         FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28),
 115         FACTOR0(CLK_TOP_SYSPLL4_D16, CLK_APMIXED_MAINPLL, 1, 112),
 116         FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2),
 117         FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
 118         FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
 119         FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
 120         FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3),
 121         FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
 122         FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
 123         FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
 124         FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL, 1, 48),
 125         FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
 126         FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10),
 127         FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20),
 128         FACTOR1(CLK_TOP_UNIVPLL3_D16, CLK_TOP_UNIVPLL, 1, 80),
 129         FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7),
 130         FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320),
 131         FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25),
 132         FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2),
 133         FACTOR2(CLK_TOP_CLKXTAL_D4, CLK_XTAL, 1, 4),
 134         FACTOR1(CLK_TOP_HD_FAXI, CLK_TOP_AXI_SEL, 1, 1),
 135         FACTOR1(CLK_TOP_FAXI, CLK_TOP_AXI_SEL, 1, 1),
 136         FACTOR1(CLK_TOP_F_FAUD_INTBUS, CLK_TOP_AUD_INTBUS_SEL, 1, 1),
 137         FACTOR1(CLK_TOP_AP2WBHIF_HCLK, CLK_TOP_SYSPLL1_D8, 1, 1),
 138         FACTOR1(CLK_TOP_10M_INFRAO, CLK_TOP_10M_SEL, 1, 1),
 139         FACTOR1(CLK_TOP_MSDC30_1, CLK_TOP_MSDC30_1, 1, 1),
 140         FACTOR1(CLK_TOP_SPI, CLK_TOP_SPI0_SEL, 1, 1),
 141         FACTOR1(CLK_TOP_SF, CLK_TOP_NFI_INFRA_SEL, 1, 1),
 142         FACTOR1(CLK_TOP_FLASH, CLK_TOP_FLASH_SEL, 1, 1),
 143         FACTOR1(CLK_TOP_TO_USB3_REF, CLK_TOP_SATA_SEL, 1, 4),
 144         FACTOR1(CLK_TOP_TO_USB3_MCU, CLK_TOP_AXI_SEL, 1, 1),
 145         FACTOR1(CLK_TOP_TO_USB3_DMA, CLK_TOP_HIF_SEL, 1, 1),
 146         FACTOR1(CLK_TOP_FROM_TOP_AHB, CLK_TOP_AXI_SEL, 1, 1),
 147         FACTOR1(CLK_TOP_FROM_TOP_AXI, CLK_TOP_HIF_SEL, 1, 1),
 148         FACTOR1(CLK_TOP_PCIE1_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
 149         FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
 150 };
 151
 152 static const int axi_parents[] = {
 153         CLK_XTAL,
 154         CLK_TOP_SYSPLL1_D2,
 155         CLK_TOP_SYSPLL_D5,
 156         CLK_TOP_SYSPLL1_D4,
 157         CLK_TOP_UNIVPLL_D5,
 158         CLK_TOP_UNIVPLL2_D2,
 159         CLK_TOP_UNIVPLL_D7,
 160         CLK_TOP_DMPLL
 161 };
 162
 163 static const int mem_parents[] = {
 164         CLK_XTAL,
 165         CLK_TOP_DMPLL
 166 };
 167
 168 static const int ddrphycfg_parents[] = {
 169         CLK_XTAL,
 170         CLK_TOP_SYSPLL1_D8
 171 };
 172
 173 static const int eth_parents[] = {
 174         CLK_XTAL,
 175         CLK_TOP_SYSPLL1_D2,
 176         CLK_TOP_UNIVPLL1_D2,
 177         CLK_TOP_SYSPLL1_D4,
 178         CLK_TOP_UNIVPLL_D5,
 179         CLK_TOP_SGMIIPLL_D2,
 180         CLK_TOP_UNIVPLL_D7,
 181         CLK_TOP_DMPLL
 182 };
 183
 184 static const int pwm_parents[] = {
 185         CLK_XTAL,
 186         CLK_TOP_UNIVPLL2_D4
 187 };
 188
 189 static const int f10m_ref_parents[] = {
 190         CLK_XTAL,
 191         CLK_TOP_SGMIIPLL_D2
 192 };
 193
 194 static const int nfi_infra_parents[] = {
 195         CLK_XTAL,
 196         CLK_XTAL,
 197         CLK_XTAL,
 198         CLK_XTAL,
 199         CLK_XTAL,
 200         CLK_XTAL,
 201         CLK_TOP_UNIVPLL2_D8,
 202         CLK_TOP_UNIVPLL3_D4,
 203         CLK_TOP_SYSPLL1_D8,
 204         CLK_TOP_UNIVPLL1_D8,
 205         CLK_TOP_SYSPLL4_D2,
 206         CLK_TOP_SYSPLL2_D4,
 207         CLK_TOP_UNIVPLL2_D4,
 208         CLK_TOP_UNIVPLL3_D2,
 209         CLK_TOP_SYSPLL1_D4,
 210         CLK_TOP_SYSPLL_D7
 211 };
 212
 213 static const int flash_parents[] = {
 214         CLK_XTAL,
 215         CLK_TOP_UNIVPLL_D80_D4,
 216         CLK_TOP_SYSPLL2_D8,
 217         CLK_TOP_SYSPLL3_D4,
 218         CLK_TOP_UNIVPLL3_D4,
 219         CLK_TOP_UNIVPLL1_D8,
 220         CLK_TOP_SYSPLL2_D4,
 221         CLK_TOP_UNIVPLL2_D4
 222 };
 223
 224 static const int uart_parents[] = {
 225         CLK_XTAL,
 226         CLK_TOP_UNIVPLL2_D8
 227 };
 228
 229 static const int spi0_parents[] = {
 230         CLK_XTAL,
 231         CLK_TOP_SYSPLL3_D2,
 232         CLK_XTAL,
 233         CLK_TOP_SYSPLL2_D4,
 234         CLK_TOP_SYSPLL4_D2,
 235         CLK_TOP_UNIVPLL2_D4,
 236         CLK_TOP_UNIVPLL1_D8,
 237         CLK_XTAL
 238 };
 239
 240 static const int spi1_parents[] = {
 241         CLK_XTAL,
 242         CLK_TOP_SYSPLL3_D2,
 243         CLK_XTAL,
 244         CLK_TOP_SYSPLL4_D4,
 245         CLK_TOP_SYSPLL4_D2,
 246         CLK_TOP_UNIVPLL2_D4,
 247         CLK_TOP_UNIVPLL1_D8,
 248         CLK_XTAL
 249 };
 250
 251 static const int msdc30_0_parents[] = {
 252         CLK_XTAL,
 253         CLK_TOP_UNIVPLL2_D16,
 254         CLK_TOP_UNIV48M
 255 };
 256
 257 static const int msdc30_1_parents[] = {
 258         CLK_XTAL,
 259         CLK_TOP_UNIVPLL2_D16,
 260         CLK_TOP_UNIV48M,
 261         CLK_TOP_SYSPLL2_D4,
 262         CLK_TOP_UNIVPLL2_D4,
 263         CLK_TOP_SYSPLL_D7,
 264         CLK_TOP_SYSPLL2_D2,
 265         CLK_TOP_UNIVPLL2_D2
 266 };
 267
 268 static const int ap2wbmcu_parents[] = {
 269         CLK_XTAL,
 270         CLK_TOP_SYSPLL1_D2,
 271         CLK_TOP_UNIV48M,
 272         CLK_TOP_SYSPLL1_D8,
 273         CLK_TOP_UNIVPLL2_D4,
 274         CLK_TOP_SYSPLL_D7,
 275         CLK_TOP_SYSPLL2_D2,
 276         CLK_TOP_UNIVPLL2_D2
 277 };
 278
 279 static const int audio_parents[] = {
 280         CLK_XTAL,
 281         CLK_TOP_SYSPLL3_D4,
 282         CLK_TOP_SYSPLL4_D4,
 283         CLK_TOP_SYSPLL1_D16
 284 };
 285
 286 static const int aud_intbus_parents[] = {
 287         CLK_XTAL,
 288         CLK_TOP_SYSPLL1_D4,
 289         CLK_TOP_SYSPLL4_D2,
 290         CLK_TOP_DMPLL_D4
 291 };
 292
 293 static const int pmicspi_parents[] = {
 294         CLK_XTAL,
 295         CLK_TOP_SYSPLL1_D8,
 296         CLK_TOP_SYSPLL3_D4,
 297         CLK_TOP_SYSPLL1_D16,
 298         CLK_TOP_UNIVPLL3_D4,
 299         CLK_XTAL,
 300         CLK_TOP_UNIVPLL2_D4,
 301         CLK_TOP_DMPLL_D8
 302 };
 303
 304 static const int scp_parents[] = {
 305         CLK_XTAL,
 306         CLK_TOP_SYSPLL1_D8,
 307         CLK_TOP_UNIVPLL2_D2,
 308         CLK_TOP_UNIVPLL2_D4
 309 };
 310
 311 static const int atb_parents[] = {
 312         CLK_XTAL,
 313         CLK_TOP_SYSPLL1_D2,
 314         CLK_TOP_SYSPLL_D5
 315 };
 316
 317 static const int hif_parents[] = {
 318         CLK_XTAL,
 319         CLK_TOP_SYSPLL1_D2,
 320         CLK_TOP_UNIVPLL1_D2,
 321         CLK_TOP_SYSPLL1_D4,
 322         CLK_TOP_UNIVPLL_D5,
 323         -1,
 324         CLK_TOP_UNIVPLL_D7
 325 };
 326
 327 static const int sata_parents[] = {
 328         CLK_XTAL,
 329         CLK_TOP_UNIVPLL2_D4
 330 };
 331
 332 static const int usb20_parents[] = {
 333         CLK_XTAL,
 334         CLK_TOP_UNIVPLL3_D4,
 335         CLK_TOP_SYSPLL1_D8
 336 };
 337
 338 static const int aud1_parents[] = {
 339         CLK_XTAL
 340 };
 341
 342 static const int irrx_parents[] = {
 343         CLK_XTAL,
 344         CLK_TOP_SYSPLL4_D16
 345 };
 346
 347 static const int crypto_parents[] = {
 348         CLK_XTAL,
 349         CLK_TOP_UNIVPLL_D3,
 350         CLK_TOP_UNIVPLL1_D2,
 351         CLK_TOP_SYSPLL1_D2,
 352         CLK_TOP_UNIVPLL_D5,
 353         CLK_TOP_SYSPLL_D5,
 354         CLK_TOP_UNIVPLL2_D2,
 355         CLK_TOP_SYSPLL_D2
 356 };
 357
 358 static const int gpt10m_parents[] = {
 359         CLK_XTAL,
 360         CLK_TOP_CLKXTAL_D4
 361 };
 362
 363 static const struct mtk_composite top_muxes[] = {
 364         /* CLK_CFG_0 */
 365         MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
 366         MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
 367         MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
 368         MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
 369
 370         /* CLK_CFG_1 */
 371         MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
 372         MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
 373         MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
 374         MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
 375
 376         /* CLK_CFG_2 */
 377         MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
 378         MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
 379         MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23),
 380         MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31),
 381
 382         /* CLK_CFG_3 */
 383         MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
 384         MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x70, 8, 3, 15),
 385         MUX_GATE(CLK_TOP_AP2WBMCU_SEL, ap2wbmcu_parents, 0x70, 16, 3, 23),
 386         MUX_GATE(CLK_TOP_AP2WBHIF_SEL, ap2wbmcu_parents, 0x70, 24, 3, 31),
 387
 388         /* CLK_CFG_4 */
 389         MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x80, 0, 2, 7),
 390         MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15),
 391         MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23),
 392         MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 24, 2, 31),
 393
 394         /* CLK_CFG_5 */
 395         MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
 396         MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15,
 397                        CLK_DOMAIN_SCPSYS),
 398         MUX_GATE(CLK_TOP_SATA_SEL, sata_parents, 0x90, 16, 1, 23),
 399         MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),
 400
 401         /* CLK_CFG_6 */
 402         MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
 403         MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15),
 404         MUX_GATE(CLK_TOP_IRRX_SEL, irrx_parents, 0xA0, 16, 1, 23),
 405         MUX_GATE(CLK_TOP_IRTX_SEL, irrx_parents, 0xA0, 24, 1, 31),
 406
 407         /* CLK_CFG_7 */
 408         MUX_GATE(CLK_TOP_SATA_MCU_SEL, scp_parents, 0xB0, 0, 2, 7),
 409         MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, scp_parents, 0xB0, 8, 2, 15),
 410         MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, scp_parents, 0xB0, 16, 2, 23),
 411         MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, scp_parents, 0xB0, 24, 2, 31),
 412
 413         /* CLK_CFG_8 */
 414         MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7),
 415         MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, f10m_ref_parents, 0xC0, 8, 1, 15),
 416         MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23),
 417 };
 418
 419 /* infracfg */
 420 static const struct mtk_gate_regs infra_cg_regs = {
 421         .set_ofs = 0x40,
 422         .clr_ofs = 0x44,
 423         .sta_ofs = 0x48,
 424 };
 425
 426 #define GATE_INFRA(_id, _parent, _shift) {                      \
 427                 .id = _id,                                      \
 428                 .parent = _parent,                              \
 429                 .regs = &infra_cg_regs,                         \
 430                 .shift = _shift,                                \
 431                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
 432         }
 433
 434 static const struct mtk_gate infra_cgs[] = {
 435         GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_HD_FAXI, 0),
 436         GATE_INFRA(CLK_INFRA_TRNG_PD, CLK_TOP_HD_FAXI, 2),
 437         GATE_INFRA(CLK_INFRA_DEVAPC_PD, CLK_TOP_HD_FAXI, 4),
 438         GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_10M_INFRAO, 18),
 439         GATE_INFRA(CLK_INFRA_SEJ_PD, CLK_TOP_10M_INFRAO, 19),
 440 };
 441
 442 /* pericfg */
 443 static const struct mtk_gate_regs peri0_cg_regs = {
 444         .set_ofs = 0x8,
 445         .clr_ofs = 0x10,
 446         .sta_ofs = 0x18,
 447 };
 448
 449 static const struct mtk_gate_regs peri1_cg_regs = {
 450         .set_ofs = 0xC,
 451         .clr_ofs = 0x14,
 452         .sta_ofs = 0x1C,
 453 };
 454
 455 #define GATE_PERI0(_id, _parent, _shift) {                      \
 456                 .id = _id,                                      \
 457                 .parent = _parent,                              \
 458                 .regs = &peri0_cg_regs,                         \
 459                 .shift = _shift,                                \
 460                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
 461         }
 462
 463 #define GATE_PERI1(_id, _parent, _shift) {                      \
 464                 .id = _id,                                      \
 465                 .parent = _parent,                              \
 466                 .regs = &peri1_cg_regs,                         \
 467                 .shift = _shift,                                \
 468                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
 469         }
 470
 471 static const struct mtk_gate peri_cgs[] = {
 472         GATE_PERI0(CLK_PERI_PWM1_PD, CLK_TOP_PWM_QTR_26M, 2),
 473         GATE_PERI0(CLK_PERI_PWM2_PD, CLK_TOP_PWM_QTR_26M, 3),
 474         GATE_PERI0(CLK_PERI_PWM3_PD, CLK_TOP_PWM_QTR_26M, 4),
 475         GATE_PERI0(CLK_PERI_PWM4_PD, CLK_TOP_PWM_QTR_26M, 5),
 476         GATE_PERI0(CLK_PERI_PWM5_PD, CLK_TOP_PWM_QTR_26M, 6),
 477         GATE_PERI0(CLK_PERI_PWM6_PD, CLK_TOP_PWM_QTR_26M, 7),
 478         GATE_PERI0(CLK_PERI_PWM7_PD, CLK_TOP_PWM_QTR_26M, 8),
 479         GATE_PERI0(CLK_PERI_PWM_PD, CLK_TOP_PWM_QTR_26M, 9),
 480         GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_FAXI, 12),
 481         GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1, 14),
 482         GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_FAXI, 17),
 483         GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_FAXI, 18),
 484         GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_FAXI, 19),
 485         GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_FAXI, 20),
 486         GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_FAXI, 22),
 487         GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_FAXI, 23),
 488         GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI, 28),
 489         GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_SF, 29),
 490         GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_FAXI, 30),
 491         GATE_PERI0(CLK_PERI_NFIECC_PD, CLK_TOP_FAXI, 31),
 492         GATE_PERI1(CLK_PERI_FLASH_PD, CLK_TOP_FLASH, 1),
 493 };
 494
 495 /* ethsys */
 496 static const struct mtk_gate_regs eth_cg_regs = {
 497         .sta_ofs = 0x30,
 498 };
 499
 500 #define GATE_ETH(_id, _parent, _shift, _flag) {                 \
 501                 .id = _id,                                      \
 502                 .parent = _parent,                              \
 503                 .regs = &eth_cg_regs,                           \
 504                 .shift = _shift,                                \
 505                 .flags = CLK_GATE_NO_SETCLR_INV | (_flag),      \
 506         }
 507
 508 #define GATE_ETH0(_id, _parent, _shift)                         \
 509         GATE_ETH(_id, _parent, _shift, CLK_PARENT_APMIXED)
 510
 511 #define GATE_ETH1(_id, _parent, _shift)                         \
 512         GATE_ETH(_id, _parent, _shift, CLK_PARENT_TOPCKGEN)
 513
 514 static const struct mtk_gate eth_cgs[] = {
 515         GATE_ETH0(CLK_ETH_FE_EN, CLK_APMIXED_ETH2PLL, 6),
 516         GATE_ETH1(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7),
 517         GATE_ETH1(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8),
 518         GATE_ETH1(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
 519         GATE_ETH1(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 16),
 520 };
 521
 522 static const struct mtk_gate_regs sgmii_cg_regs = {
 523         .set_ofs = 0xE4,
 524         .clr_ofs = 0xE4,
 525         .sta_ofs = 0xE4,
 526 };
 527
 528 #define GATE_SGMII(_id, _parent, _shift) {                      \
 529         .id = _id,                                              \
 530         .parent = _parent,                                      \
 531         .regs = &sgmii_cg_regs,                                 \
 532         .shift = _shift,                                        \
 533         .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,  \
 534 }
 535
 536 static const struct mtk_gate sgmii_cgs[] = {
 537         GATE_SGMII(CLK_SGMII_TX_EN, CLK_TOP_SSUSB_TX250M, 2),
 538         GATE_SGMII(CLK_SGMII_RX_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
 539         GATE_SGMII(CLK_SGMII_CDR_REF, CLK_TOP_SSUSB_CDR_REF, 4),
 540         GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
 541 };
 542
 543 static const struct mtk_gate_regs ssusb_cg_regs = {
 544         .set_ofs = 0x30,
 545         .clr_ofs = 0x30,
 546         .sta_ofs = 0x30,
 547 };
 548
 549 #define GATE_SSUSB(_id, _parent, _shift) {                      \
 550         .id = _id,                                              \
 551         .parent = _parent,                                      \
 552         .regs = &ssusb_cg_regs,                                 \
 553         .shift = _shift,                                        \
 554         .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,  \
 555 }
 556
 557 static const struct mtk_gate ssusb_cgs[] = {
 558         GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0),
 559         GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1),
 560         GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5),
 561         GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6),
 562         GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_TO_USB3_MCU, 7),
 563         GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_TO_USB3_DMA, 8),
 564 };
 565
 566 static const struct mtk_clk_tree mt7629_clk_tree = {
 567         .xtal_rate = 40 * MHZ,
 568         .xtal2_rate = 20 * MHZ,
 569         .fdivs_offs = CLK_TOP_TO_USB3_SYS,
 570         .muxes_offs = CLK_TOP_AXI_SEL,
 571         .plls = apmixed_plls,
 572         .fclks = top_fixed_clks,
 573         .fdivs = top_fixed_divs,
 574         .muxes = top_muxes,
 575 };
 576
 577 static int mt7629_mcucfg_probe(struct udevice *dev)
 578 {
 579         void __iomem *base;
 580
 581         base = dev_read_addr_ptr(dev);
 582         if (!base)
 583                 return -ENOENT;
 584
 585         clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
 586                         AXI_DIV_SEL(0x12));
 587         clrsetbits_le32(base + MCU_BUS_MUX, MCU_BUS_MSK,
 588                         MCU_BUS_SEL(0x1));
 589
 590         return 0;
 591 }
 592
 593 static int mt7629_apmixedsys_probe(struct udevice *dev)
 594 {
 595         struct mtk_clk_priv *priv = dev_get_priv(dev);
 596         int ret;
 597
 598         ret = mtk_common_clk_init(dev, &mt7629_clk_tree);
 599         if (ret)
 600                 return ret;
 601
 602         /* reduce clock square disable time */
 603         writel(0x501, priv->base + MT7629_CLKSQ_STB_CON0);
 604         /* extend pwr/iso control timing to 1us */
 605         writel(0x80008, priv->base + MT7629_PLL_ISO_CON0);
 606
 607         return 0;
 608 }
 609
 610 static int mt7629_topckgen_probe(struct udevice *dev)
 611 {
 612         return mtk_common_clk_init(dev, &mt7629_clk_tree);
 613 }
 614
 615 static int mt7629_infracfg_probe(struct udevice *dev)
 616 {
 617         return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, infra_cgs);
 618 }
 619
 620 static int mt7629_pericfg_probe(struct udevice *dev)
 621 {
 622         return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, peri_cgs);
 623 }
 624
 625 static int mt7629_ethsys_probe(struct udevice *dev)
 626 {
 627         return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, eth_cgs);
 628 }
 629
 630 static int mt7629_ethsys_bind(struct udevice *dev)
 631 {
 632         int ret = 0;
 633
 634 #if CONFIG_IS_ENABLED(RESET_MEDIATEK)
 635         ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
 636         if (ret)
 637                 debug("Warning: failed to bind reset controller\n");
 638 #endif
 639
 640         return ret;
 641 }
 642
 643 static int mt7629_sgmiisys_probe(struct udevice *dev)
 644 {
 645         return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs);
 646 }
 647
 648 static int mt7629_ssusbsys_probe(struct udevice *dev)
 649 {
 650         return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, ssusb_cgs);
 651 }
 652
 653 static const struct udevice_id mt7629_apmixed_compat[] = {
 654         { .compatible = "mediatek,mt7629-apmixedsys" },
 655         { }
 656 };
 657
 658 static const struct udevice_id mt7629_topckgen_compat[] = {
 659         { .compatible = "mediatek,mt7629-topckgen" },
 660         { }
 661 };
 662
 663 static const struct udevice_id mt7629_infracfg_compat[] = {
 664         { .compatible = "mediatek,mt7629-infracfg", },
 665         { }
 666 };
 667
 668 static const struct udevice_id mt7629_pericfg_compat[] = {
 669         { .compatible = "mediatek,mt7629-pericfg", },
 670         { }
 671 };
 672
 673 static const struct udevice_id mt7629_ethsys_compat[] = {
 674         { .compatible = "mediatek,mt7629-ethsys", },
 675         { }
 676 };
 677
 678 static const struct udevice_id mt7629_sgmiisys_compat[] = {
 679         { .compatible = "mediatek,mt7629-sgmiisys", },
 680         { }
 681 };
 682
 683 static const struct udevice_id mt7629_ssusbsys_compat[] = {
 684         { .compatible = "mediatek,mt7629-ssusbsys" },
 685         { }
 686 };
 687
 688 static const struct udevice_id mt7629_mcucfg_compat[] = {
 689         { .compatible = "mediatek,mt7629-mcucfg" },
 690         { }
 691 };
 692
 693 U_BOOT_DRIVER(mtk_mcucfg) = {
 694         .name = "mt7629-mcucfg",
 695         .id = UCLASS_SYSCON,
 696         .of_match = mt7629_mcucfg_compat,
 697         .probe = mt7629_mcucfg_probe,
 698         .flags = DM_FLAG_PRE_RELOC,
 699 };
 700
 701 U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
 702         .name = "mt7629-clock-apmixedsys",
 703         .id = UCLASS_CLK,
 704         .of_match = mt7629_apmixed_compat,
 705         .probe = mt7629_apmixedsys_probe,
 706         .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
 707         .ops = &mtk_clk_apmixedsys_ops,
 708         .flags = DM_FLAG_PRE_RELOC,
 709 };
 710
 711 U_BOOT_DRIVER(mtk_clk_topckgen) = {
 712         .name = "mt7629-clock-topckgen",
 713         .id = UCLASS_CLK,
 714         .of_match = mt7629_topckgen_compat,
 715         .probe = mt7629_topckgen_probe,
 716         .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
 717         .ops = &mtk_clk_topckgen_ops,
 718         .flags = DM_FLAG_PRE_RELOC,
 719 };
 720
 721 U_BOOT_DRIVER(mtk_clk_infracfg) = {
 722         .name = "mt7629-clock-infracfg",
 723         .id = UCLASS_CLK,
 724         .of_match = mt7629_infracfg_compat,
 725         .probe = mt7629_infracfg_probe,
 726         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 727         .ops = &mtk_clk_gate_ops,
 728         .flags = DM_FLAG_PRE_RELOC,
 729 };
 730
 731 U_BOOT_DRIVER(mtk_clk_pericfg) = {
 732         .name = "mt7629-clock-pericfg",
 733         .id = UCLASS_CLK,
 734         .of_match = mt7629_pericfg_compat,
 735         .probe = mt7629_pericfg_probe,
 736         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 737         .ops = &mtk_clk_gate_ops,
 738         .flags = DM_FLAG_PRE_RELOC,
 739 };
 740
 741 U_BOOT_DRIVER(mtk_clk_ethsys) = {
 742         .name = "mt7629-clock-ethsys",
 743         .id = UCLASS_CLK,
 744         .of_match = mt7629_ethsys_compat,
 745         .probe = mt7629_ethsys_probe,
 746         .bind = mt7629_ethsys_bind,
 747         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 748         .ops = &mtk_clk_gate_ops,
 749 };
 750
 751 U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
 752         .name = "mt7629-clock-sgmiisys",
 753         .id = UCLASS_CLK,
 754         .of_match = mt7629_sgmiisys_compat,
 755         .probe = mt7629_sgmiisys_probe,
 756         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 757         .ops = &mtk_clk_gate_ops,
 758 };
 759
 760 U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
 761         .name = "mt7629-clock-ssusbsys",
 762         .id = UCLASS_CLK,
 763         .of_match = mt7629_ssusbsys_compat,
 764         .probe = mt7629_ssusbsys_probe,
 765         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 766         .ops = &mtk_clk_gate_ops,
 767 };