1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek clock driver for MT7623 SoC
5 * Copyright (C) 2018 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
12 #include <asm/arch-mediatek/reset.h>
14 #include <dt-bindings/clock/mt7623-clk.h>
15 #include <linux/bitops.h>
19 #define MT7623_CLKSQ_STB_CON0 0x18
20 #define MT7623_PLL_ISO_CON0 0x24
21 #define MT7623_PLL_FMAX (2000UL * MHZ)
22 #define MT7623_CON0_RST_BAR BIT(27)
24 #define MCU_AXI_DIV 0x60
25 #define AXI_DIV_MSK GENMASK(4, 0)
26 #define AXI_DIV_SEL(x) (x)
29 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
30 _pd_shift, _pcw_reg, _pcw_shift) { \
33 .pwr_reg = _pwr_reg, \
34 .en_mask = _en_mask, \
35 .rst_bar_mask = MT7623_CON0_RST_BAR, \
36 .fmax = MT7623_PLL_FMAX, \
38 .pcwbits = _pcwbits, \
40 .pd_shift = _pd_shift, \
41 .pcw_reg = _pcw_reg, \
42 .pcw_shift = _pcw_shift, \
45 static const struct mtk_pll_data apmixed_plls[] = {
46 PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0,
47 21, 0x204, 24, 0x204, 0),
48 PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR,
49 21, 0x210, 4, 0x214, 0),
50 PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR,
51 7, 0x220, 4, 0x224, 14),
52 PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0,
53 21, 0x230, 4, 0x234, 0),
54 PLL(CLK_APMIXED_MSDCPLL, 0x240, 0x24c, 0x00000001, 0,
55 21, 0x240, 4, 0x244, 0),
56 PLL(CLK_APMIXED_TVDPLL, 0x250, 0x25c, 0x00000001, 0,
57 21, 0x250, 4, 0x254, 0),
58 PLL(CLK_APMIXED_AUD1PLL, 0x270, 0x27c, 0x00000001, 0,
59 31, 0x270, 4, 0x274, 0),
60 PLL(CLK_APMIXED_TRGPLL, 0x280, 0x28c, 0x00000001, 0,
61 31, 0x280, 4, 0x284, 0),
62 PLL(CLK_APMIXED_ETHPLL, 0x290, 0x29c, 0x00000001, 0,
63 31, 0x290, 4, 0x294, 0),
64 PLL(CLK_APMIXED_VDECPLL, 0x2a0, 0x2ac, 0x00000001, 0,
65 31, 0x2a0, 4, 0x2a4, 0),
66 PLL(CLK_APMIXED_HADDS2PLL, 0x2b0, 0x2bc, 0x00000001, 0,
67 31, 0x2b0, 4, 0x2b4, 0),
68 PLL(CLK_APMIXED_AUD2PLL, 0x2c0, 0x2cc, 0x00000001, 0,
69 31, 0x2c0, 4, 0x2c4, 0),
70 PLL(CLK_APMIXED_TVD2PLL, 0x2d0, 0x2dc, 0x00000001, 0,
71 21, 0x2d0, 4, 0x2d4, 0),
75 #define FACTOR0(_id, _parent, _mult, _div) \
76 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
78 #define FACTOR1(_id, _parent, _mult, _div) \
79 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
81 #define FACTOR2(_id, _parent, _mult, _div) \
82 FACTOR(_id, _parent, _mult, _div, 0)
84 static const struct mtk_fixed_clk top_fixed_clks[] = {
85 FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ),
86 FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),
87 FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),
88 FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ),
89 FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ),
90 FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ),
91 FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ),
92 FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ),
93 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ),
94 FIXED_CLK(CLK_TOP_HDMI_SCL_RX, CLK_XTAL, 27 * MHZ),
95 FIXED_CLK(CLK_TOP_32K_EXTERNAL, CLK_XTAL, 32000),
96 FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, CLK_XTAL, 300 * MHZ),
97 FIXED_CLK(CLK_TOP_AUD_EXT1, CLK_XTAL, 0),
98 FIXED_CLK(CLK_TOP_AUD_EXT2, CLK_XTAL, 0),
99 FIXED_CLK(CLK_TOP_NFI1X_PAD, CLK_XTAL, 0),
102 static const struct mtk_fixed_factor top_fixed_divs[] = {
103 FACTOR0(CLK_TOP_SYSPLL, CLK_APMIXED_MAINPLL, 1, 1),
104 FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
105 FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
106 FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
107 FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
108 FACTOR1(CLK_TOP_SYSPLL1_D2, CLK_TOP_SYSPLL_D2, 1, 2),
109 FACTOR1(CLK_TOP_SYSPLL1_D4, CLK_TOP_SYSPLL_D2, 1, 4),
110 FACTOR1(CLK_TOP_SYSPLL1_D8, CLK_TOP_SYSPLL_D2, 1, 8),
111 FACTOR1(CLK_TOP_SYSPLL1_D16, CLK_TOP_SYSPLL_D2, 1, 16),
112 FACTOR1(CLK_TOP_SYSPLL2_D2, CLK_TOP_SYSPLL_D3, 1, 2),
113 FACTOR1(CLK_TOP_SYSPLL2_D4, CLK_TOP_SYSPLL_D3, 1, 4),
114 FACTOR1(CLK_TOP_SYSPLL2_D8, CLK_TOP_SYSPLL_D3, 1, 8),
115 FACTOR1(CLK_TOP_SYSPLL3_D2, CLK_TOP_SYSPLL_D5, 1, 2),
116 FACTOR1(CLK_TOP_SYSPLL3_D4, CLK_TOP_SYSPLL_D5, 1, 4),
117 FACTOR1(CLK_TOP_SYSPLL4_D2, CLK_TOP_SYSPLL_D7, 1, 2),
118 FACTOR1(CLK_TOP_SYSPLL4_D4, CLK_TOP_SYSPLL_D7, 1, 4),
120 FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL, 1, 1),
121 FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
122 FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
123 FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
124 FACTOR0(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7),
125 FACTOR0(CLK_TOP_UNIVPLL_D26, CLK_APMIXED_UNIVPLL, 1, 26),
126 FACTOR0(CLK_TOP_UNIVPLL_D52, CLK_APMIXED_UNIVPLL, 1, 52),
127 FACTOR0(CLK_TOP_UNIVPLL_D108, CLK_APMIXED_UNIVPLL, 1, 108),
128 FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26),
129 FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL_D2, 1, 2),
130 FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL_D2, 1, 4),
131 FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL_D2, 1, 8),
132 FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL_D3, 1, 2),
133 FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL_D3, 1, 4),
134 FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL_D3, 1, 8),
135 FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL_D3, 1, 16),
136 FACTOR1(CLK_TOP_UNIVPLL2_D32, CLK_TOP_UNIVPLL_D3, 1, 32),
137 FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL_D5, 1, 2),
138 FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL_D5, 1, 4),
139 FACTOR1(CLK_TOP_UNIVPLL3_D8, CLK_TOP_UNIVPLL_D5, 1, 8),
141 FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1),
142 FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
143 FACTOR0(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1, 4),
144 FACTOR0(CLK_TOP_MSDCPLL_D8, CLK_APMIXED_MSDCPLL, 1, 8),
146 FACTOR0(CLK_TOP_MMPLL, CLK_APMIXED_MMPLL, 1, 1),
147 FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
149 FACTOR1(CLK_TOP_DMPLL_D2, CLK_TOP_DMPLL, 1, 2),
150 FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_DMPLL, 1, 4),
151 FACTOR1(CLK_TOP_DMPLL_X2, CLK_TOP_DMPLL, 1, 1),
153 FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1),
154 FACTOR0(CLK_TOP_TVDPLL_D2, CLK_APMIXED_TVDPLL, 1, 2),
155 FACTOR0(CLK_TOP_TVDPLL_D4, CLK_APMIXED_TVDPLL, 1, 4),
157 FACTOR0(CLK_TOP_VDECPLL, CLK_APMIXED_VDECPLL, 1, 1),
158 FACTOR0(CLK_TOP_TVD2PLL, CLK_APMIXED_TVD2PLL, 1, 1),
159 FACTOR0(CLK_TOP_TVD2PLL_D2, CLK_APMIXED_TVD2PLL, 1, 2),
161 FACTOR1(CLK_TOP_MIPIPLL, CLK_TOP_DPI, 1, 1),
162 FACTOR1(CLK_TOP_MIPIPLL_D2, CLK_TOP_DPI, 1, 2),
163 FACTOR1(CLK_TOP_MIPIPLL_D4, CLK_TOP_DPI, 1, 4),
165 FACTOR1(CLK_TOP_HDMIPLL, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 1),
166 FACTOR1(CLK_TOP_HDMIPLL_D2, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 2),
167 FACTOR1(CLK_TOP_HDMIPLL_D3, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 3),
169 FACTOR0(CLK_TOP_ARMPLL_1P3G, CLK_APMIXED_ARMPLL, 1, 1),
171 FACTOR1(CLK_TOP_AUDPLL, CLK_TOP_AUDPLL_MUX_SEL, 1, 1),
172 FACTOR1(CLK_TOP_AUDPLL_D4, CLK_TOP_AUDPLL_MUX_SEL, 1, 4),
173 FACTOR1(CLK_TOP_AUDPLL_D8, CLK_TOP_AUDPLL_MUX_SEL, 1, 8),
174 FACTOR1(CLK_TOP_AUDPLL_D16, CLK_TOP_AUDPLL_MUX_SEL, 1, 16),
175 FACTOR1(CLK_TOP_AUDPLL_D24, CLK_TOP_AUDPLL_MUX_SEL, 1, 24),
177 FACTOR0(CLK_TOP_AUD1PLL_98M, CLK_APMIXED_AUD1PLL, 1, 3),
178 FACTOR0(CLK_TOP_AUD2PLL_90M, CLK_APMIXED_AUD2PLL, 1, 3),
179 FACTOR0(CLK_TOP_HADDS2PLL_98M, CLK_APMIXED_HADDS2PLL, 1, 3),
180 FACTOR0(CLK_TOP_HADDS2PLL_294M, CLK_APMIXED_HADDS2PLL, 1, 1),
181 FACTOR0(CLK_TOP_ETHPLL_500M, CLK_APMIXED_ETHPLL, 1, 1),
182 FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8),
183 FACTOR2(CLK_TOP_32K_INTERNAL, CLK_XTAL, 1, 793),
184 FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4),
185 FACTOR1(CLK_TOP_8BDAC, CLK_TOP_UNIVPLL_D2, 1, 1),
188 static const int axi_parents[] = {
199 static const int mem_parents[] = {
204 static const int ddrphycfg_parents[] = {
209 static const int mm_parents[] = {
220 static const int pwm_parents[] = {
227 static const int vdec_parents[] = {
239 static const int mfg_parents[] = {
250 static const int camtg_parents[] = {
260 static const int uart_parents[] = {
265 static const int spi_parents[] = {
273 static const int usb20_parents[] = {
279 static const int msdc30_parents[] = {
288 static const int aud_intbus_parents[] = {
297 static const int pmicspi_parents[] = {
311 static const int scp_parents[] = {
318 static const int dpi0_tve_parents[] = {
329 static const int dpi1_parents[] = {
336 static const int hdmi_parents[] = {
343 static const int apll_parents[] = {
354 static const int rtc_parents[] = {
355 CLK_TOP_32K_INTERNAL,
356 CLK_TOP_32K_EXTERNAL,
361 static const int nfi2x_parents[] = {
372 static const int emmc_hclk_parents[] = {
379 static const int flash_parents[] = {
390 static const int di_parents[] = {
397 static const int nr_osd_parents[] = {
408 static const int hdmirx_bist_parents[] = {
419 static const int intdir_parents[] = {
426 static const int asm_parents[] = {
433 static const int ms_card_parents[] = {
439 static const int ethif_parents[] = {
450 static const int hdmirx_parents[] = {
455 static const int cmsys_parents[] = {
473 static const int clk_8bdac_parents[] = {
474 CLK_TOP_32K_INTERNAL,
480 static const int aud2dvd_parents[] = {
481 CLK_TOP_AUD_48K_TIMING,
482 CLK_TOP_AUD_44K_TIMING
485 static const int padmclk_parents[] = {
489 CLK_TOP_UNIVPLL_D108,
491 CLK_TOP_UNIVPLL2_D16,
495 static const int aud_mux_parents[] = {
499 CLK_TOP_HADDS2PLL_98M,
500 CLK_TOP_AUD_EXTCK1_DIV,
501 CLK_TOP_AUD_EXTCK2_DIV
504 static const int aud_src_parents[] = {
505 CLK_TOP_AUD_MUX1_SEL,
509 static const struct mtk_composite top_muxes[] = {
510 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
511 MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
512 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
513 MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31,
516 MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
517 MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15),
518 MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23,
520 MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31),
522 MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
523 MUX_GATE(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15),
524 MUX_GATE(CLK_TOP_USB20_SEL, usb20_parents, 0x60, 16, 2, 23),
525 MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_parents, 0x60, 24, 3, 31),
527 MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_parents, 0x70, 0, 3, 7),
528 MUX_GATE(CLK_TOP_MSDC30_2_SEL, msdc30_parents, 0x70, 8, 3, 15),
529 MUX_GATE(CLK_TOP_AUDIO_SEL, msdc30_parents, 0x70, 16, 1, 23),
530 MUX_GATE(CLK_TOP_AUDINTBUS_SEL, aud_intbus_parents, 0x70, 24, 3, 31),
532 MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 0, 4, 7),
533 MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 8, 2, 15),
534 MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_tve_parents, 0x80, 16, 3, 23),
535 MUX_GATE(CLK_TOP_DPI1_SEL, dpi1_parents, 0x80, 24, 2, 31),
537 MUX_GATE(CLK_TOP_TVE_SEL, dpi0_tve_parents, 0x90, 0, 3, 7),
538 MUX_GATE(CLK_TOP_HDMI_SEL, hdmi_parents, 0x90, 8, 2, 15),
539 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
541 MUX_GATE(CLK_TOP_RTC_SEL, rtc_parents, 0xA0, 0, 2, 7),
542 MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0xA0, 8, 3, 15),
543 MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, emmc_hclk_parents, 0xA0, 24, 2, 31),
545 MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0xB0, 0, 3, 7),
546 MUX_GATE(CLK_TOP_DI_SEL, di_parents, 0xB0, 8, 2, 15),
547 MUX_GATE(CLK_TOP_NR_SEL, nr_osd_parents, 0xB0, 16, 3, 23),
548 MUX_GATE(CLK_TOP_OSD_SEL, nr_osd_parents, 0xB0, 24, 3, 31),
550 MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, hdmirx_bist_parents, 0xC0, 0, 3, 7),
551 MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0xC0, 8, 2, 15),
552 MUX_GATE(CLK_TOP_ASM_I_SEL, asm_parents, 0xC0, 16, 2, 23),
553 MUX_GATE(CLK_TOP_ASM_M_SEL, asm_parents, 0xC0, 24, 3, 31),
555 MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7),
556 MUX_GATE(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23),
557 MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31,
560 MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7),
561 MUX_GATE(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15),
562 MUX_GATE(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xE0, 16, 4, 23),
564 MUX_GATE(CLK_TOP_SPI1_SEL, spi_parents, 0xE0, 24, 3, 31),
565 MUX_GATE(CLK_TOP_SPI2_SEL, spi_parents, 0xF0, 0, 3, 7),
566 MUX_GATE(CLK_TOP_8BDAC_SEL, clk_8bdac_parents, 0xF0, 8, 2, 15),
567 MUX_GATE(CLK_TOP_AUD2DVD_SEL, aud2dvd_parents, 0xF0, 16, 1, 23),
569 MUX(CLK_TOP_PADMCLK_SEL, padmclk_parents, 0x100, 0, 3),
571 MUX(CLK_TOP_AUD_MUX1_SEL, aud_mux_parents, 0x12c, 0, 3),
572 MUX(CLK_TOP_AUD_MUX2_SEL, aud_mux_parents, 0x12c, 3, 3),
573 MUX(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3),
575 MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, aud_src_parents, 0x12c, 15, 1, 23),
576 MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, aud_src_parents, 0x12c, 16, 1, 24),
577 MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, aud_src_parents, 0x12c, 17, 1, 25),
578 MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, aud_src_parents, 0x12c, 18, 1, 26),
579 MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, aud_src_parents, 0x12c, 19, 1, 27),
580 MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, aud_src_parents, 0x12c, 20, 1, 28),
584 static const struct mtk_gate_regs infra_cg_regs = {
590 #define GATE_INFRA(_id, _parent, _shift) { \
593 .regs = &infra_cg_regs, \
595 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
598 static const struct mtk_gate infra_cgs[] = {
599 GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0),
600 GATE_INFRA(CLK_INFRA_SMI, CLK_TOP_MM_SEL, 1),
601 GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2),
602 GATE_INFRA(CLK_INFRA_AUD_SPLIN_B, CLK_TOP_HADDS2PLL_294M, 4),
603 GATE_INFRA(CLK_INFRA_AUDIO, CLK_XTAL, 5),
604 GATE_INFRA(CLK_INFRA_EFUSE, CLK_XTAL, 6),
605 GATE_INFRA(CLK_INFRA_L2C_SRAM, CLK_TOP_MM_SEL, 7),
606 GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8),
607 GATE_INFRA(CLK_INFRA_CONNMCU, CLK_TOP_WBG_DIG_416M, 12),
608 GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 13),
609 GATE_INFRA(CLK_INFRA_RAMBUFIF, CLK_TOP_MEM_SEL, 14),
610 GATE_INFRA(CLK_INFRA_CPUM, CLK_TOP_MEM_SEL, 15),
611 GATE_INFRA(CLK_INFRA_KP, CLK_TOP_AXI_SEL, 16),
612 GATE_INFRA(CLK_INFRA_CEC, CLK_TOP_RTC_SEL, 18),
613 GATE_INFRA(CLK_INFRA_IRRX, CLK_TOP_AXI_SEL, 19),
614 GATE_INFRA(CLK_INFRA_PMICSPI, CLK_TOP_PMICSPI_SEL, 22),
615 GATE_INFRA(CLK_INFRA_PMICWRAP, CLK_TOP_AXI_SEL, 23),
616 GATE_INFRA(CLK_INFRA_DDCCI, CLK_TOP_AXI_SEL, 24),
620 static const struct mtk_gate_regs peri0_cg_regs = {
626 static const struct mtk_gate_regs peri1_cg_regs = {
632 #define GATE_PERI0(_id, _parent, _shift) { \
635 .regs = &peri0_cg_regs, \
637 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
640 #define GATE_PERI1(_id, _parent, _shift) { \
643 .regs = &peri1_cg_regs, \
645 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
648 static const struct mtk_gate peri_cgs[] = {
649 GATE_PERI0(CLK_PERI_NFI, CLK_TOP_NFI2X_SEL, 0),
650 GATE_PERI0(CLK_PERI_THERM, CLK_TOP_AXI_SEL, 1),
651 GATE_PERI0(CLK_PERI_PWM1, CLK_TOP_AXISEL_D4, 2),
652 GATE_PERI0(CLK_PERI_PWM2, CLK_TOP_AXISEL_D4, 3),
653 GATE_PERI0(CLK_PERI_PWM3, CLK_TOP_AXISEL_D4, 4),
654 GATE_PERI0(CLK_PERI_PWM4, CLK_TOP_AXISEL_D4, 5),
655 GATE_PERI0(CLK_PERI_PWM5, CLK_TOP_AXISEL_D4, 6),
656 GATE_PERI0(CLK_PERI_PWM6, CLK_TOP_AXISEL_D4, 7),
657 GATE_PERI0(CLK_PERI_PWM7, CLK_TOP_AXISEL_D4, 8),
658 GATE_PERI0(CLK_PERI_PWM, CLK_TOP_AXI_SEL, 9),
659 GATE_PERI0(CLK_PERI_USB0, CLK_TOP_USB20_SEL, 10),
660 GATE_PERI0(CLK_PERI_USB1, CLK_TOP_USB20_SEL, 11),
661 GATE_PERI0(CLK_PERI_AP_DMA, CLK_TOP_AXI_SEL, 12),
662 GATE_PERI0(CLK_PERI_MSDC30_0, CLK_TOP_MSDC30_0_SEL, 13),
663 GATE_PERI0(CLK_PERI_MSDC30_1, CLK_TOP_MSDC30_1_SEL, 14),
664 GATE_PERI0(CLK_PERI_MSDC30_2, CLK_TOP_MSDC30_2_SEL, 15),
665 GATE_PERI0(CLK_PERI_MSDC30_3, CLK_TOP_MSDC30_3_SEL, 16),
666 GATE_PERI0(CLK_PERI_MSDC50_3, CLK_TOP_EMMC_HCLK_SEL, 17),
667 GATE_PERI0(CLK_PERI_NLI, CLK_TOP_AXI_SEL, 18),
668 GATE_PERI0(CLK_PERI_UART0, CLK_TOP_AXI_SEL, 19),
669 GATE_PERI0(CLK_PERI_UART1, CLK_TOP_AXI_SEL, 20),
670 GATE_PERI0(CLK_PERI_UART2, CLK_TOP_AXI_SEL, 21),
671 GATE_PERI0(CLK_PERI_UART3, CLK_TOP_AXI_SEL, 22),
672 GATE_PERI0(CLK_PERI_BTIF, CLK_TOP_AXI_SEL, 23),
673 GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24),
674 GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25),
675 GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26),
676 GATE_PERI0(CLK_PERI_I2C3, CLK_XTAL, 27),
677 GATE_PERI0(CLK_PERI_AUXADC, CLK_XTAL, 28),
678 GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29),
679 GATE_PERI0(CLK_PERI_ETH, CLK_XTAL, 30),
680 GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31),
682 GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0),
683 GATE_PERI1(CLK_PERI_USB_SLV, CLK_TOP_AXI_SEL, 1),
684 GATE_PERI1(CLK_PERI_GCPU, CLK_TOP_AXI_SEL, 2),
685 GATE_PERI1(CLK_PERI_NFI_ECC, CLK_TOP_NFI1X_PAD, 3),
686 GATE_PERI1(CLK_PERI_NFI_PAD, CLK_TOP_NFI1X_PAD, 4),
687 GATE_PERI1(CLK_PERI_FLASH, CLK_TOP_NFI2X_SEL, 5),
688 GATE_PERI1(CLK_PERI_HOST89_INT, CLK_TOP_AXI_SEL, 6),
689 GATE_PERI1(CLK_PERI_HOST89_SPI, CLK_TOP_SPI0_SEL, 7),
690 GATE_PERI1(CLK_PERI_HOST89_DVD, CLK_TOP_AUD2DVD_SEL, 8),
691 GATE_PERI1(CLK_PERI_SPI1, CLK_TOP_SPI1_SEL, 9),
692 GATE_PERI1(CLK_PERI_SPI2, CLK_TOP_SPI2_SEL, 10),
693 GATE_PERI1(CLK_PERI_FCI, CLK_TOP_MS_CARD_SEL, 11),
696 /* ethsys and hifsys */
697 static const struct mtk_gate_regs eth_hif_cg_regs = {
701 #define GATE_ETH_HIF(_id, _parent, _shift, _flag) { \
704 .regs = ð_hif_cg_regs, \
706 .flags = CLK_GATE_NO_SETCLR_INV | (_flag), \
709 #define GATE_ETH_HIF0(_id, _parent, _shift) \
710 GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_APMIXED)
712 #define GATE_ETH_HIF1(_id, _parent, _shift) \
713 GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_TOPCKGEN)
715 static const struct mtk_gate eth_cgs[] = {
716 GATE_ETH_HIF1(CLK_ETHSYS_HSDMA, CLK_TOP_ETHIF_SEL, 5),
717 GATE_ETH_HIF1(CLK_ETHSYS_ESW, CLK_TOP_ETHPLL_500M, 6),
718 GATE_ETH_HIF0(CLK_ETHSYS_GP2, CLK_APMIXED_TRGPLL, 7),
719 GATE_ETH_HIF1(CLK_ETHSYS_GP1, CLK_TOP_ETHPLL_500M, 8),
720 GATE_ETH_HIF1(CLK_ETHSYS_PCM, CLK_TOP_ETHIF_SEL, 11),
721 GATE_ETH_HIF1(CLK_ETHSYS_GDMA, CLK_TOP_ETHIF_SEL, 14),
722 GATE_ETH_HIF1(CLK_ETHSYS_I2S, CLK_TOP_ETHIF_SEL, 17),
723 GATE_ETH_HIF1(CLK_ETHSYS_CRYPTO, CLK_TOP_ETHIF_SEL, 29),
726 static const struct mtk_gate hif_cgs[] = {
727 GATE_ETH_HIF1(CLK_HIFSYS_USB0PHY, CLK_TOP_ETHPLL_500M, 21),
728 GATE_ETH_HIF1(CLK_HIFSYS_USB1PHY, CLK_TOP_ETHPLL_500M, 22),
729 GATE_ETH_HIF1(CLK_HIFSYS_PCIE0, CLK_TOP_ETHPLL_500M, 24),
730 GATE_ETH_HIF1(CLK_HIFSYS_PCIE1, CLK_TOP_ETHPLL_500M, 25),
731 GATE_ETH_HIF1(CLK_HIFSYS_PCIE2, CLK_TOP_ETHPLL_500M, 26),
734 static const struct mtk_clk_tree mt7623_clk_tree = {
735 .xtal_rate = 26 * MHZ,
736 .xtal2_rate = 26 * MHZ,
737 .fdivs_offs = CLK_TOP_SYSPLL,
738 .muxes_offs = CLK_TOP_AXI_SEL,
739 .plls = apmixed_plls,
740 .fclks = top_fixed_clks,
741 .fdivs = top_fixed_divs,
745 static int mt7623_mcucfg_probe(struct udevice *dev)
749 base = dev_read_addr_ptr(dev);
753 clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
759 static int mt7623_apmixedsys_probe(struct udevice *dev)
761 struct mtk_clk_priv *priv = dev_get_priv(dev);
764 ret = mtk_common_clk_init(dev, &mt7623_clk_tree);
768 /* reduce clock square disable time */
769 writel(0x50001, priv->base + MT7623_CLKSQ_STB_CON0);
770 /* extend control timing to 1us */
771 writel(0x888, priv->base + MT7623_PLL_ISO_CON0);
776 static int mt7623_topckgen_probe(struct udevice *dev)
778 return mtk_common_clk_init(dev, &mt7623_clk_tree);
781 static int mt7623_infracfg_probe(struct udevice *dev)
783 return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, infra_cgs);
786 static int mt7623_pericfg_probe(struct udevice *dev)
788 return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, peri_cgs);
791 static int mt7623_hifsys_probe(struct udevice *dev)
793 return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, hif_cgs);
796 static int mt7623_ethsys_probe(struct udevice *dev)
798 return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs);
801 static int mt7623_ethsys_hifsys_bind(struct udevice *dev)
805 #if CONFIG_IS_ENABLED(RESET_MEDIATEK)
806 ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
808 debug("Warning: failed to bind reset controller\n");
814 static const struct udevice_id mt7623_apmixed_compat[] = {
815 { .compatible = "mediatek,mt7623-apmixedsys" },
819 static const struct udevice_id mt7623_topckgen_compat[] = {
820 { .compatible = "mediatek,mt7623-topckgen" },
824 static const struct udevice_id mt7623_infracfg_compat[] = {
825 { .compatible = "mediatek,mt7623-infracfg", },
829 static const struct udevice_id mt7623_pericfg_compat[] = {
830 { .compatible = "mediatek,mt7623-pericfg", },
834 static const struct udevice_id mt7623_ethsys_compat[] = {
835 { .compatible = "mediatek,mt7623-ethsys" },
839 static const struct udevice_id mt7623_hifsys_compat[] = {
840 { .compatible = "mediatek,mt7623-hifsys" },
844 static const struct udevice_id mt7623_mcucfg_compat[] = {
845 { .compatible = "mediatek,mt7623-mcucfg" },
849 U_BOOT_DRIVER(mtk_mcucfg) = {
850 .name = "mt7623-mcucfg",
852 .of_match = mt7623_mcucfg_compat,
853 .probe = mt7623_mcucfg_probe,
854 .flags = DM_FLAG_PRE_RELOC,
857 U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
858 .name = "mt7623-clock-apmixedsys",
860 .of_match = mt7623_apmixed_compat,
861 .probe = mt7623_apmixedsys_probe,
862 .priv_auto = sizeof(struct mtk_clk_priv),
863 .ops = &mtk_clk_apmixedsys_ops,
864 .flags = DM_FLAG_PRE_RELOC,
867 U_BOOT_DRIVER(mtk_clk_topckgen) = {
868 .name = "mt7623-clock-topckgen",
870 .of_match = mt7623_topckgen_compat,
871 .probe = mt7623_topckgen_probe,
872 .priv_auto = sizeof(struct mtk_clk_priv),
873 .ops = &mtk_clk_topckgen_ops,
874 .flags = DM_FLAG_PRE_RELOC,
877 U_BOOT_DRIVER(mtk_clk_infracfg) = {
878 .name = "mt7623-infracfg",
880 .of_match = mt7623_infracfg_compat,
881 .probe = mt7623_infracfg_probe,
882 .priv_auto = sizeof(struct mtk_cg_priv),
883 .ops = &mtk_clk_gate_ops,
884 .flags = DM_FLAG_PRE_RELOC,
887 U_BOOT_DRIVER(mtk_clk_pericfg) = {
888 .name = "mt7623-pericfg",
890 .of_match = mt7623_pericfg_compat,
891 .probe = mt7623_pericfg_probe,
892 .priv_auto = sizeof(struct mtk_cg_priv),
893 .ops = &mtk_clk_gate_ops,
894 .flags = DM_FLAG_PRE_RELOC,
897 U_BOOT_DRIVER(mtk_clk_hifsys) = {
898 .name = "mt7623-clock-hifsys",
900 .of_match = mt7623_hifsys_compat,
901 .probe = mt7623_hifsys_probe,
902 .bind = mt7623_ethsys_hifsys_bind,
903 .priv_auto = sizeof(struct mtk_cg_priv),
904 .ops = &mtk_clk_gate_ops,
907 U_BOOT_DRIVER(mtk_clk_ethsys) = {
908 .name = "mt7623-clock-ethsys",
910 .of_match = mt7623_ethsys_compat,
911 .probe = mt7623_ethsys_probe,
912 .bind = mt7623_ethsys_hifsys_bind,
913 .priv_auto = sizeof(struct mtk_cg_priv),
914 .ops = &mtk_clk_gate_ops,