drivers/clk/mediatek/clk-mt7623.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MediaTek clock driver for MT7623 SoC
   4  *
   5  * Copyright (C) 2018 MediaTek Inc.
   6  * Author: Ryder Lee <ryder.lee@mediatek.com>
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <log.h>
  12 #include <asm/arch-mediatek/reset.h>
  13 #include <asm/io.h>
  14 #include <dt-bindings/clock/mt7623-clk.h>
  15
  16 #include "clk-mtk.h"
  17
  18 #define MT7623_CLKSQ_STB_CON0           0x18
  19 #define MT7623_PLL_ISO_CON0             0x24
  20 #define MT7623_PLL_FMAX                 (2000UL * MHZ)
  21 #define MT7623_CON0_RST_BAR             BIT(27)
  22
  23 #define MCU_AXI_DIV                     0x60
  24 #define AXI_DIV_MSK                     GENMASK(4, 0)
  25 #define AXI_DIV_SEL(x)                  (x)
  26
  27 /* apmixedsys */
  28 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,   \
  29             _pd_shift, _pcw_reg, _pcw_shift) {                          \
  30                 .id = _id,                                              \
  31                 .reg = _reg,                                            \
  32                 .pwr_reg = _pwr_reg,                                    \
  33                 .en_mask = _en_mask,                                    \
  34                 .rst_bar_mask = MT7623_CON0_RST_BAR,                    \
  35                 .fmax = MT7623_PLL_FMAX,                                \
  36                 .flags = _flags,                                        \
  37                 .pcwbits = _pcwbits,                                    \
  38                 .pd_reg = _pd_reg,                                      \
  39                 .pd_shift = _pd_shift,                                  \
  40                 .pcw_reg = _pcw_reg,                                    \
  41                 .pcw_shift = _pcw_shift,                                \
  42         }
  43
  44 static const struct mtk_pll_data apmixed_plls[] = {
  45         PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0,
  46             21, 0x204, 24, 0x204, 0),
  47         PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR,
  48             21, 0x210, 4, 0x214, 0),
  49         PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR,
  50             7, 0x220, 4, 0x224, 14),
  51         PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0,
  52             21, 0x230, 4, 0x234, 0),
  53         PLL(CLK_APMIXED_MSDCPLL, 0x240, 0x24c, 0x00000001, 0,
  54             21, 0x240, 4, 0x244, 0),
  55         PLL(CLK_APMIXED_TVDPLL, 0x250, 0x25c, 0x00000001, 0,
  56             21, 0x250, 4, 0x254, 0),
  57         PLL(CLK_APMIXED_AUD1PLL, 0x270, 0x27c, 0x00000001, 0,
  58             31, 0x270, 4, 0x274, 0),
  59         PLL(CLK_APMIXED_TRGPLL, 0x280, 0x28c, 0x00000001, 0,
  60             31, 0x280, 4, 0x284, 0),
  61         PLL(CLK_APMIXED_ETHPLL, 0x290, 0x29c, 0x00000001, 0,
  62             31, 0x290, 4, 0x294, 0),
  63         PLL(CLK_APMIXED_VDECPLL, 0x2a0, 0x2ac, 0x00000001, 0,
  64             31, 0x2a0, 4, 0x2a4, 0),
  65         PLL(CLK_APMIXED_HADDS2PLL, 0x2b0, 0x2bc, 0x00000001, 0,
  66             31, 0x2b0, 4, 0x2b4, 0),
  67         PLL(CLK_APMIXED_AUD2PLL, 0x2c0, 0x2cc, 0x00000001, 0,
  68             31, 0x2c0, 4, 0x2c4, 0),
  69         PLL(CLK_APMIXED_TVD2PLL, 0x2d0, 0x2dc, 0x00000001, 0,
  70             21, 0x2d0, 4, 0x2d4, 0),
  71 };
  72
  73 /* topckgen */
  74 #define FACTOR0(_id, _parent, _mult, _div)                      \
  75         FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
  76
  77 #define FACTOR1(_id, _parent, _mult, _div)                      \
  78         FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
  79
  80 #define FACTOR2(_id, _parent, _mult, _div)                      \
  81         FACTOR(_id, _parent, _mult, _div, 0)
  82
  83 static const struct mtk_fixed_clk top_fixed_clks[] = {
  84         FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ),
  85         FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),
  86         FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),
  87         FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ),
  88         FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ),
  89         FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ),
  90         FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ),
  91         FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ),
  92         FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ),
  93         FIXED_CLK(CLK_TOP_HDMI_SCL_RX, CLK_XTAL, 27 * MHZ),
  94         FIXED_CLK(CLK_TOP_32K_EXTERNAL, CLK_XTAL, 32000),
  95         FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, CLK_XTAL, 300 * MHZ),
  96         FIXED_CLK(CLK_TOP_AUD_EXT1, CLK_XTAL, 0),
  97         FIXED_CLK(CLK_TOP_AUD_EXT2, CLK_XTAL, 0),
  98         FIXED_CLK(CLK_TOP_NFI1X_PAD, CLK_XTAL, 0),
  99 };
 100
 101 static const struct mtk_fixed_factor top_fixed_divs[] = {
 102         FACTOR0(CLK_TOP_SYSPLL, CLK_APMIXED_MAINPLL, 1, 1),
 103         FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
 104         FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
 105         FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
 106         FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
 107         FACTOR1(CLK_TOP_SYSPLL1_D2, CLK_TOP_SYSPLL_D2, 1, 2),
 108         FACTOR1(CLK_TOP_SYSPLL1_D4, CLK_TOP_SYSPLL_D2, 1, 4),
 109         FACTOR1(CLK_TOP_SYSPLL1_D8, CLK_TOP_SYSPLL_D2, 1, 8),
 110         FACTOR1(CLK_TOP_SYSPLL1_D16, CLK_TOP_SYSPLL_D2, 1, 16),
 111         FACTOR1(CLK_TOP_SYSPLL2_D2, CLK_TOP_SYSPLL_D3, 1, 2),
 112         FACTOR1(CLK_TOP_SYSPLL2_D4, CLK_TOP_SYSPLL_D3, 1, 4),
 113         FACTOR1(CLK_TOP_SYSPLL2_D8, CLK_TOP_SYSPLL_D3, 1, 8),
 114         FACTOR1(CLK_TOP_SYSPLL3_D2, CLK_TOP_SYSPLL_D5, 1, 2),
 115         FACTOR1(CLK_TOP_SYSPLL3_D4, CLK_TOP_SYSPLL_D5, 1, 4),
 116         FACTOR1(CLK_TOP_SYSPLL4_D2, CLK_TOP_SYSPLL_D7, 1, 2),
 117         FACTOR1(CLK_TOP_SYSPLL4_D4, CLK_TOP_SYSPLL_D7, 1, 4),
 118
 119         FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL, 1, 1),
 120         FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
 121         FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
 122         FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
 123         FACTOR0(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7),
 124         FACTOR0(CLK_TOP_UNIVPLL_D26, CLK_APMIXED_UNIVPLL, 1, 26),
 125         FACTOR0(CLK_TOP_UNIVPLL_D52, CLK_APMIXED_UNIVPLL, 1, 52),
 126         FACTOR0(CLK_TOP_UNIVPLL_D108, CLK_APMIXED_UNIVPLL, 1, 108),
 127         FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26),
 128         FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL_D2, 1, 2),
 129         FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL_D2, 1, 4),
 130         FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL_D2, 1, 8),
 131         FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL_D3, 1, 2),
 132         FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL_D3, 1, 4),
 133         FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL_D3, 1, 8),
 134         FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL_D3, 1, 16),
 135         FACTOR1(CLK_TOP_UNIVPLL2_D32, CLK_TOP_UNIVPLL_D3, 1, 32),
 136         FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL_D5, 1, 2),
 137         FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL_D5, 1, 4),
 138         FACTOR1(CLK_TOP_UNIVPLL3_D8, CLK_TOP_UNIVPLL_D5, 1, 8),
 139
 140         FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1),
 141         FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
 142         FACTOR0(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1, 4),
 143         FACTOR0(CLK_TOP_MSDCPLL_D8, CLK_APMIXED_MSDCPLL, 1, 8),
 144
 145         FACTOR0(CLK_TOP_MMPLL, CLK_APMIXED_MMPLL, 1, 1),
 146         FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
 147
 148         FACTOR1(CLK_TOP_DMPLL_D2, CLK_TOP_DMPLL, 1, 2),
 149         FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_DMPLL, 1, 4),
 150         FACTOR1(CLK_TOP_DMPLL_X2, CLK_TOP_DMPLL, 1, 1),
 151
 152         FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1),
 153         FACTOR0(CLK_TOP_TVDPLL_D2, CLK_APMIXED_TVDPLL, 1, 2),
 154         FACTOR0(CLK_TOP_TVDPLL_D4, CLK_APMIXED_TVDPLL, 1, 4),
 155
 156         FACTOR0(CLK_TOP_VDECPLL, CLK_APMIXED_VDECPLL, 1, 1),
 157         FACTOR0(CLK_TOP_TVD2PLL, CLK_APMIXED_TVD2PLL, 1, 1),
 158         FACTOR0(CLK_TOP_TVD2PLL_D2, CLK_APMIXED_TVD2PLL, 1, 2),
 159
 160         FACTOR1(CLK_TOP_MIPIPLL, CLK_TOP_DPI, 1, 1),
 161         FACTOR1(CLK_TOP_MIPIPLL_D2, CLK_TOP_DPI, 1, 2),
 162         FACTOR1(CLK_TOP_MIPIPLL_D4, CLK_TOP_DPI, 1, 4),
 163
 164         FACTOR1(CLK_TOP_HDMIPLL, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 1),
 165         FACTOR1(CLK_TOP_HDMIPLL_D2, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 2),
 166         FACTOR1(CLK_TOP_HDMIPLL_D3, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 3),
 167
 168         FACTOR0(CLK_TOP_ARMPLL_1P3G, CLK_APMIXED_ARMPLL, 1, 1),
 169
 170         FACTOR1(CLK_TOP_AUDPLL, CLK_TOP_AUDPLL_MUX_SEL, 1, 1),
 171         FACTOR1(CLK_TOP_AUDPLL_D4, CLK_TOP_AUDPLL_MUX_SEL, 1, 4),
 172         FACTOR1(CLK_TOP_AUDPLL_D8, CLK_TOP_AUDPLL_MUX_SEL, 1, 8),
 173         FACTOR1(CLK_TOP_AUDPLL_D16, CLK_TOP_AUDPLL_MUX_SEL, 1, 16),
 174         FACTOR1(CLK_TOP_AUDPLL_D24, CLK_TOP_AUDPLL_MUX_SEL, 1, 24),
 175
 176         FACTOR0(CLK_TOP_AUD1PLL_98M, CLK_APMIXED_AUD1PLL, 1, 3),
 177         FACTOR0(CLK_TOP_AUD2PLL_90M, CLK_APMIXED_AUD2PLL, 1, 3),
 178         FACTOR0(CLK_TOP_HADDS2PLL_98M, CLK_APMIXED_HADDS2PLL, 1, 3),
 179         FACTOR0(CLK_TOP_HADDS2PLL_294M, CLK_APMIXED_HADDS2PLL, 1, 1),
 180         FACTOR0(CLK_TOP_ETHPLL_500M, CLK_APMIXED_ETHPLL, 1, 1),
 181         FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8),
 182         FACTOR2(CLK_TOP_32K_INTERNAL, CLK_XTAL, 1, 793),
 183         FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4),
 184         FACTOR1(CLK_TOP_8BDAC, CLK_TOP_UNIVPLL_D2, 1, 1),
 185 };
 186
 187 static const int axi_parents[] = {
 188         CLK_XTAL,
 189         CLK_TOP_SYSPLL1_D2,
 190         CLK_TOP_SYSPLL_D5,
 191         CLK_TOP_SYSPLL1_D4,
 192         CLK_TOP_UNIVPLL_D5,
 193         CLK_TOP_UNIVPLL2_D2,
 194         CLK_TOP_MMPLL_D2,
 195         CLK_TOP_DMPLL_D2
 196 };
 197
 198 static const int mem_parents[] = {
 199         CLK_XTAL,
 200         CLK_TOP_DMPLL
 201 };
 202
 203 static const int ddrphycfg_parents[] = {
 204         CLK_XTAL,
 205         CLK_TOP_SYSPLL1_D8
 206 };
 207
 208 static const int mm_parents[] = {
 209         CLK_XTAL,
 210         CLK_TOP_VENCPLL,
 211         CLK_TOP_SYSPLL1_D2,
 212         CLK_TOP_SYSPLL1_D4,
 213         CLK_TOP_UNIVPLL_D5,
 214         CLK_TOP_UNIVPLL1_D2,
 215         CLK_TOP_UNIVPLL2_D2,
 216         CLK_TOP_DMPLL
 217 };
 218
 219 static const int pwm_parents[] = {
 220         CLK_XTAL,
 221         CLK_TOP_UNIVPLL2_D4,
 222         CLK_TOP_UNIVPLL3_D2,
 223         CLK_TOP_UNIVPLL1_D4
 224 };
 225
 226 static const int vdec_parents[] = {
 227         CLK_XTAL,
 228         CLK_TOP_VDECPLL,
 229         CLK_TOP_SYSPLL_D5,
 230         CLK_TOP_SYSPLL1_D4,
 231         CLK_TOP_UNIVPLL_D5,
 232         CLK_TOP_UNIVPLL2_D2,
 233         CLK_TOP_VENCPLL,
 234         CLK_TOP_MSDCPLL_D2,
 235         CLK_TOP_MMPLL_D2
 236 };
 237
 238 static const int mfg_parents[] = {
 239         CLK_XTAL,
 240         CLK_TOP_MMPLL,
 241         CLK_TOP_DMPLL_X2,
 242         CLK_TOP_MSDCPLL,
 243         CLK_XTAL,
 244         CLK_TOP_SYSPLL_D3,
 245         CLK_TOP_UNIVPLL_D3,
 246         CLK_TOP_UNIVPLL1_D2
 247 };
 248
 249 static const int camtg_parents[] = {
 250         CLK_XTAL,
 251         CLK_TOP_UNIVPLL_D26,
 252         CLK_TOP_UNIVPLL2_D2,
 253         CLK_TOP_SYSPLL3_D2,
 254         CLK_TOP_SYSPLL3_D4,
 255         CLK_TOP_MSDCPLL_D2,
 256         CLK_TOP_MMPLL_D2
 257 };
 258
 259 static const int uart_parents[] = {
 260         CLK_XTAL,
 261         CLK_TOP_UNIVPLL2_D8
 262 };
 263
 264 static const int spi_parents[] = {
 265         CLK_XTAL,
 266         CLK_TOP_SYSPLL3_D2,
 267         CLK_TOP_SYSPLL4_D2,
 268         CLK_TOP_UNIVPLL2_D4,
 269         CLK_TOP_UNIVPLL1_D8
 270 };
 271
 272 static const int usb20_parents[] = {
 273         CLK_XTAL,
 274         CLK_TOP_UNIVPLL1_D8,
 275         CLK_TOP_UNIVPLL3_D4
 276 };
 277
 278 static const int msdc30_parents[] = {
 279         CLK_XTAL,
 280         CLK_TOP_MSDCPLL_D2,
 281         CLK_TOP_SYSPLL2_D2,
 282         CLK_TOP_SYSPLL1_D4,
 283         CLK_TOP_UNIVPLL1_D4,
 284         CLK_TOP_UNIVPLL2_D4,
 285 };
 286
 287 static const int aud_intbus_parents[] = {
 288         CLK_XTAL,
 289         CLK_TOP_SYSPLL1_D4,
 290         CLK_TOP_SYSPLL3_D2,
 291         CLK_TOP_SYSPLL4_D2,
 292         CLK_TOP_UNIVPLL3_D2,
 293         CLK_TOP_UNIVPLL2_D4
 294 };
 295
 296 static const int pmicspi_parents[] = {
 297         CLK_XTAL,
 298         CLK_TOP_SYSPLL1_D8,
 299         CLK_TOP_SYSPLL2_D4,
 300         CLK_TOP_SYSPLL4_D2,
 301         CLK_TOP_SYSPLL3_D4,
 302         CLK_TOP_SYSPLL2_D8,
 303         CLK_TOP_SYSPLL1_D16,
 304         CLK_TOP_UNIVPLL3_D4,
 305         CLK_TOP_UNIVPLL_D26,
 306         CLK_TOP_DMPLL_D2,
 307         CLK_TOP_DMPLL_D4
 308 };
 309
 310 static const int scp_parents[] = {
 311         CLK_XTAL,
 312         CLK_TOP_SYSPLL1_D8,
 313         CLK_TOP_DMPLL_D2,
 314         CLK_TOP_DMPLL_D4
 315 };
 316
 317 static const int dpi0_tve_parents[] = {
 318         CLK_XTAL,
 319         CLK_TOP_MIPIPLL,
 320         CLK_TOP_MIPIPLL_D2,
 321         CLK_TOP_MIPIPLL_D4,
 322         CLK_XTAL,
 323         CLK_TOP_TVDPLL,
 324         CLK_TOP_TVDPLL_D2,
 325         CLK_TOP_TVDPLL_D4
 326 };
 327
 328 static const int dpi1_parents[] = {
 329         CLK_XTAL,
 330         CLK_TOP_TVDPLL,
 331         CLK_TOP_TVDPLL_D2,
 332         CLK_TOP_TVDPLL_D4
 333 };
 334
 335 static const int hdmi_parents[] = {
 336         CLK_XTAL,
 337         CLK_TOP_HDMIPLL,
 338         CLK_TOP_HDMIPLL_D2,
 339         CLK_TOP_HDMIPLL_D3
 340 };
 341
 342 static const int apll_parents[] = {
 343         CLK_XTAL,
 344         CLK_TOP_AUDPLL,
 345         CLK_TOP_AUDPLL_D4,
 346         CLK_TOP_AUDPLL_D8,
 347         CLK_TOP_AUDPLL_D16,
 348         CLK_TOP_AUDPLL_D24,
 349         CLK_XTAL,
 350         CLK_XTAL
 351 };
 352
 353 static const int rtc_parents[] = {
 354         CLK_TOP_32K_INTERNAL,
 355         CLK_TOP_32K_EXTERNAL,
 356         CLK_XTAL,
 357         CLK_TOP_UNIVPLL3_D8
 358 };
 359
 360 static const int nfi2x_parents[] = {
 361         CLK_XTAL,
 362         CLK_TOP_SYSPLL2_D2,
 363         CLK_TOP_SYSPLL_D7,
 364         CLK_TOP_UNIVPLL3_D2,
 365         CLK_TOP_SYSPLL2_D4,
 366         CLK_TOP_UNIVPLL3_D4,
 367         CLK_TOP_SYSPLL4_D4,
 368         CLK_XTAL
 369 };
 370
 371 static const int emmc_hclk_parents[] = {
 372         CLK_XTAL,
 373         CLK_TOP_SYSPLL1_D2,
 374         CLK_TOP_SYSPLL1_D4,
 375         CLK_TOP_SYSPLL2_D2
 376 };
 377
 378 static const int flash_parents[] = {
 379         CLK_TOP_CLK26M_D8,
 380         CLK_XTAL,
 381         CLK_TOP_SYSPLL2_D8,
 382         CLK_TOP_SYSPLL3_D4,
 383         CLK_TOP_UNIVPLL3_D4,
 384         CLK_TOP_SYSPLL4_D2,
 385         CLK_TOP_SYSPLL2_D4,
 386         CLK_TOP_UNIVPLL2_D4
 387 };
 388
 389 static const int di_parents[] = {
 390         CLK_XTAL,
 391         CLK_TOP_TVD2PLL,
 392         CLK_TOP_TVD2PLL_D2,
 393         CLK_XTAL
 394 };
 395
 396 static const int nr_osd_parents[] = {
 397         CLK_XTAL,
 398         CLK_TOP_VENCPLL,
 399         CLK_TOP_SYSPLL1_D2,
 400         CLK_TOP_SYSPLL1_D4,
 401         CLK_TOP_UNIVPLL_D5,
 402         CLK_TOP_UNIVPLL1_D2,
 403         CLK_TOP_UNIVPLL2_D2,
 404         CLK_TOP_DMPLL
 405 };
 406
 407 static const int hdmirx_bist_parents[] = {
 408         CLK_XTAL,
 409         CLK_TOP_SYSPLL_D3,
 410         CLK_XTAL,
 411         CLK_TOP_SYSPLL1_D16,
 412         CLK_TOP_SYSPLL4_D2,
 413         CLK_TOP_SYSPLL1_D4,
 414         CLK_TOP_VENCPLL,
 415         CLK_XTAL
 416 };
 417
 418 static const int intdir_parents[] = {
 419         CLK_XTAL,
 420         CLK_TOP_MMPLL,
 421         CLK_TOP_SYSPLL_D2,
 422         CLK_TOP_UNIVPLL_D2
 423 };
 424
 425 static const int asm_parents[] = {
 426         CLK_XTAL,
 427         CLK_TOP_UNIVPLL2_D4,
 428         CLK_TOP_UNIVPLL2_D2,
 429         CLK_TOP_SYSPLL_D5
 430 };
 431
 432 static const int ms_card_parents[] = {
 433         CLK_XTAL,
 434         CLK_TOP_UNIVPLL3_D8,
 435         CLK_TOP_SYSPLL4_D4
 436 };
 437
 438 static const int ethif_parents[] = {
 439         CLK_XTAL,
 440         CLK_TOP_SYSPLL1_D2,
 441         CLK_TOP_SYSPLL_D5,
 442         CLK_TOP_SYSPLL1_D4,
 443         CLK_TOP_UNIVPLL_D5,
 444         CLK_TOP_UNIVPLL1_D2,
 445         CLK_TOP_DMPLL,
 446         CLK_TOP_DMPLL_D2
 447 };
 448
 449 static const int hdmirx_parents[] = {
 450         CLK_XTAL,
 451         CLK_TOP_UNIVPLL_D52
 452 };
 453
 454 static const int cmsys_parents[] = {
 455         CLK_XTAL,
 456         CLK_TOP_SYSPLL1_D2,
 457         CLK_TOP_UNIVPLL1_D2,
 458         CLK_TOP_UNIVPLL_D5,
 459         CLK_TOP_SYSPLL_D5,
 460         CLK_TOP_SYSPLL2_D2,
 461         CLK_TOP_SYSPLL1_D4,
 462         CLK_TOP_SYSPLL3_D2,
 463         CLK_TOP_SYSPLL2_D4,
 464         CLK_TOP_SYSPLL1_D8,
 465         CLK_XTAL,
 466         CLK_XTAL,
 467         CLK_XTAL,
 468         CLK_XTAL,
 469         CLK_XTAL
 470 };
 471
 472 static const int clk_8bdac_parents[] = {
 473         CLK_TOP_32K_INTERNAL,
 474         CLK_TOP_8BDAC,
 475         CLK_XTAL,
 476         CLK_XTAL
 477 };
 478
 479 static const int aud2dvd_parents[] = {
 480         CLK_TOP_AUD_48K_TIMING,
 481         CLK_TOP_AUD_44K_TIMING
 482 };
 483
 484 static const int padmclk_parents[] = {
 485         CLK_XTAL,
 486         CLK_TOP_UNIVPLL_D26,
 487         CLK_TOP_UNIVPLL_D52,
 488         CLK_TOP_UNIVPLL_D108,
 489         CLK_TOP_UNIVPLL2_D8,
 490         CLK_TOP_UNIVPLL2_D16,
 491         CLK_TOP_UNIVPLL2_D32
 492 };
 493
 494 static const int aud_mux_parents[] = {
 495         CLK_XTAL,
 496         CLK_TOP_AUD1PLL_98M,
 497         CLK_TOP_AUD2PLL_90M,
 498         CLK_TOP_HADDS2PLL_98M,
 499         CLK_TOP_AUD_EXTCK1_DIV,
 500         CLK_TOP_AUD_EXTCK2_DIV
 501 };
 502
 503 static const int aud_src_parents[] = {
 504         CLK_TOP_AUD_MUX1_SEL,
 505         CLK_TOP_AUD_MUX2_SEL
 506 };
 507
 508 static const struct mtk_composite top_muxes[] = {
 509         MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
 510         MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
 511         MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
 512         MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31,
 513                        CLK_DOMAIN_SCPSYS),
 514
 515         MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
 516         MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15),
 517         MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23,
 518                        CLK_DOMAIN_SCPSYS),
 519         MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31),
 520
 521         MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
 522         MUX_GATE(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15),
 523         MUX_GATE(CLK_TOP_USB20_SEL, usb20_parents, 0x60, 16, 2, 23),
 524         MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_parents, 0x60, 24, 3, 31),
 525
 526         MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_parents, 0x70, 0, 3, 7),
 527         MUX_GATE(CLK_TOP_MSDC30_2_SEL, msdc30_parents, 0x70, 8, 3, 15),
 528         MUX_GATE(CLK_TOP_AUDIO_SEL, msdc30_parents, 0x70, 16, 1, 23),
 529         MUX_GATE(CLK_TOP_AUDINTBUS_SEL, aud_intbus_parents, 0x70, 24, 3, 31),
 530
 531         MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 0, 4, 7),
 532         MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 8, 2, 15),
 533         MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_tve_parents, 0x80, 16, 3, 23),
 534         MUX_GATE(CLK_TOP_DPI1_SEL, dpi1_parents, 0x80, 24, 2, 31),
 535
 536         MUX_GATE(CLK_TOP_TVE_SEL, dpi0_tve_parents, 0x90, 0, 3, 7),
 537         MUX_GATE(CLK_TOP_HDMI_SEL, hdmi_parents, 0x90, 8, 2, 15),
 538         MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
 539
 540         MUX_GATE(CLK_TOP_RTC_SEL, rtc_parents, 0xA0, 0, 2, 7),
 541         MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0xA0, 8, 3, 15),
 542         MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, emmc_hclk_parents, 0xA0, 24, 2, 31),
 543
 544         MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0xB0, 0, 3, 7),
 545         MUX_GATE(CLK_TOP_DI_SEL, di_parents, 0xB0, 8, 2, 15),
 546         MUX_GATE(CLK_TOP_NR_SEL, nr_osd_parents, 0xB0, 16, 3, 23),
 547         MUX_GATE(CLK_TOP_OSD_SEL, nr_osd_parents, 0xB0, 24, 3, 31),
 548
 549         MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, hdmirx_bist_parents, 0xC0, 0, 3, 7),
 550         MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0xC0, 8, 2, 15),
 551         MUX_GATE(CLK_TOP_ASM_I_SEL, asm_parents, 0xC0, 16, 2, 23),
 552         MUX_GATE(CLK_TOP_ASM_M_SEL, asm_parents, 0xC0, 24, 3, 31),
 553
 554         MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7),
 555         MUX_GATE(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23),
 556         MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31,
 557                        CLK_DOMAIN_SCPSYS),
 558
 559         MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7),
 560         MUX_GATE(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15),
 561         MUX_GATE(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xE0, 16, 4, 23),
 562
 563         MUX_GATE(CLK_TOP_SPI1_SEL, spi_parents, 0xE0, 24, 3, 31),
 564         MUX_GATE(CLK_TOP_SPI2_SEL, spi_parents, 0xF0, 0, 3, 7),
 565         MUX_GATE(CLK_TOP_8BDAC_SEL, clk_8bdac_parents, 0xF0, 8, 2, 15),
 566         MUX_GATE(CLK_TOP_AUD2DVD_SEL, aud2dvd_parents, 0xF0, 16, 1, 23),
 567
 568         MUX(CLK_TOP_PADMCLK_SEL, padmclk_parents, 0x100, 0, 3),
 569
 570         MUX(CLK_TOP_AUD_MUX1_SEL, aud_mux_parents, 0x12c, 0, 3),
 571         MUX(CLK_TOP_AUD_MUX2_SEL, aud_mux_parents, 0x12c, 3, 3),
 572         MUX(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3),
 573
 574         MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, aud_src_parents, 0x12c, 15, 1, 23),
 575         MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, aud_src_parents, 0x12c, 16, 1, 24),
 576         MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, aud_src_parents, 0x12c, 17, 1, 25),
 577         MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, aud_src_parents, 0x12c, 18, 1, 26),
 578         MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, aud_src_parents, 0x12c, 19, 1, 27),
 579         MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, aud_src_parents, 0x12c, 20, 1, 28),
 580 };
 581
 582 /* infracfg */
 583 static const struct mtk_gate_regs infra_cg_regs = {
 584         .set_ofs = 0x40,
 585         .clr_ofs = 0x44,
 586         .sta_ofs = 0x48,
 587 };
 588
 589 #define GATE_INFRA(_id, _parent, _shift) {                      \
 590                 .id = _id,                                      \
 591                 .parent = _parent,                              \
 592                 .regs = &infra_cg_regs,                         \
 593                 .shift = _shift,                                \
 594                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
 595         }
 596
 597 static const struct mtk_gate infra_cgs[] = {
 598         GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0),
 599         GATE_INFRA(CLK_INFRA_SMI, CLK_TOP_MM_SEL, 1),
 600         GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2),
 601         GATE_INFRA(CLK_INFRA_AUD_SPLIN_B, CLK_TOP_HADDS2PLL_294M, 4),
 602         GATE_INFRA(CLK_INFRA_AUDIO, CLK_XTAL, 5),
 603         GATE_INFRA(CLK_INFRA_EFUSE, CLK_XTAL, 6),
 604         GATE_INFRA(CLK_INFRA_L2C_SRAM, CLK_TOP_MM_SEL, 7),
 605         GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8),
 606         GATE_INFRA(CLK_INFRA_CONNMCU, CLK_TOP_WBG_DIG_416M, 12),
 607         GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 13),
 608         GATE_INFRA(CLK_INFRA_RAMBUFIF, CLK_TOP_MEM_SEL, 14),
 609         GATE_INFRA(CLK_INFRA_CPUM, CLK_TOP_MEM_SEL, 15),
 610         GATE_INFRA(CLK_INFRA_KP, CLK_TOP_AXI_SEL, 16),
 611         GATE_INFRA(CLK_INFRA_CEC, CLK_TOP_RTC_SEL, 18),
 612         GATE_INFRA(CLK_INFRA_IRRX, CLK_TOP_AXI_SEL, 19),
 613         GATE_INFRA(CLK_INFRA_PMICSPI, CLK_TOP_PMICSPI_SEL, 22),
 614         GATE_INFRA(CLK_INFRA_PMICWRAP, CLK_TOP_AXI_SEL, 23),
 615         GATE_INFRA(CLK_INFRA_DDCCI, CLK_TOP_AXI_SEL, 24),
 616 };
 617
 618 /* pericfg */
 619 static const struct mtk_gate_regs peri0_cg_regs = {
 620         .set_ofs = 0x8,
 621         .clr_ofs = 0x10,
 622         .sta_ofs = 0x18,
 623 };
 624
 625 static const struct mtk_gate_regs peri1_cg_regs = {
 626         .set_ofs = 0xC,
 627         .clr_ofs = 0x14,
 628         .sta_ofs = 0x1C,
 629 };
 630
 631 #define GATE_PERI0(_id, _parent, _shift) {                      \
 632                 .id = _id,                                      \
 633                 .parent = _parent,                              \
 634                 .regs = &peri0_cg_regs,                         \
 635                 .shift = _shift,                                \
 636                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
 637         }
 638
 639 #define GATE_PERI1(_id, _parent, _shift) {                      \
 640                 .id = _id,                                      \
 641                 .parent = _parent,                              \
 642                 .regs = &peri1_cg_regs,                         \
 643                 .shift = _shift,                                \
 644                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
 645         }
 646
 647 static const struct mtk_gate peri_cgs[] = {
 648         GATE_PERI0(CLK_PERI_NFI, CLK_TOP_NFI2X_SEL, 0),
 649         GATE_PERI0(CLK_PERI_THERM, CLK_TOP_AXI_SEL, 1),
 650         GATE_PERI0(CLK_PERI_PWM1, CLK_TOP_AXISEL_D4, 2),
 651         GATE_PERI0(CLK_PERI_PWM2, CLK_TOP_AXISEL_D4, 3),
 652         GATE_PERI0(CLK_PERI_PWM3, CLK_TOP_AXISEL_D4, 4),
 653         GATE_PERI0(CLK_PERI_PWM4, CLK_TOP_AXISEL_D4, 5),
 654         GATE_PERI0(CLK_PERI_PWM5, CLK_TOP_AXISEL_D4, 6),
 655         GATE_PERI0(CLK_PERI_PWM6, CLK_TOP_AXISEL_D4, 7),
 656         GATE_PERI0(CLK_PERI_PWM7, CLK_TOP_AXISEL_D4, 8),
 657         GATE_PERI0(CLK_PERI_PWM, CLK_TOP_AXI_SEL, 9),
 658         GATE_PERI0(CLK_PERI_USB0, CLK_TOP_USB20_SEL, 10),
 659         GATE_PERI0(CLK_PERI_USB1, CLK_TOP_USB20_SEL, 11),
 660         GATE_PERI0(CLK_PERI_AP_DMA, CLK_TOP_AXI_SEL, 12),
 661         GATE_PERI0(CLK_PERI_MSDC30_0, CLK_TOP_MSDC30_0_SEL, 13),
 662         GATE_PERI0(CLK_PERI_MSDC30_1, CLK_TOP_MSDC30_1_SEL, 14),
 663         GATE_PERI0(CLK_PERI_MSDC30_2, CLK_TOP_MSDC30_2_SEL, 15),
 664         GATE_PERI0(CLK_PERI_MSDC30_3, CLK_TOP_MSDC30_3_SEL, 16),
 665         GATE_PERI0(CLK_PERI_MSDC50_3, CLK_TOP_EMMC_HCLK_SEL, 17),
 666         GATE_PERI0(CLK_PERI_NLI, CLK_TOP_AXI_SEL, 18),
 667         GATE_PERI0(CLK_PERI_UART0, CLK_TOP_AXI_SEL, 19),
 668         GATE_PERI0(CLK_PERI_UART1, CLK_TOP_AXI_SEL, 20),
 669         GATE_PERI0(CLK_PERI_UART2, CLK_TOP_AXI_SEL, 21),
 670         GATE_PERI0(CLK_PERI_UART3, CLK_TOP_AXI_SEL, 22),
 671         GATE_PERI0(CLK_PERI_BTIF, CLK_TOP_AXI_SEL, 23),
 672         GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24),
 673         GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25),
 674         GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26),
 675         GATE_PERI0(CLK_PERI_I2C3, CLK_XTAL, 27),
 676         GATE_PERI0(CLK_PERI_AUXADC, CLK_XTAL, 28),
 677         GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29),
 678         GATE_PERI0(CLK_PERI_ETH, CLK_XTAL, 30),
 679         GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31),
 680
 681         GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0),
 682         GATE_PERI1(CLK_PERI_USB_SLV, CLK_TOP_AXI_SEL, 1),
 683         GATE_PERI1(CLK_PERI_GCPU, CLK_TOP_AXI_SEL, 2),
 684         GATE_PERI1(CLK_PERI_NFI_ECC, CLK_TOP_NFI1X_PAD, 3),
 685         GATE_PERI1(CLK_PERI_NFI_PAD, CLK_TOP_NFI1X_PAD, 4),
 686         GATE_PERI1(CLK_PERI_FLASH, CLK_TOP_NFI2X_SEL, 5),
 687         GATE_PERI1(CLK_PERI_HOST89_INT, CLK_TOP_AXI_SEL, 6),
 688         GATE_PERI1(CLK_PERI_HOST89_SPI, CLK_TOP_SPI0_SEL, 7),
 689         GATE_PERI1(CLK_PERI_HOST89_DVD, CLK_TOP_AUD2DVD_SEL, 8),
 690         GATE_PERI1(CLK_PERI_SPI1, CLK_TOP_SPI1_SEL, 9),
 691         GATE_PERI1(CLK_PERI_SPI2, CLK_TOP_SPI2_SEL, 10),
 692         GATE_PERI1(CLK_PERI_FCI, CLK_TOP_MS_CARD_SEL, 11),
 693 };
 694
 695 /* ethsys and hifsys */
 696 static const struct mtk_gate_regs eth_hif_cg_regs = {
 697         .sta_ofs = 0x30,
 698 };
 699
 700 #define GATE_ETH_HIF(_id, _parent, _shift, _flag) {             \
 701                 .id = _id,                                      \
 702                 .parent = _parent,                              \
 703                 .regs = &eth_hif_cg_regs,                       \
 704                 .shift = _shift,                                \
 705                 .flags = CLK_GATE_NO_SETCLR_INV | (_flag),      \
 706         }
 707
 708 #define GATE_ETH_HIF0(_id, _parent, _shift)                             \
 709         GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_APMIXED)
 710
 711 #define GATE_ETH_HIF1(_id, _parent, _shift)                             \
 712         GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_TOPCKGEN)
 713
 714 static const struct mtk_gate eth_cgs[] = {
 715         GATE_ETH_HIF1(CLK_ETHSYS_HSDMA, CLK_TOP_ETHIF_SEL, 5),
 716         GATE_ETH_HIF1(CLK_ETHSYS_ESW, CLK_TOP_ETHPLL_500M, 6),
 717         GATE_ETH_HIF0(CLK_ETHSYS_GP2, CLK_APMIXED_TRGPLL, 7),
 718         GATE_ETH_HIF1(CLK_ETHSYS_GP1, CLK_TOP_ETHPLL_500M, 8),
 719         GATE_ETH_HIF1(CLK_ETHSYS_PCM, CLK_TOP_ETHIF_SEL, 11),
 720         GATE_ETH_HIF1(CLK_ETHSYS_GDMA, CLK_TOP_ETHIF_SEL, 14),
 721         GATE_ETH_HIF1(CLK_ETHSYS_I2S, CLK_TOP_ETHIF_SEL, 17),
 722         GATE_ETH_HIF1(CLK_ETHSYS_CRYPTO, CLK_TOP_ETHIF_SEL, 29),
 723 };
 724
 725 static const struct mtk_gate hif_cgs[] = {
 726         GATE_ETH_HIF1(CLK_HIFSYS_USB0PHY, CLK_TOP_ETHPLL_500M, 21),
 727         GATE_ETH_HIF1(CLK_HIFSYS_USB1PHY, CLK_TOP_ETHPLL_500M, 22),
 728         GATE_ETH_HIF1(CLK_HIFSYS_PCIE0, CLK_TOP_ETHPLL_500M, 24),
 729         GATE_ETH_HIF1(CLK_HIFSYS_PCIE1, CLK_TOP_ETHPLL_500M, 25),
 730         GATE_ETH_HIF1(CLK_HIFSYS_PCIE2, CLK_TOP_ETHPLL_500M, 26),
 731 };
 732
 733 static const struct mtk_clk_tree mt7623_clk_tree = {
 734         .xtal_rate = 26 * MHZ,
 735         .xtal2_rate = 26 * MHZ,
 736         .fdivs_offs = CLK_TOP_SYSPLL,
 737         .muxes_offs = CLK_TOP_AXI_SEL,
 738         .plls = apmixed_plls,
 739         .fclks = top_fixed_clks,
 740         .fdivs = top_fixed_divs,
 741         .muxes = top_muxes,
 742 };
 743
 744 static int mt7623_mcucfg_probe(struct udevice *dev)
 745 {
 746         void __iomem *base;
 747
 748         base = dev_read_addr_ptr(dev);
 749         if (!base)
 750                 return -ENOENT;
 751
 752         clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
 753                         AXI_DIV_SEL(0x12));
 754
 755         return 0;
 756 }
 757
 758 static int mt7623_apmixedsys_probe(struct udevice *dev)
 759 {
 760         struct mtk_clk_priv *priv = dev_get_priv(dev);
 761         int ret;
 762
 763         ret = mtk_common_clk_init(dev, &mt7623_clk_tree);
 764         if (ret)
 765                 return ret;
 766
 767         /* reduce clock square disable time */
 768         writel(0x50001, priv->base + MT7623_CLKSQ_STB_CON0);
 769         /* extend control timing to 1us */
 770         writel(0x888, priv->base + MT7623_PLL_ISO_CON0);
 771
 772         return 0;
 773 }
 774
 775 static int mt7623_topckgen_probe(struct udevice *dev)
 776 {
 777         return mtk_common_clk_init(dev, &mt7623_clk_tree);
 778 }
 779
 780 static int mt7623_infracfg_probe(struct udevice *dev)
 781 {
 782         return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, infra_cgs);
 783 }
 784
 785 static int mt7623_pericfg_probe(struct udevice *dev)
 786 {
 787         return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, peri_cgs);
 788 }
 789
 790 static int mt7623_hifsys_probe(struct udevice *dev)
 791 {
 792         return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, hif_cgs);
 793 }
 794
 795 static int mt7623_ethsys_probe(struct udevice *dev)
 796 {
 797         return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs);
 798 }
 799
 800 static int mt7623_ethsys_hifsys_bind(struct udevice *dev)
 801 {
 802         int ret = 0;
 803
 804 #if CONFIG_IS_ENABLED(RESET_MEDIATEK)
 805         ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
 806         if (ret)
 807                 debug("Warning: failed to bind reset controller\n");
 808 #endif
 809
 810         return ret;
 811 }
 812
 813 static const struct udevice_id mt7623_apmixed_compat[] = {
 814         { .compatible = "mediatek,mt7623-apmixedsys" },
 815         { }
 816 };
 817
 818 static const struct udevice_id mt7623_topckgen_compat[] = {
 819         { .compatible = "mediatek,mt7623-topckgen" },
 820         { }
 821 };
 822
 823 static const struct udevice_id mt7623_infracfg_compat[] = {
 824         { .compatible = "mediatek,mt7623-infracfg", },
 825         { }
 826 };
 827
 828 static const struct udevice_id mt7623_pericfg_compat[] = {
 829         { .compatible = "mediatek,mt7623-pericfg", },
 830         { }
 831 };
 832
 833 static const struct udevice_id mt7623_ethsys_compat[] = {
 834         { .compatible = "mediatek,mt7623-ethsys" },
 835         { }
 836 };
 837
 838 static const struct udevice_id mt7623_hifsys_compat[] = {
 839         { .compatible = "mediatek,mt7623-hifsys" },
 840         { }
 841 };
 842
 843 static const struct udevice_id mt7623_mcucfg_compat[] = {
 844         { .compatible = "mediatek,mt7623-mcucfg" },
 845         { }
 846 };
 847
 848 U_BOOT_DRIVER(mtk_mcucfg) = {
 849         .name = "mt7623-mcucfg",
 850         .id = UCLASS_SYSCON,
 851         .of_match = mt7623_mcucfg_compat,
 852         .probe = mt7623_mcucfg_probe,
 853         .flags = DM_FLAG_PRE_RELOC,
 854 };
 855
 856 U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
 857         .name = "mt7623-clock-apmixedsys",
 858         .id = UCLASS_CLK,
 859         .of_match = mt7623_apmixed_compat,
 860         .probe = mt7623_apmixedsys_probe,
 861         .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
 862         .ops = &mtk_clk_apmixedsys_ops,
 863         .flags = DM_FLAG_PRE_RELOC,
 864 };
 865
 866 U_BOOT_DRIVER(mtk_clk_topckgen) = {
 867         .name = "mt7623-clock-topckgen",
 868         .id = UCLASS_CLK,
 869         .of_match = mt7623_topckgen_compat,
 870         .probe = mt7623_topckgen_probe,
 871         .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
 872         .ops = &mtk_clk_topckgen_ops,
 873         .flags = DM_FLAG_PRE_RELOC,
 874 };
 875
 876 U_BOOT_DRIVER(mtk_clk_infracfg) = {
 877         .name = "mt7623-infracfg",
 878         .id = UCLASS_CLK,
 879         .of_match = mt7623_infracfg_compat,
 880         .probe = mt7623_infracfg_probe,
 881         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 882         .ops = &mtk_clk_gate_ops,
 883         .flags = DM_FLAG_PRE_RELOC,
 884 };
 885
 886 U_BOOT_DRIVER(mtk_clk_pericfg) = {
 887         .name = "mt7623-pericfg",
 888         .id = UCLASS_CLK,
 889         .of_match = mt7623_pericfg_compat,
 890         .probe = mt7623_pericfg_probe,
 891         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 892         .ops = &mtk_clk_gate_ops,
 893         .flags = DM_FLAG_PRE_RELOC,
 894 };
 895
 896 U_BOOT_DRIVER(mtk_clk_hifsys) = {
 897         .name = "mt7623-clock-hifsys",
 898         .id = UCLASS_CLK,
 899         .of_match = mt7623_hifsys_compat,
 900         .probe = mt7623_hifsys_probe,
 901         .bind = mt7623_ethsys_hifsys_bind,
 902         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 903         .ops = &mtk_clk_gate_ops,
 904 };
 905
 906 U_BOOT_DRIVER(mtk_clk_ethsys) = {
 907         .name = "mt7623-clock-ethsys",
 908         .id = UCLASS_CLK,
 909         .of_match = mt7623_ethsys_compat,
 910         .probe = mt7623_ethsys_probe,
 911         .bind = mt7623_ethsys_hifsys_bind,
 912         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 913         .ops = &mtk_clk_gate_ops,
 914 };