drivers/clk/mediatek/clk-mt7622.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MediaTek clock driver for MT7622 SoC
   4  *
   5  * Copyright (C) 2019 MediaTek Inc.
   6  * Author: Ryder Lee <ryder.lee@mediatek.com>
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <asm/arch-mediatek/reset.h>
  12 #include <asm/io.h>
  13 #include <dt-bindings/clock/mt7622-clk.h>
  14
  15 #include "clk-mtk.h"
  16
  17 #define MT7622_CLKSQ_STB_CON0           0x20
  18 #define MT7622_PLL_ISO_CON0             0x2c
  19 #define MT7622_PLL_FMAX                 (2500UL * MHZ)
  20 #define MT7622_CON0_RST_BAR             BIT(24)
  21
  22 #define MCU_AXI_DIV                     0x640
  23 #define AXI_DIV_MSK                     GENMASK(4, 0)
  24 #define AXI_DIV_SEL(x)                  (x)
  25
  26 #define MCU_BUS_MUX                     0x7c0
  27 #define MCU_BUS_MSK                     GENMASK(10, 9)
  28 #define MCU_BUS_SEL(x)                  ((x) << 9)
  29
  30 /* apmixedsys */
  31 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,   \
  32             _pd_shift, _pcw_reg, _pcw_shift) {                          \
  33                 .id = _id,                                              \
  34                 .reg = _reg,                                            \
  35                 .pwr_reg = _pwr_reg,                                    \
  36                 .en_mask = _en_mask,                                    \
  37                 .rst_bar_mask = MT7622_CON0_RST_BAR,                    \
  38                 .fmax = MT7622_PLL_FMAX,                                \
  39                 .flags = _flags,                                        \
  40                 .pcwbits = _pcwbits,                                    \
  41                 .pd_reg = _pd_reg,                                      \
  42                 .pd_shift = _pd_shift,                                  \
  43                 .pcw_reg = _pcw_reg,                                    \
  44                 .pcw_shift = _pcw_shift,                                \
  45         }
  46
  47 static const struct mtk_pll_data apmixed_plls[] = {
  48         PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
  49             21, 0x204, 24, 0x204, 0),
  50         PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
  51             21, 0x214, 24, 0x214, 0),
  52         PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
  53             7, 0x224, 24, 0x224, 14),
  54         PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
  55             21, 0x300, 1, 0x304, 0),
  56         PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
  57             21, 0x314, 1, 0x318, 0),
  58         PLL(CLK_APMIXED_AUD1PLL, 0x324, 0x330, 0x1, 0,
  59             31, 0x324, 1, 0x328, 0),
  60         PLL(CLK_APMIXED_AUD2PLL, 0x334, 0x340, 0x1, 0,
  61             31, 0x334, 1, 0x338, 0),
  62         PLL(CLK_APMIXED_TRGPLL, 0x344, 0x354, 0x1, 0,
  63             21, 0x344, 1, 0x348, 0),
  64         PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
  65             21, 0x358, 1, 0x35c, 0),
  66 };
  67
  68 /* topckgen */
  69 #define FACTOR0(_id, _parent, _mult, _div)                      \
  70         FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
  71
  72 #define FACTOR1(_id, _parent, _mult, _div)                      \
  73         FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
  74
  75 #define FACTOR2(_id, _parent, _mult, _div)                      \
  76         FACTOR(_id, _parent, _mult, _div, 0)
  77
  78 static const struct mtk_fixed_clk top_fixed_clks[] = {
  79         FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000),
  80         FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000),
  81         FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000),
  82         FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000),
  83         FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000),
  84         FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000),
  85         FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333),
  86         FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000),
  87         FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000),
  88         FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000),
  89 };
  90
  91 static const struct mtk_fixed_factor top_fixed_divs[] = {
  92         FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4),
  93         FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
  94         FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125),
  95         FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
  96         FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1),
  97         FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024),
  98         FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1),
  99         FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
 100         FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
 101         FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
 102         FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
 103         FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
 104         FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
 105         FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
 106         FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
 107         FACTOR0(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10),
 108         FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20),
 109         FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
 110         FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28),
 111         FACTOR0(CLK_TOP_SYSPLL4_D16, CLK_APMIXED_MAINPLL, 1, 112),
 112         FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2),
 113         FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2),
 114         FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
 115         FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
 116         FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
 117         FACTOR1(CLK_TOP_UNIVPLL1_D16, CLK_TOP_UNIVPLL, 1, 32),
 118         FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
 119         FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
 120         FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
 121         FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL, 1, 48),
 122         FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
 123         FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10),
 124         FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20),
 125         FACTOR1(CLK_TOP_UNIVPLL3_D16, CLK_TOP_UNIVPLL, 1, 80),
 126         FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7),
 127         FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320),
 128         FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25),
 129         FACTOR0(CLK_TOP_SGMIIPLL, CLK_APMIXED_SGMIPLL, 1, 1),
 130         FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2),
 131         FACTOR0(CLK_TOP_AUD1PLL, CLK_APMIXED_AUD1PLL, 1, 1),
 132         FACTOR0(CLK_TOP_AUD2PLL, CLK_APMIXED_AUD2PLL, 1, 1),
 133         FACTOR1(CLK_TOP_AUD_I2S2_MCK, CLK_TOP_I2S2_MCK_SEL, 1, 2),
 134         FACTOR1(CLK_TOP_TO_USB3_REF, CLK_TOP_UNIVPLL2_D4, 1, 4),
 135         FACTOR1(CLK_TOP_PCIE1_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
 136         FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
 137         FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1),
 138 };
 139
 140 static const int axi_parents[] = {
 141         CLK_XTAL,
 142         CLK_TOP_SYSPLL1_D2,
 143         CLK_TOP_SYSPLL_D5,
 144         CLK_TOP_SYSPLL1_D4,
 145         CLK_TOP_UNIVPLL_D5,
 146         CLK_TOP_UNIVPLL2_D2,
 147         CLK_TOP_UNIVPLL_D7
 148 };
 149
 150 static const int mem_parents[] = {
 151         CLK_XTAL,
 152         CLK_TOP_DMPLL
 153 };
 154
 155 static const int ddrphycfg_parents[] = {
 156         CLK_XTAL,
 157         CLK_TOP_SYSPLL1_D8
 158 };
 159
 160 static const int eth_parents[] = {
 161         CLK_XTAL,
 162         CLK_TOP_SYSPLL1_D2,
 163         CLK_TOP_UNIVPLL1_D2,
 164         CLK_TOP_SYSPLL1_D4,
 165         CLK_TOP_UNIVPLL_D5,
 166         -1,
 167         CLK_TOP_UNIVPLL_D7
 168 };
 169
 170 static const int pwm_parents[] = {
 171         CLK_XTAL,
 172         CLK_TOP_UNIVPLL2_D4
 173 };
 174
 175 static const int f10m_ref_parents[] = {
 176         CLK_XTAL,
 177         CLK_TOP_SYSPLL4_D16
 178 };
 179
 180 static const int nfi_infra_parents[] = {
 181         CLK_XTAL,
 182         CLK_XTAL,
 183         CLK_XTAL,
 184         CLK_XTAL,
 185         CLK_XTAL,
 186         CLK_XTAL,
 187         CLK_XTAL,
 188         CLK_XTAL,
 189         CLK_TOP_UNIVPLL2_D8,
 190         CLK_TOP_SYSPLL1_D8,
 191         CLK_TOP_UNIVPLL1_D8,
 192         CLK_TOP_SYSPLL4_D2,
 193         CLK_TOP_UNIVPLL2_D4,
 194         CLK_TOP_UNIVPLL3_D2,
 195         CLK_TOP_SYSPLL1_D4
 196 };
 197
 198 static const int flash_parents[] = {
 199         CLK_XTAL,
 200         CLK_TOP_UNIVPLL_D80_D4,
 201         CLK_TOP_SYSPLL2_D8,
 202         CLK_TOP_SYSPLL3_D4,
 203         CLK_TOP_UNIVPLL3_D4,
 204         CLK_TOP_UNIVPLL1_D8,
 205         CLK_TOP_SYSPLL2_D4,
 206         CLK_TOP_UNIVPLL2_D4
 207 };
 208
 209 static const int uart_parents[] = {
 210         CLK_XTAL,
 211         CLK_TOP_UNIVPLL2_D8
 212 };
 213
 214 static const int spi0_parents[] = {
 215         CLK_XTAL,
 216         CLK_TOP_SYSPLL3_D2,
 217         CLK_XTAL,
 218         CLK_TOP_SYSPLL2_D4,
 219         CLK_TOP_SYSPLL4_D2,
 220         CLK_TOP_UNIVPLL2_D4,
 221         CLK_TOP_UNIVPLL1_D8,
 222         CLK_XTAL
 223 };
 224
 225 static const int spi1_parents[] = {
 226         CLK_XTAL,
 227         CLK_TOP_SYSPLL3_D2,
 228         CLK_XTAL,
 229         CLK_TOP_SYSPLL4_D4,
 230         CLK_TOP_SYSPLL4_D2,
 231         CLK_TOP_UNIVPLL2_D4,
 232         CLK_TOP_UNIVPLL1_D8,
 233         CLK_XTAL
 234 };
 235
 236 static const int msdc30_0_parents[] = {
 237         CLK_XTAL,
 238         CLK_TOP_UNIVPLL2_D16,
 239         CLK_TOP_UNIV48M
 240 };
 241
 242 static const int a1sys_hp_parents[] = {
 243         CLK_XTAL,
 244         CLK_TOP_AUD1PLL,
 245         CLK_TOP_AUD2PLL,
 246         CLK_XTAL
 247 };
 248
 249 static const int intdir_parents[] = {
 250         CLK_XTAL,
 251         CLK_TOP_SYSPLL1_D2,
 252         CLK_TOP_UNIVPLL_D2,
 253         CLK_TOP_SGMIIPLL
 254 };
 255
 256 static const int aud_intbus_parents[] = {
 257         CLK_XTAL,
 258         CLK_TOP_SYSPLL1_D4,
 259         CLK_TOP_SYSPLL4_D2,
 260         CLK_TOP_SYSPLL3_D2
 261 };
 262
 263 static const int pmicspi_parents[] = {
 264         CLK_XTAL,
 265         -1,
 266         -1,
 267         -1,
 268         -1,
 269         CLK_TOP_UNIVPLL2_D16
 270 };
 271
 272 static const int atb_parents[] = {
 273         CLK_XTAL,
 274         CLK_TOP_SYSPLL1_D2,
 275         CLK_TOP_SYSPLL_D5
 276 };
 277
 278 static const int audio_parents[] = {
 279         CLK_XTAL,
 280         CLK_TOP_SYSPLL3_D4,
 281         CLK_TOP_SYSPLL4_D4,
 282         CLK_TOP_UNIVPLL1_D16
 283 };
 284
 285 static const int usb20_parents[] = {
 286         CLK_XTAL,
 287         CLK_TOP_UNIVPLL3_D4,
 288         CLK_TOP_SYSPLL1_D8,
 289         CLK_XTAL
 290 };
 291
 292 static const int aud1_parents[] = {
 293         CLK_XTAL,
 294         CLK_TOP_AUD1PLL
 295 };
 296
 297 static const int asm_l_parents[] = {
 298         CLK_XTAL,
 299         CLK_TOP_SYSPLL_D5,
 300         CLK_TOP_UNIVPLL2_D2,
 301         CLK_TOP_UNIVPLL2_D4
 302 };
 303
 304 static const int apll1_ck_parents[] = {
 305         CLK_TOP_AUD1_SEL,
 306         CLK_TOP_AUD2_SEL
 307 };
 308
 309 static const struct mtk_composite top_muxes[] = {
 310         /* CLK_CFG_0 */
 311         MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
 312         MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
 313         MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
 314         MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
 315
 316         /* CLK_CFG_1 */
 317         MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
 318         MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
 319         MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
 320         MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
 321
 322         /* CLK_CFG_2 */
 323         MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
 324         MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
 325         MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23),
 326         MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31),
 327
 328         /* CLK_CFG_3 */
 329         MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
 330         MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15),
 331         MUX_GATE(CLK_TOP_A1SYS_HP_SEL, a1sys_hp_parents, 0x70, 16, 3, 23),
 332         MUX_GATE(CLK_TOP_A2SYS_HP_SEL, a1sys_hp_parents, 0x70, 24, 3, 31),
 333
 334         /* CLK_CFG_4 */
 335         MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7),
 336         MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15),
 337         MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23),
 338         MUX_GATE(CLK_TOP_SCP_SEL, ddrphycfg_parents, 0x80, 24, 2, 31),
 339
 340         /* CLK_CFG_5 */
 341         MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
 342         MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15,
 343                        CLK_DOMAIN_SCPSYS),
 344         MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23),
 345         MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),
 346
 347         /* CLK_CFG_6 */
 348         MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
 349         MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15),
 350         MUX_GATE(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23),
 351         MUX_GATE(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31),
 352
 353         /* CLK_CFG_7 */
 354         MUX_GATE(CLK_TOP_ASM_L_SEL, asm_l_parents, 0xB0, 0, 2, 7),
 355         MUX_GATE(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15),
 356         MUX_GATE(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23),
 357
 358         /* CLK_AUDDIV_0 */
 359         MUX(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1),
 360         MUX(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1),
 361         MUX(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1),
 362         MUX(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1),
 363         MUX(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1),
 364         MUX(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1),
 365 };
 366
 367 /* infracfg */
 368 static const struct mtk_gate_regs infra_cg_regs = {
 369         .set_ofs = 0x40,
 370         .clr_ofs = 0x44,
 371         .sta_ofs = 0x48,
 372 };
 373
 374 #define GATE_INFRA(_id, _parent, _shift) {                      \
 375                 .id = _id,                                      \
 376                 .parent = _parent,                              \
 377                 .regs = &infra_cg_regs,                         \
 378                 .shift = _shift,                                \
 379                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
 380         }
 381
 382 static const struct mtk_gate infra_cgs[] = {
 383         GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_AXI_SEL, 0),
 384         GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2),
 385         GATE_INFRA(CLK_INFRA_AUDIO_PD, CLK_TOP_AUD_INTBUS_SEL, 5),
 386         GATE_INFRA(CLK_INFRA_IRRX_PD, CLK_TOP_IRRX_SEL, 16),
 387         GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_F10M_REF_SEL, 18),
 388         GATE_INFRA(CLK_INFRA_PMIC_PD, CLK_TOP_PMICSPI_SEL, 22),
 389 };
 390
 391 /* pericfg */
 392 static const struct mtk_gate_regs peri0_cg_regs = {
 393         .set_ofs = 0x8,
 394         .clr_ofs = 0x10,
 395         .sta_ofs = 0x18,
 396 };
 397
 398 static const struct mtk_gate_regs peri1_cg_regs = {
 399         .set_ofs = 0xC,
 400         .clr_ofs = 0x14,
 401         .sta_ofs = 0x1C,
 402 };
 403
 404 #define GATE_PERI0(_id, _parent, _shift) {                      \
 405                 .id = _id,                                      \
 406                 .parent = _parent,                              \
 407                 .regs = &peri0_cg_regs,                         \
 408                 .shift = _shift,                                \
 409                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
 410         }
 411
 412 #define GATE_PERI1(_id, _parent, _shift) {                      \
 413                 .id = _id,                                      \
 414                 .parent = _parent,                              \
 415                 .regs = &peri1_cg_regs,                         \
 416                 .shift = _shift,                                \
 417                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
 418         }
 419
 420 static const struct mtk_gate peri_cgs[] = {
 421         /* PERI0 */
 422         GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1),
 423         GATE_PERI0(CLK_PERI_PWM1_PD, CLK_XTAL, 2),
 424         GATE_PERI0(CLK_PERI_PWM2_PD, CLK_XTAL, 3),
 425         GATE_PERI0(CLK_PERI_PWM3_PD, CLK_XTAL, 4),
 426         GATE_PERI0(CLK_PERI_PWM4_PD, CLK_XTAL, 5),
 427         GATE_PERI0(CLK_PERI_PWM5_PD, CLK_XTAL, 6),
 428         GATE_PERI0(CLK_PERI_PWM6_PD, CLK_XTAL, 7),
 429         GATE_PERI0(CLK_PERI_PWM7_PD, CLK_XTAL, 8),
 430         GATE_PERI0(CLK_PERI_PWM_PD, CLK_XTAL, 9),
 431         GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12),
 432         GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13),
 433         GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14),
 434         GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_AXI_SEL, 17),
 435         GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18),
 436         GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19),
 437         GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20),
 438         GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22),
 439         GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23),
 440         GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24),
 441         GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25),
 442         GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26),
 443         GATE_PERI0(CLK_PERI_AUXADC_PD, CLK_XTAL, 27),
 444         GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28),
 445         GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29),
 446         GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30),
 447         GATE_PERI1(CLK_PERI_NFIECC_PD, CLK_TOP_AXI_SEL, 31),
 448
 449         /* PERI1 */
 450         GATE_PERI1(CLK_PERI_FLASH_PD, CLK_TOP_FLASH_SEL, 1),
 451         GATE_PERI1(CLK_PERI_IRTX_PD, CLK_TOP_IRTX_SEL, 2),
 452 };
 453
 454 /* ethsys */
 455 static const struct mtk_gate_regs eth_cg_regs = {
 456         .sta_ofs = 0x30,
 457 };
 458
 459 #define GATE_ETH(_id, _parent, _shift) {                        \
 460                 .id = _id,                                      \
 461                 .parent = _parent,                              \
 462                 .regs = &eth_cg_regs,                           \
 463                 .shift = _shift,                                \
 464                 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,  \
 465         }
 466
 467 static const struct mtk_gate eth_cgs[] = {
 468         GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5),
 469         GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6),
 470         GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7),
 471         GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8),
 472         GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
 473 };
 474
 475 static const struct mtk_gate_regs sgmii_cg_regs = {
 476         .sta_ofs = 0xE4,
 477 };
 478
 479 #define GATE_SGMII(_id, _parent, _shift) {                      \
 480         .id = _id,                                              \
 481         .parent = _parent,                                      \
 482         .regs = &sgmii_cg_regs,                                 \
 483         .shift = _shift,                                        \
 484         .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,  \
 485 }
 486
 487 static const struct mtk_gate sgmii_cgs[] = {
 488         GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2),
 489         GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
 490         GATE_SGMII(CLK_SGMII_CDR_REF, CLK_TOP_SSUSB_CDR_REF, 4),
 491         GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
 492 };
 493
 494 static const struct mtk_clk_tree mt7622_clk_tree = {
 495         .xtal_rate = 25 * MHZ,
 496         .xtal2_rate = 25 * MHZ,
 497         .fdivs_offs = CLK_TOP_TO_USB3_SYS,
 498         .muxes_offs = CLK_TOP_AXI_SEL,
 499         .plls = apmixed_plls,
 500         .fclks = top_fixed_clks,
 501         .fdivs = top_fixed_divs,
 502         .muxes = top_muxes,
 503 };
 504
 505 static int mt7622_mcucfg_probe(struct udevice *dev)
 506 {
 507         void __iomem *base;
 508
 509         base = dev_read_addr_ptr(dev);
 510         if (!base)
 511                 return -ENOENT;
 512
 513         clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
 514                         AXI_DIV_SEL(0x12));
 515         clrsetbits_le32(base + MCU_BUS_MUX, MCU_BUS_MSK,
 516                         MCU_BUS_SEL(0x1));
 517
 518         return 0;
 519 }
 520
 521 static int mt7622_apmixedsys_probe(struct udevice *dev)
 522 {
 523         struct mtk_clk_priv *priv = dev_get_priv(dev);
 524         int ret;
 525
 526         ret = mtk_common_clk_init(dev, &mt7622_clk_tree);
 527         if (ret)
 528                 return ret;
 529
 530         /* reduce clock square disable time */
 531         // writel(0x501, priv->base + MT7622_CLKSQ_STB_CON0);
 532         writel(0x98940501, priv->base + MT7622_CLKSQ_STB_CON0);
 533
 534         /* extend pwr/iso control timing to 1us */
 535         writel(0x80008, priv->base + MT7622_PLL_ISO_CON0);
 536
 537         return 0;
 538 }
 539
 540 static int mt7622_topckgen_probe(struct udevice *dev)
 541 {
 542         return mtk_common_clk_init(dev, &mt7622_clk_tree);
 543 }
 544
 545 static int mt7622_infracfg_probe(struct udevice *dev)
 546 {
 547         return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, infra_cgs);
 548 }
 549
 550 static int mt7622_pericfg_probe(struct udevice *dev)
 551 {
 552         return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs);
 553 }
 554
 555 static int mt7622_ethsys_probe(struct udevice *dev)
 556 {
 557         return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs);
 558 }
 559
 560 static int mt7622_ethsys_bind(struct udevice *dev)
 561 {
 562         int ret = 0;
 563
 564 #if CONFIG_IS_ENABLED(RESET_MEDIATEK)
 565         ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
 566         if (ret)
 567                 debug("Warning: failed to bind reset controller\n");
 568 #endif
 569
 570         return ret;
 571 }
 572
 573 static int mt7622_sgmiisys_probe(struct udevice *dev)
 574 {
 575         return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs);
 576 }
 577
 578 static const struct udevice_id mt7622_apmixed_compat[] = {
 579         { .compatible = "mediatek,mt7622-apmixedsys" },
 580         { }
 581 };
 582
 583 static const struct udevice_id mt7622_topckgen_compat[] = {
 584         { .compatible = "mediatek,mt7622-topckgen" },
 585         { }
 586 };
 587
 588 static const struct udevice_id mt7622_infracfg_compat[] = {
 589         { .compatible = "mediatek,mt7622-infracfg", },
 590         { }
 591 };
 592
 593 static const struct udevice_id mt7622_pericfg_compat[] = {
 594         { .compatible = "mediatek,mt7622-pericfg", },
 595         { }
 596 };
 597
 598 static const struct udevice_id mt7622_ethsys_compat[] = {
 599         { .compatible = "mediatek,mt7622-ethsys", },
 600         { }
 601 };
 602
 603 static const struct udevice_id mt7622_sgmiisys_compat[] = {
 604         { .compatible = "mediatek,mt7622-sgmiisys", },
 605         { }
 606 };
 607
 608 static const struct udevice_id mt7622_mcucfg_compat[] = {
 609         { .compatible = "mediatek,mt7622-mcucfg" },
 610         { }
 611 };
 612
 613 U_BOOT_DRIVER(mtk_mcucfg) = {
 614         .name = "mt7622-mcucfg",
 615         .id = UCLASS_SYSCON,
 616         .of_match = mt7622_mcucfg_compat,
 617         .probe = mt7622_mcucfg_probe,
 618         .flags = DM_FLAG_PRE_RELOC,
 619 };
 620
 621 U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
 622         .name = "mt7622-clock-apmixedsys",
 623         .id = UCLASS_CLK,
 624         .of_match = mt7622_apmixed_compat,
 625         .probe = mt7622_apmixedsys_probe,
 626         .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
 627         .ops = &mtk_clk_apmixedsys_ops,
 628         .flags = DM_FLAG_PRE_RELOC,
 629 };
 630
 631 U_BOOT_DRIVER(mtk_clk_topckgen) = {
 632         .name = "mt7622-clock-topckgen",
 633         .id = UCLASS_CLK,
 634         .of_match = mt7622_topckgen_compat,
 635         .probe = mt7622_topckgen_probe,
 636         .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
 637         .ops = &mtk_clk_topckgen_ops,
 638         .flags = DM_FLAG_PRE_RELOC,
 639 };
 640
 641 U_BOOT_DRIVER(mtk_clk_infracfg) = {
 642         .name = "mt7622-clock-infracfg",
 643         .id = UCLASS_CLK,
 644         .of_match = mt7622_infracfg_compat,
 645         .probe = mt7622_infracfg_probe,
 646         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 647         .ops = &mtk_clk_gate_ops,
 648         .flags = DM_FLAG_PRE_RELOC,
 649 };
 650
 651 U_BOOT_DRIVER(mtk_clk_pericfg) = {
 652         .name = "mt7622-clock-pericfg",
 653         .id = UCLASS_CLK,
 654         .of_match = mt7622_pericfg_compat,
 655         .probe = mt7622_pericfg_probe,
 656         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 657         .ops = &mtk_clk_gate_ops,
 658         .flags = DM_FLAG_PRE_RELOC,
 659 };
 660
 661 U_BOOT_DRIVER(mtk_clk_ethsys) = {
 662         .name = "mt7622-clock-ethsys",
 663         .id = UCLASS_CLK,
 664         .of_match = mt7622_ethsys_compat,
 665         .probe = mt7622_ethsys_probe,
 666         .bind = mt7622_ethsys_bind,
 667         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 668         .ops = &mtk_clk_gate_ops,
 669 };
 670
 671 U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
 672         .name = "mt7622-clock-sgmiisys",
 673         .id = UCLASS_CLK,
 674         .of_match = mt7622_sgmiisys_compat,
 675         .probe = mt7622_sgmiisys_probe,
 676         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 677         .ops = &mtk_clk_gate_ops,
 678 };