1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek clock driver for MT7622 SoC
5 * Copyright (C) 2019 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
12 #include <asm/arch-mediatek/reset.h>
14 #include <dt-bindings/clock/mt7622-clk.h>
15 #include <linux/bitops.h>
19 #define MT7622_CLKSQ_STB_CON0 0x20
20 #define MT7622_PLL_ISO_CON0 0x2c
21 #define MT7622_PLL_FMAX (2500UL * MHZ)
22 #define MT7622_CON0_RST_BAR BIT(24)
24 #define MCU_AXI_DIV 0x640
25 #define AXI_DIV_MSK GENMASK(4, 0)
26 #define AXI_DIV_SEL(x) (x)
28 #define MCU_BUS_MUX 0x7c0
29 #define MCU_BUS_MSK GENMASK(10, 9)
30 #define MCU_BUS_SEL(x) ((x) << 9)
33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
34 _pd_shift, _pcw_reg, _pcw_shift) { \
37 .pwr_reg = _pwr_reg, \
38 .en_mask = _en_mask, \
39 .rst_bar_mask = MT7622_CON0_RST_BAR, \
40 .fmax = MT7622_PLL_FMAX, \
42 .pcwbits = _pcwbits, \
44 .pd_shift = _pd_shift, \
45 .pcw_reg = _pcw_reg, \
46 .pcw_shift = _pcw_shift, \
49 static const struct mtk_pll_data apmixed_plls[] = {
50 PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
51 21, 0x204, 24, 0x204, 0),
52 PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
53 21, 0x214, 24, 0x214, 0),
54 PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
55 7, 0x224, 24, 0x224, 14),
56 PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
57 21, 0x300, 1, 0x304, 0),
58 PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
59 21, 0x314, 1, 0x318, 0),
60 PLL(CLK_APMIXED_AUD1PLL, 0x324, 0x330, 0x1, 0,
61 31, 0x324, 1, 0x328, 0),
62 PLL(CLK_APMIXED_AUD2PLL, 0x334, 0x340, 0x1, 0,
63 31, 0x334, 1, 0x338, 0),
64 PLL(CLK_APMIXED_TRGPLL, 0x344, 0x354, 0x1, 0,
65 21, 0x344, 1, 0x348, 0),
66 PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
67 21, 0x358, 1, 0x35c, 0),
71 #define FACTOR0(_id, _parent, _mult, _div) \
72 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
74 #define FACTOR1(_id, _parent, _mult, _div) \
75 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
77 #define FACTOR2(_id, _parent, _mult, _div) \
78 FACTOR(_id, _parent, _mult, _div, 0)
80 static const struct mtk_fixed_clk top_fixed_clks[] = {
81 FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000),
82 FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000),
83 FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000),
84 FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000),
85 FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000),
86 FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000),
87 FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333),
88 FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000),
89 FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000),
90 FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000),
93 static const struct mtk_fixed_factor top_fixed_divs[] = {
94 FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4),
95 FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
96 FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125),
97 FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
98 FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1),
99 FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024),
100 FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1),
101 FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
102 FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
103 FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
104 FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
105 FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
106 FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
107 FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
108 FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
109 FACTOR0(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10),
110 FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20),
111 FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
112 FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28),
113 FACTOR0(CLK_TOP_SYSPLL4_D16, CLK_APMIXED_MAINPLL, 1, 112),
114 FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2),
115 FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2),
116 FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
117 FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
118 FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
119 FACTOR1(CLK_TOP_UNIVPLL1_D16, CLK_TOP_UNIVPLL, 1, 32),
120 FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
121 FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
122 FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
123 FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL, 1, 48),
124 FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
125 FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10),
126 FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20),
127 FACTOR1(CLK_TOP_UNIVPLL3_D16, CLK_TOP_UNIVPLL, 1, 80),
128 FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7),
129 FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320),
130 FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25),
131 FACTOR0(CLK_TOP_SGMIIPLL, CLK_APMIXED_SGMIPLL, 1, 1),
132 FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2),
133 FACTOR0(CLK_TOP_AUD1PLL, CLK_APMIXED_AUD1PLL, 1, 1),
134 FACTOR0(CLK_TOP_AUD2PLL, CLK_APMIXED_AUD2PLL, 1, 1),
135 FACTOR1(CLK_TOP_AUD_I2S2_MCK, CLK_TOP_I2S2_MCK_SEL, 1, 2),
136 FACTOR1(CLK_TOP_TO_USB3_REF, CLK_TOP_UNIVPLL2_D4, 1, 4),
137 FACTOR1(CLK_TOP_PCIE1_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
138 FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
139 FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1),
142 static const int axi_parents[] = {
152 static const int mem_parents[] = {
157 static const int ddrphycfg_parents[] = {
162 static const int eth_parents[] = {
172 static const int pwm_parents[] = {
177 static const int f10m_ref_parents[] = {
182 static const int nfi_infra_parents[] = {
200 static const int flash_parents[] = {
202 CLK_TOP_UNIVPLL_D80_D4,
211 static const int uart_parents[] = {
216 static const int spi0_parents[] = {
227 static const int spi1_parents[] = {
238 static const int msdc30_0_parents[] = {
240 CLK_TOP_UNIVPLL2_D16,
244 static const int a1sys_hp_parents[] = {
251 static const int intdir_parents[] = {
258 static const int aud_intbus_parents[] = {
265 static const int pmicspi_parents[] = {
274 static const int atb_parents[] = {
280 static const int audio_parents[] = {
287 static const int usb20_parents[] = {
294 static const int aud1_parents[] = {
299 static const int asm_l_parents[] = {
306 static const int apll1_ck_parents[] = {
311 static const struct mtk_composite top_muxes[] = {
313 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
314 MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
315 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
316 MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
319 MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
320 MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
321 MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
322 MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
325 MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
326 MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
327 MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23),
328 MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31),
331 MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
332 MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15),
333 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, a1sys_hp_parents, 0x70, 16, 3, 23),
334 MUX_GATE(CLK_TOP_A2SYS_HP_SEL, a1sys_hp_parents, 0x70, 24, 3, 31),
337 MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7),
338 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15),
339 MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23),
340 MUX_GATE(CLK_TOP_SCP_SEL, ddrphycfg_parents, 0x80, 24, 2, 31),
343 MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
344 MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15,
346 MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23),
347 MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),
350 MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
351 MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15),
352 MUX_GATE(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23),
353 MUX_GATE(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31),
356 MUX_GATE(CLK_TOP_ASM_L_SEL, asm_l_parents, 0xB0, 0, 2, 7),
357 MUX_GATE(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15),
358 MUX_GATE(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23),
361 MUX(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1),
362 MUX(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1),
363 MUX(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1),
364 MUX(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1),
365 MUX(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1),
366 MUX(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1),
370 static const struct mtk_gate_regs infra_cg_regs = {
376 #define GATE_INFRA(_id, _parent, _shift) { \
379 .regs = &infra_cg_regs, \
381 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
384 static const struct mtk_gate infra_cgs[] = {
385 GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_AXI_SEL, 0),
386 GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2),
387 GATE_INFRA(CLK_INFRA_AUDIO_PD, CLK_TOP_AUD_INTBUS_SEL, 5),
388 GATE_INFRA(CLK_INFRA_IRRX_PD, CLK_TOP_IRRX_SEL, 16),
389 GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_F10M_REF_SEL, 18),
390 GATE_INFRA(CLK_INFRA_PMIC_PD, CLK_TOP_PMICSPI_SEL, 22),
394 static const struct mtk_gate_regs peri0_cg_regs = {
400 static const struct mtk_gate_regs peri1_cg_regs = {
406 #define GATE_PERI0(_id, _parent, _shift) { \
409 .regs = &peri0_cg_regs, \
411 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
414 #define GATE_PERI1(_id, _parent, _shift) { \
417 .regs = &peri1_cg_regs, \
419 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
422 static const struct mtk_gate peri_cgs[] = {
424 GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1),
425 GATE_PERI0(CLK_PERI_PWM1_PD, CLK_XTAL, 2),
426 GATE_PERI0(CLK_PERI_PWM2_PD, CLK_XTAL, 3),
427 GATE_PERI0(CLK_PERI_PWM3_PD, CLK_XTAL, 4),
428 GATE_PERI0(CLK_PERI_PWM4_PD, CLK_XTAL, 5),
429 GATE_PERI0(CLK_PERI_PWM5_PD, CLK_XTAL, 6),
430 GATE_PERI0(CLK_PERI_PWM6_PD, CLK_XTAL, 7),
431 GATE_PERI0(CLK_PERI_PWM7_PD, CLK_XTAL, 8),
432 GATE_PERI0(CLK_PERI_PWM_PD, CLK_XTAL, 9),
433 GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12),
434 GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13),
435 GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14),
436 GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_AXI_SEL, 17),
437 GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18),
438 GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19),
439 GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20),
440 GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22),
441 GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23),
442 GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24),
443 GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25),
444 GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26),
445 GATE_PERI0(CLK_PERI_AUXADC_PD, CLK_XTAL, 27),
446 GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28),
447 GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29),
448 GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30),
449 GATE_PERI1(CLK_PERI_NFIECC_PD, CLK_TOP_AXI_SEL, 31),
452 GATE_PERI1(CLK_PERI_FLASH_PD, CLK_TOP_FLASH_SEL, 1),
453 GATE_PERI1(CLK_PERI_IRTX_PD, CLK_TOP_IRTX_SEL, 2),
457 static const struct mtk_gate_regs pcie_cg_regs = {
463 #define GATE_PCIE(_id, _parent, _shift) { \
466 .regs = &pcie_cg_regs, \
468 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
471 static const struct mtk_gate pcie_cgs[] = {
472 GATE_PCIE(CLK_PCIE_P1_AUX_EN, CLK_TOP_P1_1MHZ, 12),
473 GATE_PCIE(CLK_PCIE_P1_OBFF_EN, CLK_TOP_4MHZ, 13),
474 GATE_PCIE(CLK_PCIE_P1_AHB_EN, CLK_TOP_AXI_SEL, 14),
475 GATE_PCIE(CLK_PCIE_P1_AXI_EN, CLK_TOP_HIF_SEL, 15),
476 GATE_PCIE(CLK_PCIE_P1_MAC_EN, CLK_TOP_PCIE1_MAC_EN, 16),
477 GATE_PCIE(CLK_PCIE_P1_PIPE_EN, CLK_TOP_PCIE1_PIPE_EN, 17),
478 GATE_PCIE(CLK_PCIE_P0_AUX_EN, CLK_TOP_P0_1MHZ, 18),
479 GATE_PCIE(CLK_PCIE_P0_OBFF_EN, CLK_TOP_4MHZ, 19),
480 GATE_PCIE(CLK_PCIE_P0_AHB_EN, CLK_TOP_AXI_SEL, 20),
481 GATE_PCIE(CLK_PCIE_P0_AXI_EN, CLK_TOP_HIF_SEL, 21),
482 GATE_PCIE(CLK_PCIE_P0_MAC_EN, CLK_TOP_PCIE0_MAC_EN, 22),
483 GATE_PCIE(CLK_PCIE_P0_PIPE_EN, CLK_TOP_PCIE0_PIPE_EN, 23),
484 GATE_PCIE(CLK_SATA_AHB_EN, CLK_TOP_AXI_SEL, 26),
485 GATE_PCIE(CLK_SATA_AXI_EN, CLK_TOP_HIF_SEL, 27),
486 GATE_PCIE(CLK_SATA_ASIC_EN, CLK_TOP_SATA_ASIC, 28),
487 GATE_PCIE(CLK_SATA_RBC_EN, CLK_TOP_SATA_RBC, 29),
488 GATE_PCIE(CLK_SATA_PM_EN, CLK_TOP_UNIVPLL2_D4, 30),
492 static const struct mtk_gate_regs eth_cg_regs = {
496 #define GATE_ETH(_id, _parent, _shift) { \
499 .regs = ð_cg_regs, \
501 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
504 static const struct mtk_gate eth_cgs[] = {
505 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5),
506 GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6),
507 GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7),
508 GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8),
509 GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
512 static const struct mtk_gate_regs sgmii_cg_regs = {
516 #define GATE_SGMII(_id, _parent, _shift) { \
519 .regs = &sgmii_cg_regs, \
521 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
524 static const struct mtk_gate_regs ssusb_cg_regs = {
530 #define GATE_SSUSB(_id, _parent, _shift) { \
533 .regs = &ssusb_cg_regs, \
535 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
538 static const struct mtk_gate sgmii_cgs[] = {
539 GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2),
540 GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
541 GATE_SGMII(CLK_SGMII_CDR_REF, CLK_TOP_SSUSB_CDR_REF, 4),
542 GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
545 static const struct mtk_gate ssusb_cgs[] = {
546 GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0),
547 GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1),
548 GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5),
549 GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6),
550 GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_AXI_SEL, 7),
551 GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8),
554 static const struct mtk_clk_tree mt7622_clk_tree = {
555 .xtal_rate = 25 * MHZ,
556 .xtal2_rate = 25 * MHZ,
557 .fdivs_offs = CLK_TOP_TO_USB3_SYS,
558 .muxes_offs = CLK_TOP_AXI_SEL,
559 .plls = apmixed_plls,
560 .fclks = top_fixed_clks,
561 .fdivs = top_fixed_divs,
565 static int mt7622_mcucfg_probe(struct udevice *dev)
569 base = dev_read_addr_ptr(dev);
573 clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
575 clrsetbits_le32(base + MCU_BUS_MUX, MCU_BUS_MSK,
581 static int mt7622_apmixedsys_probe(struct udevice *dev)
583 struct mtk_clk_priv *priv = dev_get_priv(dev);
586 ret = mtk_common_clk_init(dev, &mt7622_clk_tree);
590 /* reduce clock square disable time */
591 // writel(0x501, priv->base + MT7622_CLKSQ_STB_CON0);
592 writel(0x98940501, priv->base + MT7622_CLKSQ_STB_CON0);
594 /* extend pwr/iso control timing to 1us */
595 writel(0x80008, priv->base + MT7622_PLL_ISO_CON0);
600 static int mt7622_topckgen_probe(struct udevice *dev)
602 return mtk_common_clk_init(dev, &mt7622_clk_tree);
605 static int mt7622_infracfg_probe(struct udevice *dev)
607 return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, infra_cgs);
610 static int mt7622_pericfg_probe(struct udevice *dev)
612 return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs);
615 static int mt7622_pciesys_probe(struct udevice *dev)
617 return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs);
620 static int mt7622_pciesys_bind(struct udevice *dev)
624 if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) {
625 ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
627 debug("Warning: failed to bind reset controller\n");
633 static int mt7622_ethsys_probe(struct udevice *dev)
635 return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs);
638 static int mt7622_ethsys_bind(struct udevice *dev)
642 #if CONFIG_IS_ENABLED(RESET_MEDIATEK)
643 ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
645 debug("Warning: failed to bind reset controller\n");
651 static int mt7622_sgmiisys_probe(struct udevice *dev)
653 return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs);
656 static int mt7622_ssusbsys_probe(struct udevice *dev)
658 return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs);
661 static const struct udevice_id mt7622_apmixed_compat[] = {
662 { .compatible = "mediatek,mt7622-apmixedsys" },
666 static const struct udevice_id mt7622_topckgen_compat[] = {
667 { .compatible = "mediatek,mt7622-topckgen" },
671 static const struct udevice_id mt7622_infracfg_compat[] = {
672 { .compatible = "mediatek,mt7622-infracfg", },
676 static const struct udevice_id mt7622_pericfg_compat[] = {
677 { .compatible = "mediatek,mt7622-pericfg", },
681 static const struct udevice_id mt7622_pciesys_compat[] = {
682 { .compatible = "mediatek,mt7622-pciesys", },
686 static const struct udevice_id mt7622_ethsys_compat[] = {
687 { .compatible = "mediatek,mt7622-ethsys", },
691 static const struct udevice_id mt7622_sgmiisys_compat[] = {
692 { .compatible = "mediatek,mt7622-sgmiisys", },
696 static const struct udevice_id mt7622_mcucfg_compat[] = {
697 { .compatible = "mediatek,mt7622-mcucfg" },
701 static const struct udevice_id mt7622_ssusbsys_compat[] = {
702 { .compatible = "mediatek,mt7622-ssusbsys" },
706 U_BOOT_DRIVER(mtk_mcucfg) = {
707 .name = "mt7622-mcucfg",
709 .of_match = mt7622_mcucfg_compat,
710 .probe = mt7622_mcucfg_probe,
711 .flags = DM_FLAG_PRE_RELOC,
714 U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
715 .name = "mt7622-clock-apmixedsys",
717 .of_match = mt7622_apmixed_compat,
718 .probe = mt7622_apmixedsys_probe,
719 .priv_auto = sizeof(struct mtk_clk_priv),
720 .ops = &mtk_clk_apmixedsys_ops,
721 .flags = DM_FLAG_PRE_RELOC,
724 U_BOOT_DRIVER(mtk_clk_topckgen) = {
725 .name = "mt7622-clock-topckgen",
727 .of_match = mt7622_topckgen_compat,
728 .probe = mt7622_topckgen_probe,
729 .priv_auto = sizeof(struct mtk_clk_priv),
730 .ops = &mtk_clk_topckgen_ops,
731 .flags = DM_FLAG_PRE_RELOC,
734 U_BOOT_DRIVER(mtk_clk_infracfg) = {
735 .name = "mt7622-clock-infracfg",
737 .of_match = mt7622_infracfg_compat,
738 .probe = mt7622_infracfg_probe,
739 .priv_auto = sizeof(struct mtk_cg_priv),
740 .ops = &mtk_clk_gate_ops,
741 .flags = DM_FLAG_PRE_RELOC,
744 U_BOOT_DRIVER(mtk_clk_pericfg) = {
745 .name = "mt7622-clock-pericfg",
747 .of_match = mt7622_pericfg_compat,
748 .probe = mt7622_pericfg_probe,
749 .priv_auto = sizeof(struct mtk_cg_priv),
750 .ops = &mtk_clk_gate_ops,
751 .flags = DM_FLAG_PRE_RELOC,
754 U_BOOT_DRIVER(mtk_clk_pciesys) = {
755 .name = "mt7622-clock-pciesys",
757 .of_match = mt7622_pciesys_compat,
758 .probe = mt7622_pciesys_probe,
759 .bind = mt7622_pciesys_bind,
760 .priv_auto = sizeof(struct mtk_cg_priv),
761 .ops = &mtk_clk_gate_ops,
764 U_BOOT_DRIVER(mtk_clk_ethsys) = {
765 .name = "mt7622-clock-ethsys",
767 .of_match = mt7622_ethsys_compat,
768 .probe = mt7622_ethsys_probe,
769 .bind = mt7622_ethsys_bind,
770 .priv_auto = sizeof(struct mtk_cg_priv),
771 .ops = &mtk_clk_gate_ops,
774 U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
775 .name = "mt7622-clock-sgmiisys",
777 .of_match = mt7622_sgmiisys_compat,
778 .probe = mt7622_sgmiisys_probe,
779 .priv_auto = sizeof(struct mtk_cg_priv),
780 .ops = &mtk_clk_gate_ops,
783 U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
784 .name = "mt7622-clock-ssusbsys",
786 .of_match = mt7622_ssusbsys_compat,
787 .probe = mt7622_ssusbsys_probe,
788 .priv_auto = sizeof(struct mtk_cg_priv),
789 .ops = &mtk_clk_gate_ops,