drivers/clk/mediatek/clk-mt7622.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MediaTek clock driver for MT7622 SoC
   4  *
   5  * Copyright (C) 2019 MediaTek Inc.
   6  * Author: Ryder Lee <ryder.lee@mediatek.com>
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <log.h>
  12 #include <asm/arch-mediatek/reset.h>
  13 #include <asm/io.h>
  14 #include <dt-bindings/clock/mt7622-clk.h>
  15 #include <linux/bitops.h>
  16
  17 #include "clk-mtk.h"
  18
  19 #define MT7622_CLKSQ_STB_CON0           0x20
  20 #define MT7622_PLL_ISO_CON0             0x2c
  21 #define MT7622_PLL_FMAX                 (2500UL * MHZ)
  22 #define MT7622_CON0_RST_BAR             BIT(24)
  23
  24 #define MCU_AXI_DIV                     0x640
  25 #define AXI_DIV_MSK                     GENMASK(4, 0)
  26 #define AXI_DIV_SEL(x)                  (x)
  27
  28 #define MCU_BUS_MUX                     0x7c0
  29 #define MCU_BUS_MSK                     GENMASK(10, 9)
  30 #define MCU_BUS_SEL(x)                  ((x) << 9)
  31
  32 /* apmixedsys */
  33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,   \
  34             _pd_shift, _pcw_reg, _pcw_shift) {                          \
  35                 .id = _id,                                              \
  36                 .reg = _reg,                                            \
  37                 .pwr_reg = _pwr_reg,                                    \
  38                 .en_mask = _en_mask,                                    \
  39                 .rst_bar_mask = MT7622_CON0_RST_BAR,                    \
  40                 .fmax = MT7622_PLL_FMAX,                                \
  41                 .flags = _flags,                                        \
  42                 .pcwbits = _pcwbits,                                    \
  43                 .pd_reg = _pd_reg,                                      \
  44                 .pd_shift = _pd_shift,                                  \
  45                 .pcw_reg = _pcw_reg,                                    \
  46                 .pcw_shift = _pcw_shift,                                \
  47         }
  48
  49 static const struct mtk_pll_data apmixed_plls[] = {
  50         PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
  51             21, 0x204, 24, 0x204, 0),
  52         PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
  53             21, 0x214, 24, 0x214, 0),
  54         PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
  55             7, 0x224, 24, 0x224, 14),
  56         PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
  57             21, 0x300, 1, 0x304, 0),
  58         PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
  59             21, 0x314, 1, 0x318, 0),
  60         PLL(CLK_APMIXED_AUD1PLL, 0x324, 0x330, 0x1, 0,
  61             31, 0x324, 1, 0x328, 0),
  62         PLL(CLK_APMIXED_AUD2PLL, 0x334, 0x340, 0x1, 0,
  63             31, 0x334, 1, 0x338, 0),
  64         PLL(CLK_APMIXED_TRGPLL, 0x344, 0x354, 0x1, 0,
  65             21, 0x344, 1, 0x348, 0),
  66         PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
  67             21, 0x358, 1, 0x35c, 0),
  68 };
  69
  70 /* topckgen */
  71 #define FACTOR0(_id, _parent, _mult, _div)                      \
  72         FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
  73
  74 #define FACTOR1(_id, _parent, _mult, _div)                      \
  75         FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
  76
  77 #define FACTOR2(_id, _parent, _mult, _div)                      \
  78         FACTOR(_id, _parent, _mult, _div, 0)
  79
  80 static const struct mtk_fixed_clk top_fixed_clks[] = {
  81         FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000),
  82         FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000),
  83         FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000),
  84         FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000),
  85         FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000),
  86         FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000),
  87         FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333),
  88         FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000),
  89         FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000),
  90         FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000),
  91 };
  92
  93 static const struct mtk_fixed_factor top_fixed_divs[] = {
  94         FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4),
  95         FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
  96         FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125),
  97         FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
  98         FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1),
  99         FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024),
 100         FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1),
 101         FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
 102         FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
 103         FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
 104         FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
 105         FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
 106         FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
 107         FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
 108         FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
 109         FACTOR0(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10),
 110         FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20),
 111         FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
 112         FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28),
 113         FACTOR0(CLK_TOP_SYSPLL4_D16, CLK_APMIXED_MAINPLL, 1, 112),
 114         FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2),
 115         FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2),
 116         FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
 117         FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
 118         FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
 119         FACTOR1(CLK_TOP_UNIVPLL1_D16, CLK_TOP_UNIVPLL, 1, 32),
 120         FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
 121         FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
 122         FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
 123         FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL, 1, 48),
 124         FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
 125         FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10),
 126         FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20),
 127         FACTOR1(CLK_TOP_UNIVPLL3_D16, CLK_TOP_UNIVPLL, 1, 80),
 128         FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7),
 129         FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320),
 130         FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25),
 131         FACTOR0(CLK_TOP_SGMIIPLL, CLK_APMIXED_SGMIPLL, 1, 1),
 132         FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2),
 133         FACTOR0(CLK_TOP_AUD1PLL, CLK_APMIXED_AUD1PLL, 1, 1),
 134         FACTOR0(CLK_TOP_AUD2PLL, CLK_APMIXED_AUD2PLL, 1, 1),
 135         FACTOR1(CLK_TOP_AUD_I2S2_MCK, CLK_TOP_I2S2_MCK_SEL, 1, 2),
 136         FACTOR1(CLK_TOP_TO_USB3_REF, CLK_TOP_UNIVPLL2_D4, 1, 4),
 137         FACTOR1(CLK_TOP_PCIE1_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
 138         FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
 139         FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1),
 140 };
 141
 142 static const int axi_parents[] = {
 143         CLK_XTAL,
 144         CLK_TOP_SYSPLL1_D2,
 145         CLK_TOP_SYSPLL_D5,
 146         CLK_TOP_SYSPLL1_D4,
 147         CLK_TOP_UNIVPLL_D5,
 148         CLK_TOP_UNIVPLL2_D2,
 149         CLK_TOP_UNIVPLL_D7
 150 };
 151
 152 static const int mem_parents[] = {
 153         CLK_XTAL,
 154         CLK_TOP_DMPLL
 155 };
 156
 157 static const int ddrphycfg_parents[] = {
 158         CLK_XTAL,
 159         CLK_TOP_SYSPLL1_D8
 160 };
 161
 162 static const int eth_parents[] = {
 163         CLK_XTAL,
 164         CLK_TOP_SYSPLL1_D2,
 165         CLK_TOP_UNIVPLL1_D2,
 166         CLK_TOP_SYSPLL1_D4,
 167         CLK_TOP_UNIVPLL_D5,
 168         -1,
 169         CLK_TOP_UNIVPLL_D7
 170 };
 171
 172 static const int pwm_parents[] = {
 173         CLK_XTAL,
 174         CLK_TOP_UNIVPLL2_D4
 175 };
 176
 177 static const int f10m_ref_parents[] = {
 178         CLK_XTAL,
 179         CLK_TOP_SYSPLL4_D16
 180 };
 181
 182 static const int nfi_infra_parents[] = {
 183         CLK_XTAL,
 184         CLK_XTAL,
 185         CLK_XTAL,
 186         CLK_XTAL,
 187         CLK_XTAL,
 188         CLK_XTAL,
 189         CLK_XTAL,
 190         CLK_XTAL,
 191         CLK_TOP_UNIVPLL2_D8,
 192         CLK_TOP_SYSPLL1_D8,
 193         CLK_TOP_UNIVPLL1_D8,
 194         CLK_TOP_SYSPLL4_D2,
 195         CLK_TOP_UNIVPLL2_D4,
 196         CLK_TOP_UNIVPLL3_D2,
 197         CLK_TOP_SYSPLL1_D4
 198 };
 199
 200 static const int flash_parents[] = {
 201         CLK_XTAL,
 202         CLK_TOP_UNIVPLL_D80_D4,
 203         CLK_TOP_SYSPLL2_D8,
 204         CLK_TOP_SYSPLL3_D4,
 205         CLK_TOP_UNIVPLL3_D4,
 206         CLK_TOP_UNIVPLL1_D8,
 207         CLK_TOP_SYSPLL2_D4,
 208         CLK_TOP_UNIVPLL2_D4
 209 };
 210
 211 static const int uart_parents[] = {
 212         CLK_XTAL,
 213         CLK_TOP_UNIVPLL2_D8
 214 };
 215
 216 static const int spi0_parents[] = {
 217         CLK_XTAL,
 218         CLK_TOP_SYSPLL3_D2,
 219         CLK_XTAL,
 220         CLK_TOP_SYSPLL2_D4,
 221         CLK_TOP_SYSPLL4_D2,
 222         CLK_TOP_UNIVPLL2_D4,
 223         CLK_TOP_UNIVPLL1_D8,
 224         CLK_XTAL
 225 };
 226
 227 static const int spi1_parents[] = {
 228         CLK_XTAL,
 229         CLK_TOP_SYSPLL3_D2,
 230         CLK_XTAL,
 231         CLK_TOP_SYSPLL4_D4,
 232         CLK_TOP_SYSPLL4_D2,
 233         CLK_TOP_UNIVPLL2_D4,
 234         CLK_TOP_UNIVPLL1_D8,
 235         CLK_XTAL
 236 };
 237
 238 static const int msdc30_0_parents[] = {
 239         CLK_XTAL,
 240         CLK_TOP_UNIVPLL2_D16,
 241         CLK_TOP_UNIV48M
 242 };
 243
 244 static const int a1sys_hp_parents[] = {
 245         CLK_XTAL,
 246         CLK_TOP_AUD1PLL,
 247         CLK_TOP_AUD2PLL,
 248         CLK_XTAL
 249 };
 250
 251 static const int intdir_parents[] = {
 252         CLK_XTAL,
 253         CLK_TOP_SYSPLL1_D2,
 254         CLK_TOP_UNIVPLL_D2,
 255         CLK_TOP_SGMIIPLL
 256 };
 257
 258 static const int aud_intbus_parents[] = {
 259         CLK_XTAL,
 260         CLK_TOP_SYSPLL1_D4,
 261         CLK_TOP_SYSPLL4_D2,
 262         CLK_TOP_SYSPLL3_D2
 263 };
 264
 265 static const int pmicspi_parents[] = {
 266         CLK_XTAL,
 267         -1,
 268         -1,
 269         -1,
 270         -1,
 271         CLK_TOP_UNIVPLL2_D16
 272 };
 273
 274 static const int atb_parents[] = {
 275         CLK_XTAL,
 276         CLK_TOP_SYSPLL1_D2,
 277         CLK_TOP_SYSPLL_D5
 278 };
 279
 280 static const int audio_parents[] = {
 281         CLK_XTAL,
 282         CLK_TOP_SYSPLL3_D4,
 283         CLK_TOP_SYSPLL4_D4,
 284         CLK_TOP_UNIVPLL1_D16
 285 };
 286
 287 static const int usb20_parents[] = {
 288         CLK_XTAL,
 289         CLK_TOP_UNIVPLL3_D4,
 290         CLK_TOP_SYSPLL1_D8,
 291         CLK_XTAL
 292 };
 293
 294 static const int aud1_parents[] = {
 295         CLK_XTAL,
 296         CLK_TOP_AUD1PLL
 297 };
 298
 299 static const int asm_l_parents[] = {
 300         CLK_XTAL,
 301         CLK_TOP_SYSPLL_D5,
 302         CLK_TOP_UNIVPLL2_D2,
 303         CLK_TOP_UNIVPLL2_D4
 304 };
 305
 306 static const int apll1_ck_parents[] = {
 307         CLK_TOP_AUD1_SEL,
 308         CLK_TOP_AUD2_SEL
 309 };
 310
 311 static const struct mtk_composite top_muxes[] = {
 312         /* CLK_CFG_0 */
 313         MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
 314         MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
 315         MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
 316         MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
 317
 318         /* CLK_CFG_1 */
 319         MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
 320         MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
 321         MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
 322         MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
 323
 324         /* CLK_CFG_2 */
 325         MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
 326         MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
 327         MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23),
 328         MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31),
 329
 330         /* CLK_CFG_3 */
 331         MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
 332         MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15),
 333         MUX_GATE(CLK_TOP_A1SYS_HP_SEL, a1sys_hp_parents, 0x70, 16, 3, 23),
 334         MUX_GATE(CLK_TOP_A2SYS_HP_SEL, a1sys_hp_parents, 0x70, 24, 3, 31),
 335
 336         /* CLK_CFG_4 */
 337         MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7),
 338         MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15),
 339         MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23),
 340         MUX_GATE(CLK_TOP_SCP_SEL, ddrphycfg_parents, 0x80, 24, 2, 31),
 341
 342         /* CLK_CFG_5 */
 343         MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
 344         MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15,
 345                        CLK_DOMAIN_SCPSYS),
 346         MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23),
 347         MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),
 348
 349         /* CLK_CFG_6 */
 350         MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
 351         MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15),
 352         MUX_GATE(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23),
 353         MUX_GATE(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31),
 354
 355         /* CLK_CFG_7 */
 356         MUX_GATE(CLK_TOP_ASM_L_SEL, asm_l_parents, 0xB0, 0, 2, 7),
 357         MUX_GATE(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15),
 358         MUX_GATE(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23),
 359
 360         /* CLK_AUDDIV_0 */
 361         MUX(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1),
 362         MUX(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1),
 363         MUX(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1),
 364         MUX(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1),
 365         MUX(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1),
 366         MUX(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1),
 367 };
 368
 369 /* infracfg */
 370 static const struct mtk_gate_regs infra_cg_regs = {
 371         .set_ofs = 0x40,
 372         .clr_ofs = 0x44,
 373         .sta_ofs = 0x48,
 374 };
 375
 376 #define GATE_INFRA(_id, _parent, _shift) {                      \
 377                 .id = _id,                                      \
 378                 .parent = _parent,                              \
 379                 .regs = &infra_cg_regs,                         \
 380                 .shift = _shift,                                \
 381                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
 382         }
 383
 384 static const struct mtk_gate infra_cgs[] = {
 385         GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_AXI_SEL, 0),
 386         GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2),
 387         GATE_INFRA(CLK_INFRA_AUDIO_PD, CLK_TOP_AUD_INTBUS_SEL, 5),
 388         GATE_INFRA(CLK_INFRA_IRRX_PD, CLK_TOP_IRRX_SEL, 16),
 389         GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_F10M_REF_SEL, 18),
 390         GATE_INFRA(CLK_INFRA_PMIC_PD, CLK_TOP_PMICSPI_SEL, 22),
 391 };
 392
 393 /* pericfg */
 394 static const struct mtk_gate_regs peri0_cg_regs = {
 395         .set_ofs = 0x8,
 396         .clr_ofs = 0x10,
 397         .sta_ofs = 0x18,
 398 };
 399
 400 static const struct mtk_gate_regs peri1_cg_regs = {
 401         .set_ofs = 0xC,
 402         .clr_ofs = 0x14,
 403         .sta_ofs = 0x1C,
 404 };
 405
 406 #define GATE_PERI0(_id, _parent, _shift) {                      \
 407                 .id = _id,                                      \
 408                 .parent = _parent,                              \
 409                 .regs = &peri0_cg_regs,                         \
 410                 .shift = _shift,                                \
 411                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
 412         }
 413
 414 #define GATE_PERI1(_id, _parent, _shift) {                      \
 415                 .id = _id,                                      \
 416                 .parent = _parent,                              \
 417                 .regs = &peri1_cg_regs,                         \
 418                 .shift = _shift,                                \
 419                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
 420         }
 421
 422 static const struct mtk_gate peri_cgs[] = {
 423         /* PERI0 */
 424         GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1),
 425         GATE_PERI0(CLK_PERI_PWM1_PD, CLK_XTAL, 2),
 426         GATE_PERI0(CLK_PERI_PWM2_PD, CLK_XTAL, 3),
 427         GATE_PERI0(CLK_PERI_PWM3_PD, CLK_XTAL, 4),
 428         GATE_PERI0(CLK_PERI_PWM4_PD, CLK_XTAL, 5),
 429         GATE_PERI0(CLK_PERI_PWM5_PD, CLK_XTAL, 6),
 430         GATE_PERI0(CLK_PERI_PWM6_PD, CLK_XTAL, 7),
 431         GATE_PERI0(CLK_PERI_PWM7_PD, CLK_XTAL, 8),
 432         GATE_PERI0(CLK_PERI_PWM_PD, CLK_XTAL, 9),
 433         GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12),
 434         GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13),
 435         GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14),
 436         GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_AXI_SEL, 17),
 437         GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18),
 438         GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19),
 439         GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20),
 440         GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22),
 441         GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23),
 442         GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24),
 443         GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25),
 444         GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26),
 445         GATE_PERI0(CLK_PERI_AUXADC_PD, CLK_XTAL, 27),
 446         GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28),
 447         GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29),
 448         GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30),
 449         GATE_PERI1(CLK_PERI_NFIECC_PD, CLK_TOP_AXI_SEL, 31),
 450
 451         /* PERI1 */
 452         GATE_PERI1(CLK_PERI_FLASH_PD, CLK_TOP_FLASH_SEL, 1),
 453         GATE_PERI1(CLK_PERI_IRTX_PD, CLK_TOP_IRTX_SEL, 2),
 454 };
 455
 456 /* pciesys */
 457 static const struct mtk_gate_regs pcie_cg_regs = {
 458         .set_ofs = 0x30,
 459         .clr_ofs = 0x30,
 460         .sta_ofs = 0x30,
 461 };
 462
 463 #define GATE_PCIE(_id, _parent, _shift) {               \
 464                 .id = _id,                              \
 465                 .parent = _parent,                      \
 466                 .regs = &pcie_cg_regs,                  \
 467                 .shift = _shift,                        \
 468                 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,  \
 469         }
 470
 471 static const struct mtk_gate pcie_cgs[] = {
 472         GATE_PCIE(CLK_PCIE_P1_AUX_EN, CLK_TOP_P1_1MHZ, 12),
 473         GATE_PCIE(CLK_PCIE_P1_OBFF_EN, CLK_TOP_4MHZ, 13),
 474         GATE_PCIE(CLK_PCIE_P1_AHB_EN, CLK_TOP_AXI_SEL, 14),
 475         GATE_PCIE(CLK_PCIE_P1_AXI_EN, CLK_TOP_HIF_SEL, 15),
 476         GATE_PCIE(CLK_PCIE_P1_MAC_EN, CLK_TOP_PCIE1_MAC_EN, 16),
 477         GATE_PCIE(CLK_PCIE_P1_PIPE_EN, CLK_TOP_PCIE1_PIPE_EN, 17),
 478         GATE_PCIE(CLK_PCIE_P0_AUX_EN, CLK_TOP_P0_1MHZ, 18),
 479         GATE_PCIE(CLK_PCIE_P0_OBFF_EN, CLK_TOP_4MHZ, 19),
 480         GATE_PCIE(CLK_PCIE_P0_AHB_EN, CLK_TOP_AXI_SEL, 20),
 481         GATE_PCIE(CLK_PCIE_P0_AXI_EN, CLK_TOP_HIF_SEL, 21),
 482         GATE_PCIE(CLK_PCIE_P0_MAC_EN, CLK_TOP_PCIE0_MAC_EN, 22),
 483         GATE_PCIE(CLK_PCIE_P0_PIPE_EN, CLK_TOP_PCIE0_PIPE_EN, 23),
 484         GATE_PCIE(CLK_SATA_AHB_EN, CLK_TOP_AXI_SEL, 26),
 485         GATE_PCIE(CLK_SATA_AXI_EN, CLK_TOP_HIF_SEL, 27),
 486         GATE_PCIE(CLK_SATA_ASIC_EN, CLK_TOP_SATA_ASIC, 28),
 487         GATE_PCIE(CLK_SATA_RBC_EN, CLK_TOP_SATA_RBC, 29),
 488         GATE_PCIE(CLK_SATA_PM_EN, CLK_TOP_UNIVPLL2_D4, 30),
 489 };
 490
 491 /* ethsys */
 492 static const struct mtk_gate_regs eth_cg_regs = {
 493         .sta_ofs = 0x30,
 494 };
 495
 496 #define GATE_ETH(_id, _parent, _shift) {                        \
 497                 .id = _id,                                      \
 498                 .parent = _parent,                              \
 499                 .regs = &eth_cg_regs,                           \
 500                 .shift = _shift,                                \
 501                 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,  \
 502         }
 503
 504 static const struct mtk_gate eth_cgs[] = {
 505         GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5),
 506         GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6),
 507         GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7),
 508         GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8),
 509         GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
 510 };
 511
 512 static const struct mtk_gate_regs sgmii_cg_regs = {
 513         .sta_ofs = 0xE4,
 514 };
 515
 516 #define GATE_SGMII(_id, _parent, _shift) {                      \
 517         .id = _id,                                              \
 518         .parent = _parent,                                      \
 519         .regs = &sgmii_cg_regs,                                 \
 520         .shift = _shift,                                        \
 521         .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,  \
 522 }
 523
 524 static const struct mtk_gate_regs ssusb_cg_regs = {
 525         .set_ofs = 0x30,
 526         .clr_ofs = 0x30,
 527         .sta_ofs = 0x30,
 528 };
 529
 530 #define GATE_SSUSB(_id, _parent, _shift) {                      \
 531         .id = _id,                                              \
 532         .parent = _parent,                                      \
 533         .regs = &ssusb_cg_regs,                                 \
 534         .shift = _shift,                                        \
 535         .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,  \
 536 }
 537
 538 static const struct mtk_gate sgmii_cgs[] = {
 539         GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2),
 540         GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
 541         GATE_SGMII(CLK_SGMII_CDR_REF, CLK_TOP_SSUSB_CDR_REF, 4),
 542         GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
 543 };
 544
 545 static const struct mtk_gate ssusb_cgs[] = {
 546         GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0),
 547         GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1),
 548         GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5),
 549         GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6),
 550         GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_AXI_SEL, 7),
 551         GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8),
 552 };
 553
 554 static const struct mtk_clk_tree mt7622_clk_tree = {
 555         .xtal_rate = 25 * MHZ,
 556         .xtal2_rate = 25 * MHZ,
 557         .fdivs_offs = CLK_TOP_TO_USB3_SYS,
 558         .muxes_offs = CLK_TOP_AXI_SEL,
 559         .plls = apmixed_plls,
 560         .fclks = top_fixed_clks,
 561         .fdivs = top_fixed_divs,
 562         .muxes = top_muxes,
 563 };
 564
 565 static int mt7622_mcucfg_probe(struct udevice *dev)
 566 {
 567         void __iomem *base;
 568
 569         base = dev_read_addr_ptr(dev);
 570         if (!base)
 571                 return -ENOENT;
 572
 573         clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
 574                         AXI_DIV_SEL(0x12));
 575         clrsetbits_le32(base + MCU_BUS_MUX, MCU_BUS_MSK,
 576                         MCU_BUS_SEL(0x1));
 577
 578         return 0;
 579 }
 580
 581 static int mt7622_apmixedsys_probe(struct udevice *dev)
 582 {
 583         struct mtk_clk_priv *priv = dev_get_priv(dev);
 584         int ret;
 585
 586         ret = mtk_common_clk_init(dev, &mt7622_clk_tree);
 587         if (ret)
 588                 return ret;
 589
 590         /* reduce clock square disable time */
 591         // writel(0x501, priv->base + MT7622_CLKSQ_STB_CON0);
 592         writel(0x98940501, priv->base + MT7622_CLKSQ_STB_CON0);
 593
 594         /* extend pwr/iso control timing to 1us */
 595         writel(0x80008, priv->base + MT7622_PLL_ISO_CON0);
 596
 597         return 0;
 598 }
 599
 600 static int mt7622_topckgen_probe(struct udevice *dev)
 601 {
 602         return mtk_common_clk_init(dev, &mt7622_clk_tree);
 603 }
 604
 605 static int mt7622_infracfg_probe(struct udevice *dev)
 606 {
 607         return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, infra_cgs);
 608 }
 609
 610 static int mt7622_pericfg_probe(struct udevice *dev)
 611 {
 612         return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs);
 613 }
 614
 615 static int mt7622_pciesys_probe(struct udevice *dev)
 616 {
 617         return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs);
 618 }
 619
 620 static int mt7622_pciesys_bind(struct udevice *dev)
 621 {
 622         int ret = 0;
 623
 624         if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) {
 625         ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
 626         if (ret)
 627                 debug("Warning: failed to bind reset controller\n");
 628         }
 629
 630         return ret;
 631 }
 632
 633 static int mt7622_ethsys_probe(struct udevice *dev)
 634 {
 635         return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs);
 636 }
 637
 638 static int mt7622_ethsys_bind(struct udevice *dev)
 639 {
 640         int ret = 0;
 641
 642 #if CONFIG_IS_ENABLED(RESET_MEDIATEK)
 643         ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
 644         if (ret)
 645                 debug("Warning: failed to bind reset controller\n");
 646 #endif
 647
 648         return ret;
 649 }
 650
 651 static int mt7622_sgmiisys_probe(struct udevice *dev)
 652 {
 653         return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs);
 654 }
 655
 656 static int mt7622_ssusbsys_probe(struct udevice *dev)
 657 {
 658         return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs);
 659 }
 660
 661 static const struct udevice_id mt7622_apmixed_compat[] = {
 662         { .compatible = "mediatek,mt7622-apmixedsys" },
 663         { }
 664 };
 665
 666 static const struct udevice_id mt7622_topckgen_compat[] = {
 667         { .compatible = "mediatek,mt7622-topckgen" },
 668         { }
 669 };
 670
 671 static const struct udevice_id mt7622_infracfg_compat[] = {
 672         { .compatible = "mediatek,mt7622-infracfg", },
 673         { }
 674 };
 675
 676 static const struct udevice_id mt7622_pericfg_compat[] = {
 677         { .compatible = "mediatek,mt7622-pericfg", },
 678         { }
 679 };
 680
 681 static const struct udevice_id mt7622_pciesys_compat[] = {
 682         { .compatible = "mediatek,mt7622-pciesys", },
 683         { }
 684 };
 685
 686 static const struct udevice_id mt7622_ethsys_compat[] = {
 687         { .compatible = "mediatek,mt7622-ethsys", },
 688         { }
 689 };
 690
 691 static const struct udevice_id mt7622_sgmiisys_compat[] = {
 692         { .compatible = "mediatek,mt7622-sgmiisys", },
 693         { }
 694 };
 695
 696 static const struct udevice_id mt7622_mcucfg_compat[] = {
 697         { .compatible = "mediatek,mt7622-mcucfg" },
 698         { }
 699 };
 700
 701 static const struct udevice_id mt7622_ssusbsys_compat[] = {
 702         { .compatible = "mediatek,mt7622-ssusbsys" },
 703         { }
 704 };
 705
 706 U_BOOT_DRIVER(mtk_mcucfg) = {
 707         .name = "mt7622-mcucfg",
 708         .id = UCLASS_SYSCON,
 709         .of_match = mt7622_mcucfg_compat,
 710         .probe = mt7622_mcucfg_probe,
 711         .flags = DM_FLAG_PRE_RELOC,
 712 };
 713
 714 U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
 715         .name = "mt7622-clock-apmixedsys",
 716         .id = UCLASS_CLK,
 717         .of_match = mt7622_apmixed_compat,
 718         .probe = mt7622_apmixedsys_probe,
 719         .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
 720         .ops = &mtk_clk_apmixedsys_ops,
 721         .flags = DM_FLAG_PRE_RELOC,
 722 };
 723
 724 U_BOOT_DRIVER(mtk_clk_topckgen) = {
 725         .name = "mt7622-clock-topckgen",
 726         .id = UCLASS_CLK,
 727         .of_match = mt7622_topckgen_compat,
 728         .probe = mt7622_topckgen_probe,
 729         .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
 730         .ops = &mtk_clk_topckgen_ops,
 731         .flags = DM_FLAG_PRE_RELOC,
 732 };
 733
 734 U_BOOT_DRIVER(mtk_clk_infracfg) = {
 735         .name = "mt7622-clock-infracfg",
 736         .id = UCLASS_CLK,
 737         .of_match = mt7622_infracfg_compat,
 738         .probe = mt7622_infracfg_probe,
 739         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 740         .ops = &mtk_clk_gate_ops,
 741         .flags = DM_FLAG_PRE_RELOC,
 742 };
 743
 744 U_BOOT_DRIVER(mtk_clk_pericfg) = {
 745         .name = "mt7622-clock-pericfg",
 746         .id = UCLASS_CLK,
 747         .of_match = mt7622_pericfg_compat,
 748         .probe = mt7622_pericfg_probe,
 749         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 750         .ops = &mtk_clk_gate_ops,
 751         .flags = DM_FLAG_PRE_RELOC,
 752 };
 753
 754 U_BOOT_DRIVER(mtk_clk_pciesys) = {
 755         .name = "mt7622-clock-pciesys",
 756         .id = UCLASS_CLK,
 757         .of_match = mt7622_pciesys_compat,
 758         .probe = mt7622_pciesys_probe,
 759         .bind = mt7622_pciesys_bind,
 760         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 761         .ops = &mtk_clk_gate_ops,
 762 };
 763
 764 U_BOOT_DRIVER(mtk_clk_ethsys) = {
 765         .name = "mt7622-clock-ethsys",
 766         .id = UCLASS_CLK,
 767         .of_match = mt7622_ethsys_compat,
 768         .probe = mt7622_ethsys_probe,
 769         .bind = mt7622_ethsys_bind,
 770         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 771         .ops = &mtk_clk_gate_ops,
 772 };
 773
 774 U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
 775         .name = "mt7622-clock-sgmiisys",
 776         .id = UCLASS_CLK,
 777         .of_match = mt7622_sgmiisys_compat,
 778         .probe = mt7622_sgmiisys_probe,
 779         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 780         .ops = &mtk_clk_gate_ops,
 781 };
 782
 783 U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
 784         .name = "mt7622-clock-ssusbsys",
 785         .id = UCLASS_CLK,
 786         .of_match = mt7622_ssusbsys_compat,
 787         .probe = mt7622_ssusbsys_probe,
 788         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 789         .ops = &mtk_clk_gate_ops,
 790 };