drivers/clk/mediatek/clk-mt6765-mm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018 MediaTek Inc.
   4  * Author: Owen Chen <owen.chen@mediatek.com>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/platform_device.h>
   9
  10 #include "clk-mtk.h"
  11 #include "clk-gate.h"
  12
  13 #include <dt-bindings/clock/mt6765-clk.h>
  14
  15 static const struct mtk_gate_regs mm_cg_regs = {
  16         .set_ofs = 0x104,
  17         .clr_ofs = 0x108,
  18         .sta_ofs = 0x100,
  19 };
  20
  21 #define GATE_MM(_id, _name, _parent, _shift) {          \
  22                 .id = _id,                              \
  23                 .name = _name,                          \
  24                 .parent_name = _parent,                 \
  25                 .regs = &mm_cg_regs,                    \
  26                 .shift = _shift,                        \
  27                 .ops = &mtk_clk_gate_ops_setclr,        \
  28         }
  29
  30 static const struct mtk_gate mm_clks[] = {
  31         /* MM */
  32         GATE_MM(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_ck", 0),
  33         GATE_MM(CLK_MM_MDP_CCORR0, "mm_mdp_ccorr0", "mm_ck", 1),
  34         GATE_MM(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_ck", 2),
  35         GATE_MM(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_ck", 3),
  36         GATE_MM(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_ck", 4),
  37         GATE_MM(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_ck", 5),
  38         GATE_MM(CLK_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_ck", 6),
  39         GATE_MM(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_ck", 7),
  40         GATE_MM(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_ck", 8),
  41         GATE_MM(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "mm_ck", 9),
  42         GATE_MM(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_ck", 10),
  43         GATE_MM(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_ck", 11),
  44         GATE_MM(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_ck", 12),
  45         GATE_MM(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_ck", 13),
  46         GATE_MM(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_ck", 14),
  47         GATE_MM(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_ck", 15),
  48         GATE_MM(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_ck", 16),
  49         GATE_MM(CLK_MM_DSI0, "mm_dsi0", "mm_ck", 17),
  50         GATE_MM(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_ck", 18),
  51         GATE_MM(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_ck", 19),
  52         GATE_MM(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_ck", 20),
  53         GATE_MM(CLK_MM_SMI_COMM0, "mm_smi_comm0", "mm_ck", 21),
  54         GATE_MM(CLK_MM_SMI_COMM1, "mm_smi_comm1", "mm_ck", 22),
  55         GATE_MM(CLK_MM_CAM_MDP, "mm_cam_mdp_ck", "mm_ck", 23),
  56         GATE_MM(CLK_MM_SMI_IMG, "mm_smi_img_ck", "mm_ck", 24),
  57         GATE_MM(CLK_MM_SMI_CAM, "mm_smi_cam_ck", "mm_ck", 25),
  58         GATE_MM(CLK_MM_IMG_DL_RELAY, "mm_img_dl_relay", "mm_ck", 26),
  59         GATE_MM(CLK_MM_IMG_DL_ASYNC_TOP, "mm_imgdl_async", "mm_ck", 27),
  60         GATE_MM(CLK_MM_DIG_DSI, "mm_dig_dsi_ck", "mm_ck", 28),
  61         GATE_MM(CLK_MM_F26M_HRTWT, "mm_hrtwt", "f_f26m_ck", 29),
  62 };
  63
  64 static const struct mtk_clk_desc mm_desc = {
  65         .clks = mm_clks,
  66         .num_clks = ARRAY_SIZE(mm_clks),
  67 };
  68
  69 static const struct of_device_id of_match_clk_mt6765_mm[] = {
  70         {
  71                 .compatible = "mediatek,mt6765-mmsys",
  72                 .data = &mm_desc,
  73         }, {
  74                 /* sentinel */
  75         }
  76 };
  77
  78 static struct platform_driver clk_mt6765_mm_drv = {
  79         .probe = mtk_clk_simple_probe,
  80         .remove = mtk_clk_simple_remove,
  81         .driver = {
  82                 .name = "clk-mt6765-mm",
  83                 .of_match_table = of_match_clk_mt6765_mm,
  84         },
  85 };
  86
  87 builtin_platform_driver(clk_mt6765_mm_drv);