1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
5 #define LOG_CATEGORY UCLASS_CLK
9 /* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */
14 #include <dt-bindings/clock/k210-sysctl.h>
15 #include <dt-bindings/mfd/k210-sysctl.h>
16 #include <kendryte/pll.h>
17 #include <linux/bitfield.h>
18 #include <linux/clk-provider.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
23 * struct k210_pll_params - K210 PLL parameters
24 * @off: The offset of the PLL from the base sysctl address
25 * @shift: The offset of the LSB of the lock status
26 * @width: The number of bits in the lock status
28 struct k210_pll_params {
34 static const struct k210_pll_params k210_plls[] = {
35 #define PLL(_off, _shift, _width) { \
40 [0] = PLL(K210_SYSCTL_PLL0, 0, 2),
41 [1] = PLL(K210_SYSCTL_PLL1, 8, 1),
42 [2] = PLL(K210_SYSCTL_PLL2, 16, 1),
46 #ifdef CONFIG_CLK_K210_SET_RATE
47 int k210_pll_enable(struct k210_clk_priv *priv, int id);
48 int k210_pll_disable(struct k210_clk_priv *priv, int id);
49 ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id, ulong rate_in);
52 * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc.
53 * General-Purpose PLL. The logical layout of the PLL with internal feedback is
54 * approximately the following:
72 * |phase detector|<---+
76 * +---+ |feedback clock|
77 * |VCO| +--------------+
92 * The k210 PLLs have three factors: r, f, and od. Because of the feedback mode,
93 * the effect of the division by f is to multiply the input frequency. The
94 * equation for the output rate is
95 * rate = (rate_in * f) / (r * od).
96 * Moving knowns to one side of the equation, we get
97 * rate / rate_in = f / (r * od)
98 * Rearranging slightly,
99 * abs_error = abs((rate / rate_in) - (f / (r * od))).
100 * To get relative, error, we divide by the expected ratio
101 * error = abs((rate / rate_in) - (f / (r * od))) / (rate / rate_in).
103 * error = abs(1 - f / (r * od)) / (rate / rate_in)
104 * error = abs(1 - (f * rate_in) / (r * od * rate))
105 * Using the constants ratio = rate / rate_in and inv_ratio = rate_in / rate,
106 * error = abs((f * inv_ratio) / (r * od) - 1)
107 * This is the error used in evaluating parameters.
109 * r and od are four bits each, while f is six bits. Because r and od are
110 * multiplied together, instead of the full 256 values possible if both bits
111 * were used fully, there are only 97 distinct products. Combined with f, there
112 * are 6208 theoretical settings for the PLL. However, most of these settings
113 * can be ruled out immediately because they do not have the correct ratio.
115 * In addition to the constraint of approximating the desired ratio, parameters
116 * must also keep internal pll frequencies within acceptable ranges. The divided
117 * clock's minimum and maximum frequencies have a ratio of around 128. This
118 * leaves fairly substantial room to work with, especially since the only
119 * affected parameter is r. The VCO's minimum and maximum frequency have a ratio
120 * of 5, which is considerably more restrictive.
122 * The r and od factors are stored in a table. This is to make it easy to find
123 * the next-largest product. Some products have multiple factorizations, but
124 * only when one factor has at least a 2.5x ratio to the factors of the other
125 * factorization. This is because any smaller ratio would not make a difference
126 * when ensuring the VCO's frequency is within spec.
128 * Throughout the calculation function, fixed point arithmetic is used. Because
129 * the range of rate and rate_in may be up to 1.75 GHz, or around 2^30, 64-bit
130 * 32.32 fixed-point numbers are used to represent ratios. In general, to
131 * implement division, the numerator is first multiplied by 2^32. This gives a
132 * result where the whole number part is in the upper 32 bits, and the fraction
133 * is in the lower 32 bits.
135 * In general, rounding is done to the closest integer. This helps find the best
136 * approximation for the ratio. Rounding in one direction (e.g down) could cause
137 * the function to miss a better ratio with one of the parameters increased by
142 * The factors table was generated with the following python code:
145 * return (1.0*x/y > 2.5) or (1.0*y/x > 2.5)
148 * for i in range(1, 17):
149 * for j in range(1, 17):
150 * fs = factors.get(i*j) or []
151 * if fs == [] or all([
152 * (p(i, x) and p(i, y)) or (p(j, x) and p(j, y))
153 * for (x, y) in fs]):
157 * for k, l in sorted(factors.items()):
159 * print("PACK(%s, %s)," % v)
161 #define PACK(r, od) (((((r) - 1) & 0xF) << 4) | (((od) - 1) & 0xF))
162 #define UNPACK_R(val) ((((val) >> 4) & 0xF) + 1)
163 #define UNPACK_OD(val) (((val) & 0xF) + 1)
164 static const u8 factors[] = {
268 TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in,
269 struct k210_pll_config *best)
272 s64 error, best_error;
273 u64 ratio, inv_ratio; /* fixed point 32.32 ratio of the rates */
278 * Can't go over 1.75 GHz or under 21.25 MHz due to limitations on the
279 * VCO frequency. These are not the same limits as below because od can
280 * reduce the output frequency by 16.
282 if (rate > 1750000000 || rate < 21250000)
285 /* Similar restrictions on the input rate */
286 if (rate_in > 1750000000 || rate_in < 13300000)
289 ratio = DIV_ROUND_CLOSEST_ULL((u64)rate << 32, rate_in);
290 inv_ratio = DIV_ROUND_CLOSEST_ULL((u64)rate_in << 32, rate);
291 /* Can't increase by more than 64 or reduce by more than 256 */
292 if (rate > rate_in && ratio > (64ULL << 32))
294 else if (rate <= rate_in && inv_ratio > (256ULL << 32))
298 * The divided clock (rate_in / r) must stay between 1.75 GHz and 13.3
299 * MHz. There is no minimum, since the only way to get a higher input
300 * clock than 26 MHz is to use a clock generated by a PLL. Because PLLs
301 * cannot output frequencies greater than 1.75 GHz, the minimum would
302 * never be greater than one.
304 max_r = DIV_ROUND_DOWN_ULL(rate_in, 13300000);
306 /* Variables get immediately incremented, so start at -1th iteration */
311 best_error = S64_MAX;
313 /* do-while here so we always try at least one ratio */
316 * Whether we swapped r and od while enforcing frequency limits
318 bool swapped = false;
323 * Try the next largest value for f (or r and od) and
324 * recalculate the other parameters based on that
326 if (rate > rate_in) {
328 * Skip factors of the same product if we already tried
333 r = UNPACK_R(factors[i]);
334 od = UNPACK_OD(factors[i]);
335 } while (i + 1 < ARRAY_SIZE(factors) &&
336 r * od == last_r * last_od);
339 f = (r * od * ratio + BIT(31)) >> 32;
343 u64 tmp = ++f * inv_ratio;
344 bool round_up = !!(tmp & BIT(31));
345 u32 goal = (tmp >> 32) + round_up;
348 /* Get the next r/od pair in factors */
349 while (r * od < goal && i + 1 < ARRAY_SIZE(factors)) {
351 r = UNPACK_R(factors[i]);
352 od = UNPACK_OD(factors[i]);
356 * This is a case of double rounding. If we rounded up
357 * above, we need to round down (in cases of ties) here.
358 * This prevents off-by-one errors resulting from
359 * choosing X+2 over X when X.Y rounds up to X+1 and
360 * there is no r * od = X+1. For the converse, when X.Y
361 * is rounded down to X, we should choose X+1 over X-1.
363 err = abs(r * od - goal);
364 last_err = abs(last_r * last_od - goal);
365 if (last_err < err || (round_up && last_err == err)) {
373 * Enforce limits on internal clock frequencies. If we
374 * aren't in spec, try swapping r and od. If everything is
375 * in-spec, calculate the relative error.
379 * Whether the intermediate frequencies are out-of-spec
381 bool out_of_spec = false;
387 * There is no way to only divide once; we need
388 * to examine the frequency with and without the
391 u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r);
393 if (vco > 1750000000 || vco < 340000000)
407 * Try looking ahead to see if there are
408 * additional factors for the same
411 if (i + 1 < ARRAY_SIZE(factors)) {
415 new_r = UNPACK_R(factors[i]);
416 new_od = UNPACK_OD(factors[i]);
417 if (r * od == new_r * new_od) {
429 error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od);
430 /* The lower 16 bits are spurious */
431 error = abs((error - BIT(32))) >> 16;
433 if (error < best_error) {
441 } while (f < 64 && i + 1 < ARRAY_SIZE(factors) && error != 0);
443 if (best_error == S64_MAX)
446 log_debug("best error %lld\n", best_error);
450 static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate,
454 const struct k210_pll_params *pll = &k210_plls[id];
455 struct k210_pll_config config = {};
461 log_debug("Calculating parameters with rate=%lu and rate_in=%lld\n",
463 err = k210_pll_calc_config(rate, rate_in, &config);
466 log_debug("Got r=%u f=%u od=%u\n", config.r, config.f, config.od);
469 * Don't use clk_disable as it might not actually disable the pll due to
472 k210_pll_disable(clk);
474 reg = readl(priv->base + pll->off);
475 reg &= ~K210_PLL_CLKR
479 reg |= FIELD_PREP(K210_PLL_CLKR, config.r - 1)
480 | FIELD_PREP(K210_PLL_CLKF, config.f - 1)
481 | FIELD_PREP(K210_PLL_CLKOD, config.od - 1)
482 | FIELD_PREP(K210_PLL_BWADJ, config.f - 1);
483 writel(reg, priv->base + pll->off);
485 err = k210_pll_enable(clk);
490 return clk_get_rate(clk);
493 ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate,
498 #endif /* CONFIG_CLK_K210_SET_RATE */
500 ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id, ulong rate_in)
503 u32 reg = readl(priv->base + k210_plls[id].off);
505 if (rate_in < 0 || (reg & K210_PLL_BYPASS))
508 if (!(reg & K210_PLL_PWRD))
511 r = FIELD_GET(K210_PLL_CLKR, reg) + 1;
512 f = FIELD_GET(K210_PLL_CLKF, reg) + 1;
513 od = FIELD_GET(K210_PLL_CLKOD, reg) + 1;
515 return DIV_ROUND_DOWN_ULL(((u64)rate_in) * f, r * od);
519 * Wait for the PLL to be locked. If the PLL is not locked, try clearing the
520 * slip before retrying
522 void k210_pll_waitfor_lock(struct k210_clk_priv *priv, int id)
524 const struct k210_pll_params *pll = &k210_plls[id];
525 u32 mask = GENMASK(pll->width - 1, 0) << pll->shift;
528 u32 reg = readl(priv->base + K210_SYSCTL_PLL_LOCK);
530 if ((reg & mask) == mask)
533 reg |= BIT(pll->shift + K210_PLL_CLEAR_SLIP);
534 writel(reg, priv->base + K210_SYSCTL_PLL_LOCK);
538 /* Adapted from sysctl_pll_enable */
539 int k210_pll_enable(struct k210_clk_priv *priv, int id)
541 const struct k210_pll_params *pll = &k210_plls[id];
542 u32 reg = readl(priv->base + pll->off);
544 if ((reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) &&
545 !(reg & K210_PLL_RESET))
548 reg |= K210_PLL_PWRD;
549 writel(reg, priv->base + pll->off);
551 /* Ensure reset is low before asserting it */
552 reg &= ~K210_PLL_RESET;
553 writel(reg, priv->base + pll->off);
554 reg |= K210_PLL_RESET;
555 writel(reg, priv->base + pll->off);
558 reg &= ~K210_PLL_RESET;
559 writel(reg, priv->base + pll->off);
561 k210_pll_waitfor_lock(priv, id);
563 reg &= ~K210_PLL_BYPASS;
565 writel(reg, priv->base + pll->off);
570 int k210_pll_disable(struct k210_clk_priv *priv, int id)
572 const struct k210_pll_params *pll = &k210_plls[id];
573 u32 reg = readl(priv->base + pll->off);
576 * Bypassing before powering off is important so child clocks don't stop
577 * working. This is especially important for pll0, the indirect parent
580 reg |= K210_PLL_BYPASS;
581 writel(reg, priv->base + pll->off);
583 reg &= ~K210_PLL_PWRD;
585 writel(reg, priv->base + pll->off);