1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
5 #define LOG_CATEGORY UCLASS_CLK
9 #include <clk-uclass.h>
15 #include <dt-bindings/clock/k210-sysctl.h>
16 #include <dt-bindings/mfd/k210-sysctl.h>
17 #include <kendryte/pll.h>
18 #include <linux/bitfield.h>
21 * struct k210_clk_priv - K210 clock driver private data
22 * @base: The base address of the sysctl device
23 * @in0: The "in0" external oscillator
25 struct k210_clk_priv {
31 * All parameters for different sub-clocks are collected into parameter arrays.
32 * These parameters are then initialized by the clock which uses them during
33 * probe. To save space, ids are automatically generated for each sub-clock by
34 * using an enum. Instead of storing a parameter struct for each clock, even for
35 * those clocks which don't use a particular type of sub-clock, we can just
36 * store the parameters for the clocks which need them.
38 * So why do it like this? Arranging all the sub-clocks together makes it very
39 * easy to find bugs in the code.
43 * enum k210_clk_div_type - The type of divider
44 * @K210_DIV_ONE: freq = parent / (reg + 1)
45 * @K210_DIV_EVEN: freq = parent / 2 / (reg + 1)
46 * @K210_DIV_POWER: freq = parent / (2 << reg)
47 * @K210_DIV_FIXED: freq = parent / factor
49 enum k210_clk_div_type {
57 * struct k210_div_params - Parameters for dividing clocks
58 * @type: An &enum k210_clk_div_type specifying the dividing formula
59 * @off: The offset of the divider from the sysctl base address
60 * @shift: The offset of the LSB of the divider
61 * @width: The number of bits in the divider
62 * @div: The fixed divisor for this divider
64 struct k210_div_params {
77 DIV(K210_CLK_ACLK, K210_SYSCTL_SEL0, 1, 2, K210_DIV_POWER) \
78 DIV(K210_CLK_APB0, K210_SYSCTL_SEL0, 3, 3, K210_DIV_ONE) \
79 DIV(K210_CLK_APB1, K210_SYSCTL_SEL0, 6, 3, K210_DIV_ONE) \
80 DIV(K210_CLK_APB2, K210_SYSCTL_SEL0, 9, 3, K210_DIV_ONE) \
81 DIV(K210_CLK_SRAM0, K210_SYSCTL_THR0, 0, 4, K210_DIV_ONE) \
82 DIV(K210_CLK_SRAM1, K210_SYSCTL_THR0, 4, 4, K210_DIV_ONE) \
83 DIV(K210_CLK_AI, K210_SYSCTL_THR0, 8, 4, K210_DIV_ONE) \
84 DIV(K210_CLK_DVP, K210_SYSCTL_THR0, 12, 4, K210_DIV_ONE) \
85 DIV(K210_CLK_ROM, K210_SYSCTL_THR0, 16, 4, K210_DIV_ONE) \
86 DIV(K210_CLK_SPI0, K210_SYSCTL_THR1, 0, 8, K210_DIV_EVEN) \
87 DIV(K210_CLK_SPI1, K210_SYSCTL_THR1, 8, 8, K210_DIV_EVEN) \
88 DIV(K210_CLK_SPI2, K210_SYSCTL_THR1, 16, 8, K210_DIV_EVEN) \
89 DIV(K210_CLK_SPI3, K210_SYSCTL_THR1, 24, 8, K210_DIV_EVEN) \
90 DIV(K210_CLK_TIMER0, K210_SYSCTL_THR2, 0, 8, K210_DIV_EVEN) \
91 DIV(K210_CLK_TIMER1, K210_SYSCTL_THR2, 8, 8, K210_DIV_EVEN) \
92 DIV(K210_CLK_TIMER2, K210_SYSCTL_THR2, 16, 8, K210_DIV_EVEN) \
93 DIV(K210_CLK_I2S0, K210_SYSCTL_THR3, 0, 16, K210_DIV_EVEN) \
94 DIV(K210_CLK_I2S1, K210_SYSCTL_THR3, 16, 16, K210_DIV_EVEN) \
95 DIV(K210_CLK_I2S2, K210_SYSCTL_THR4, 0, 16, K210_DIV_EVEN) \
96 DIV(K210_CLK_I2S0_M, K210_SYSCTL_THR4, 16, 8, K210_DIV_EVEN) \
97 DIV(K210_CLK_I2S1_M, K210_SYSCTL_THR4, 24, 8, K210_DIV_EVEN) \
98 DIV(K210_CLK_I2S2_M, K210_SYSCTL_THR4, 0, 8, K210_DIV_EVEN) \
99 DIV(K210_CLK_I2C0, K210_SYSCTL_THR5, 8, 8, K210_DIV_EVEN) \
100 DIV(K210_CLK_I2C1, K210_SYSCTL_THR5, 16, 8, K210_DIV_EVEN) \
101 DIV(K210_CLK_I2C2, K210_SYSCTL_THR5, 24, 8, K210_DIV_EVEN) \
102 DIV(K210_CLK_WDT0, K210_SYSCTL_THR6, 0, 8, K210_DIV_EVEN) \
103 DIV(K210_CLK_WDT1, K210_SYSCTL_THR6, 8, 8, K210_DIV_EVEN) \
104 DIV_FIXED(K210_CLK_CLINT, 50) \
106 #define _DIVIFY(id) K210_CLK_DIV_##id
107 #define DIVIFY(id) _DIVIFY(id)
110 #define DIV(id, ...) DIVIFY(id),
111 #define DIV_FIXED DIV
118 static const struct k210_div_params k210_divs[] = {
119 #define DIV(id, _off, _shift, _width, _type) \
126 #define DIV_FIXED(id, _div) \
128 .type = K210_DIV_FIXED, \
140 * struct k210_gate_params - Parameters for gated clocks
141 * @off: The offset of the gate from the sysctl base address
142 * @bit_idx: The index of the bit within the register
144 struct k210_gate_params {
150 GATE(K210_CLK_CPU, K210_SYSCTL_EN_CENT, 0) \
151 GATE(K210_CLK_SRAM0, K210_SYSCTL_EN_CENT, 1) \
152 GATE(K210_CLK_SRAM1, K210_SYSCTL_EN_CENT, 2) \
153 GATE(K210_CLK_APB0, K210_SYSCTL_EN_CENT, 3) \
154 GATE(K210_CLK_APB1, K210_SYSCTL_EN_CENT, 4) \
155 GATE(K210_CLK_APB2, K210_SYSCTL_EN_CENT, 5) \
156 GATE(K210_CLK_ROM, K210_SYSCTL_EN_PERI, 0) \
157 GATE(K210_CLK_DMA, K210_SYSCTL_EN_PERI, 1) \
158 GATE(K210_CLK_AI, K210_SYSCTL_EN_PERI, 2) \
159 GATE(K210_CLK_DVP, K210_SYSCTL_EN_PERI, 3) \
160 GATE(K210_CLK_FFT, K210_SYSCTL_EN_PERI, 4) \
161 GATE(K210_CLK_GPIO, K210_SYSCTL_EN_PERI, 5) \
162 GATE(K210_CLK_SPI0, K210_SYSCTL_EN_PERI, 6) \
163 GATE(K210_CLK_SPI1, K210_SYSCTL_EN_PERI, 7) \
164 GATE(K210_CLK_SPI2, K210_SYSCTL_EN_PERI, 8) \
165 GATE(K210_CLK_SPI3, K210_SYSCTL_EN_PERI, 9) \
166 GATE(K210_CLK_I2S0, K210_SYSCTL_EN_PERI, 10) \
167 GATE(K210_CLK_I2S1, K210_SYSCTL_EN_PERI, 11) \
168 GATE(K210_CLK_I2S2, K210_SYSCTL_EN_PERI, 12) \
169 GATE(K210_CLK_I2C0, K210_SYSCTL_EN_PERI, 13) \
170 GATE(K210_CLK_I2C1, K210_SYSCTL_EN_PERI, 14) \
171 GATE(K210_CLK_I2C2, K210_SYSCTL_EN_PERI, 15) \
172 GATE(K210_CLK_UART1, K210_SYSCTL_EN_PERI, 16) \
173 GATE(K210_CLK_UART2, K210_SYSCTL_EN_PERI, 17) \
174 GATE(K210_CLK_UART3, K210_SYSCTL_EN_PERI, 18) \
175 GATE(K210_CLK_AES, K210_SYSCTL_EN_PERI, 19) \
176 GATE(K210_CLK_FPIOA, K210_SYSCTL_EN_PERI, 20) \
177 GATE(K210_CLK_TIMER0, K210_SYSCTL_EN_PERI, 21) \
178 GATE(K210_CLK_TIMER1, K210_SYSCTL_EN_PERI, 22) \
179 GATE(K210_CLK_TIMER2, K210_SYSCTL_EN_PERI, 23) \
180 GATE(K210_CLK_WDT0, K210_SYSCTL_EN_PERI, 24) \
181 GATE(K210_CLK_WDT1, K210_SYSCTL_EN_PERI, 25) \
182 GATE(K210_CLK_SHA, K210_SYSCTL_EN_PERI, 26) \
183 GATE(K210_CLK_OTP, K210_SYSCTL_EN_PERI, 27) \
184 GATE(K210_CLK_RTC, K210_SYSCTL_EN_PERI, 29)
186 #define _GATEIFY(id) K210_CLK_GATE_##id
187 #define GATEIFY(id) _GATEIFY(id)
190 #define GATE(id, ...) GATEIFY(id),
196 static const struct k210_gate_params k210_gates[] = {
197 #define GATE(id, _off, _idx) \
208 /* The most parents is PLL2 */
209 #define K210_CLK_MAX_PARENTS 3
212 * struct k210_mux_params - Parameters for muxed clocks
213 * @parents: A list of parent clock ids
214 * @num_parents: The number of parent clocks
215 * @off: The offset of the mux from the base sysctl address
216 * @shift: The offset of the LSB of the mux selector
217 * @width: The number of bits in the mux selector
219 struct k210_mux_params {
220 u8 parents[K210_CLK_MAX_PARENTS];
227 #define MUX(id, reg, shift, width) \
228 MUX_PARENTS(id, reg, shift, width, K210_CLK_IN0, K210_CLK_PLL0)
230 MUX_PARENTS(K210_CLK_PLL2, K210_SYSCTL_PLL2, 26, 2, \
231 K210_CLK_IN0, K210_CLK_PLL0, K210_CLK_PLL1) \
232 MUX(K210_CLK_ACLK, K210_SYSCTL_SEL0, 0, 1) \
233 MUX(K210_CLK_SPI3, K210_SYSCTL_SEL0, 12, 1) \
234 MUX(K210_CLK_TIMER0, K210_SYSCTL_SEL0, 13, 1) \
235 MUX(K210_CLK_TIMER1, K210_SYSCTL_SEL0, 14, 1) \
236 MUX(K210_CLK_TIMER2, K210_SYSCTL_SEL0, 15, 1)
238 #define _MUXIFY(id) K210_CLK_MUX_##id
239 #define MUXIFY(id) _MUXIFY(id)
242 #define MUX_PARENTS(id, ...) MUXIFY(id),
248 static const struct k210_mux_params k210_muxes[] = {
249 #define MUX_PARENTS(id, _off, _shift, _width, ...) \
251 .parents = { __VA_ARGS__ }, \
252 .num_parents = __count_args(__VA_ARGS__), \
265 * struct k210_pll_params - K210 PLL parameters
266 * @off: The offset of the PLL from the base sysctl address
267 * @shift: The offset of the LSB of the lock status
268 * @width: The number of bits in the lock status
270 struct k210_pll_params {
276 static const struct k210_pll_params k210_plls[] = {
277 #define PLL(_off, _shift, _width) { \
282 [0] = PLL(K210_SYSCTL_PLL0, 0, 2),
283 [1] = PLL(K210_SYSCTL_PLL1, 8, 1),
284 [2] = PLL(K210_SYSCTL_PLL2, 16, 1),
289 * enum k210_clk_flags - The type of a K210 clock
290 * @K210_CLKF_MUX: This clock has a mux and not a static parent
291 * @K210_CLKF_PLL: This clock is a PLL
293 enum k210_clk_flags {
294 K210_CLKF_MUX = BIT(0),
295 K210_CLKF_PLL = BIT(1),
299 * struct k210_clk_params - The parameters defining a K210 clock
300 * @name: The name of the clock
301 * @flags: A set of &enum k210_clk_flags defining which fields are valid
302 * @mux: An &enum k210_mux_id of this clock's mux
303 * @parent: The clock id of this clock's parent
304 * @pll: The id of the PLL (if this clock is a PLL)
305 * @div: An &enum k210_div_id of this clock's divider
306 * @gate: An &enum k210_gate_id of this clock's gate
308 struct k210_clk_params {
309 #if CONFIG_IS_ENABLED(CMD_CLK)
326 static const struct k210_clk_params k210_clks[] = {
327 #if CONFIG_IS_ENABLED(CMD_CLK)
328 #define NAME(_name) .name = (_name),
332 #define CLK(id, _name, _parent, _div, _gate) \
335 .parent = (_parent), \
339 #define CLK_MUX(id, _name, _mux, _div, _gate) \
342 .flags = K210_CLKF_MUX, \
347 #define CLK_PLL(id, _pll, _parent) \
350 .flags = K210_CLKF_PLL, \
351 .parent = (_parent), \
354 #define CLK_FULL(id, name) \
355 CLK_MUX(id, name, MUXIFY(id), DIVIFY(id), GATEIFY(id))
356 #define CLK_NOMUX(id, name, parent) \
357 CLK(id, name, parent, DIVIFY(id), GATEIFY(id))
358 #define CLK_DIV(id, name, parent) \
359 CLK(id, name, parent, DIVIFY(id), K210_CLK_GATE_NONE)
360 #define CLK_GATE(id, name, parent) \
361 CLK(id, name, parent, K210_CLK_DIV_NONE, GATEIFY(id))
362 CLK_PLL(K210_CLK_PLL0, 0, K210_CLK_IN0),
363 CLK_PLL(K210_CLK_PLL1, 1, K210_CLK_IN0),
366 .flags = K210_CLKF_MUX | K210_CLKF_PLL,
367 .mux = MUXIFY(K210_CLK_PLL2),
370 CLK_MUX(K210_CLK_ACLK, "aclk", MUXIFY(K210_CLK_ACLK),
371 DIVIFY(K210_CLK_ACLK), K210_CLK_GATE_NONE),
372 CLK_FULL(K210_CLK_SPI3, "spi3"),
373 CLK_FULL(K210_CLK_TIMER0, "timer0"),
374 CLK_FULL(K210_CLK_TIMER1, "timer1"),
375 CLK_FULL(K210_CLK_TIMER2, "timer2"),
376 CLK_NOMUX(K210_CLK_SRAM0, "sram0", K210_CLK_ACLK),
377 CLK_NOMUX(K210_CLK_SRAM1, "sram1", K210_CLK_ACLK),
378 CLK_NOMUX(K210_CLK_ROM, "rom", K210_CLK_ACLK),
379 CLK_NOMUX(K210_CLK_DVP, "dvp", K210_CLK_ACLK),
380 CLK_NOMUX(K210_CLK_APB0, "apb0", K210_CLK_ACLK),
381 CLK_NOMUX(K210_CLK_APB1, "apb1", K210_CLK_ACLK),
382 CLK_NOMUX(K210_CLK_APB2, "apb2", K210_CLK_ACLK),
383 CLK_NOMUX(K210_CLK_AI, "ai", K210_CLK_PLL1),
384 CLK_NOMUX(K210_CLK_I2S0, "i2s0", K210_CLK_PLL2),
385 CLK_NOMUX(K210_CLK_I2S1, "i2s1", K210_CLK_PLL2),
386 CLK_NOMUX(K210_CLK_I2S2, "i2s2", K210_CLK_PLL2),
387 CLK_NOMUX(K210_CLK_WDT0, "wdt0", K210_CLK_IN0),
388 CLK_NOMUX(K210_CLK_WDT1, "wdt1", K210_CLK_IN0),
389 CLK_NOMUX(K210_CLK_SPI0, "spi0", K210_CLK_PLL0),
390 CLK_NOMUX(K210_CLK_SPI1, "spi1", K210_CLK_PLL0),
391 CLK_NOMUX(K210_CLK_SPI2, "spi2", K210_CLK_PLL0),
392 CLK_NOMUX(K210_CLK_I2C0, "i2c0", K210_CLK_PLL0),
393 CLK_NOMUX(K210_CLK_I2C1, "i2c1", K210_CLK_PLL0),
394 CLK_NOMUX(K210_CLK_I2C2, "i2c2", K210_CLK_PLL0),
395 CLK_DIV(K210_CLK_I2S0_M, "i2s0_m", K210_CLK_PLL2),
396 CLK_DIV(K210_CLK_I2S1_M, "i2s1_m", K210_CLK_PLL2),
397 CLK_DIV(K210_CLK_I2S2_M, "i2s2_m", K210_CLK_PLL2),
398 CLK_DIV(K210_CLK_CLINT, "clint", K210_CLK_ACLK),
399 CLK_GATE(K210_CLK_CPU, "cpu", K210_CLK_ACLK),
400 CLK_GATE(K210_CLK_DMA, "dma", K210_CLK_ACLK),
401 CLK_GATE(K210_CLK_FFT, "fft", K210_CLK_ACLK),
402 CLK_GATE(K210_CLK_GPIO, "gpio", K210_CLK_APB0),
403 CLK_GATE(K210_CLK_UART1, "uart1", K210_CLK_APB0),
404 CLK_GATE(K210_CLK_UART2, "uart2", K210_CLK_APB0),
405 CLK_GATE(K210_CLK_UART3, "uart3", K210_CLK_APB0),
406 CLK_GATE(K210_CLK_FPIOA, "fpioa", K210_CLK_APB0),
407 CLK_GATE(K210_CLK_SHA, "sha", K210_CLK_APB0),
408 CLK_GATE(K210_CLK_AES, "aes", K210_CLK_APB1),
409 CLK_GATE(K210_CLK_OTP, "otp", K210_CLK_APB1),
410 CLK_GATE(K210_CLK_RTC, "rtc", K210_CLK_IN0),
421 #define K210_PLL_CLKR GENMASK(3, 0)
422 #define K210_PLL_CLKF GENMASK(9, 4)
423 #define K210_PLL_CLKOD GENMASK(13, 10) /* Output Divider */
424 #define K210_PLL_BWADJ GENMASK(19, 14) /* BandWidth Adjust */
425 #define K210_PLL_RESET BIT(20)
426 #define K210_PLL_PWRD BIT(21) /* PoWeReD */
427 #define K210_PLL_INTFB BIT(22) /* Internal FeedBack */
428 #define K210_PLL_BYPASS BIT(23)
429 #define K210_PLL_TEST BIT(24)
430 #define K210_PLL_EN BIT(25)
431 #define K210_PLL_TEST_EN BIT(26)
433 #define K210_PLL_LOCK 0
434 #define K210_PLL_CLEAR_SLIP 2
435 #define K210_PLL_TEST_OUT 3
437 #ifdef CONFIG_CLK_K210_SET_RATE
438 static int k210_pll_enable(struct k210_clk_priv *priv, int id);
439 static int k210_pll_disable(struct k210_clk_priv *priv, int id);
440 static ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id, ulong rate_in);
443 * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc.
444 * General-Purpose PLL. The logical layout of the PLL with internal feedback is
445 * approximately the following:
463 * |phase detector|<---+
467 * +---+ |feedback clock|
468 * |VCO| +--------------+
483 * The k210 PLLs have three factors: r, f, and od. Because of the feedback mode,
484 * the effect of the division by f is to multiply the input frequency. The
485 * equation for the output rate is
486 * rate = (rate_in * f) / (r * od).
487 * Moving knowns to one side of the equation, we get
488 * rate / rate_in = f / (r * od)
489 * Rearranging slightly,
490 * abs_error = abs((rate / rate_in) - (f / (r * od))).
491 * To get relative, error, we divide by the expected ratio
492 * error = abs((rate / rate_in) - (f / (r * od))) / (rate / rate_in).
494 * error = abs(1 - f / (r * od)) / (rate / rate_in)
495 * error = abs(1 - (f * rate_in) / (r * od * rate))
496 * Using the constants ratio = rate / rate_in and inv_ratio = rate_in / rate,
497 * error = abs((f * inv_ratio) / (r * od) - 1)
498 * This is the error used in evaluating parameters.
500 * r and od are four bits each, while f is six bits. Because r and od are
501 * multiplied together, instead of the full 256 values possible if both bits
502 * were used fully, there are only 97 distinct products. Combined with f, there
503 * are 6208 theoretical settings for the PLL. However, most of these settings
504 * can be ruled out immediately because they do not have the correct ratio.
506 * In addition to the constraint of approximating the desired ratio, parameters
507 * must also keep internal pll frequencies within acceptable ranges. The divided
508 * clock's minimum and maximum frequencies have a ratio of around 128. This
509 * leaves fairly substantial room to work with, especially since the only
510 * affected parameter is r. The VCO's minimum and maximum frequency have a ratio
511 * of 5, which is considerably more restrictive.
513 * The r and od factors are stored in a table. This is to make it easy to find
514 * the next-largest product. Some products have multiple factorizations, but
515 * only when one factor has at least a 2.5x ratio to the factors of the other
516 * factorization. This is because any smaller ratio would not make a difference
517 * when ensuring the VCO's frequency is within spec.
519 * Throughout the calculation function, fixed point arithmetic is used. Because
520 * the range of rate and rate_in may be up to 1.75 GHz, or around 2^30, 64-bit
521 * 32.32 fixed-point numbers are used to represent ratios. In general, to
522 * implement division, the numerator is first multiplied by 2^32. This gives a
523 * result where the whole number part is in the upper 32 bits, and the fraction
524 * is in the lower 32 bits.
526 * In general, rounding is done to the closest integer. This helps find the best
527 * approximation for the ratio. Rounding in one direction (e.g down) could cause
528 * the function to miss a better ratio with one of the parameters increased by
533 * The factors table was generated with the following python code:
536 * return (1.0*x/y > 2.5) or (1.0*y/x > 2.5)
539 * for i in range(1, 17):
540 * for j in range(1, 17):
541 * fs = factors.get(i*j) or []
542 * if fs == [] or all([
543 * (p(i, x) and p(i, y)) or (p(j, x) and p(j, y))
544 * for (x, y) in fs]):
548 * for k, l in sorted(factors.items()):
550 * print("PACK(%s, %s)," % v)
552 #define PACK(r, od) (((((r) - 1) & 0xF) << 4) | (((od) - 1) & 0xF))
553 #define UNPACK_R(val) ((((val) >> 4) & 0xF) + 1)
554 #define UNPACK_OD(val) (((val) & 0xF) + 1)
555 static const u8 factors[] = {
659 TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in,
660 struct k210_pll_config *best)
663 s64 error, best_error;
664 u64 ratio, inv_ratio; /* fixed point 32.32 ratio of the rates */
669 * Can't go over 1.75 GHz or under 21.25 MHz due to limitations on the
670 * VCO frequency. These are not the same limits as below because od can
671 * reduce the output frequency by 16.
673 if (rate > 1750000000 || rate < 21250000)
676 /* Similar restrictions on the input rate */
677 if (rate_in > 1750000000 || rate_in < 13300000)
680 ratio = DIV_ROUND_CLOSEST_ULL((u64)rate << 32, rate_in);
681 inv_ratio = DIV_ROUND_CLOSEST_ULL((u64)rate_in << 32, rate);
682 /* Can't increase by more than 64 or reduce by more than 256 */
683 if (rate > rate_in && ratio > (64ULL << 32))
685 else if (rate <= rate_in && inv_ratio > (256ULL << 32))
689 * The divided clock (rate_in / r) must stay between 1.75 GHz and 13.3
690 * MHz. There is no minimum, since the only way to get a higher input
691 * clock than 26 MHz is to use a clock generated by a PLL. Because PLLs
692 * cannot output frequencies greater than 1.75 GHz, the minimum would
693 * never be greater than one.
695 max_r = DIV_ROUND_DOWN_ULL(rate_in, 13300000);
697 /* Variables get immediately incremented, so start at -1th iteration */
702 best_error = S64_MAX;
704 /* do-while here so we always try at least one ratio */
707 * Whether we swapped r and od while enforcing frequency limits
709 bool swapped = false;
714 * Try the next largest value for f (or r and od) and
715 * recalculate the other parameters based on that
717 if (rate > rate_in) {
719 * Skip factors of the same product if we already tried
724 r = UNPACK_R(factors[i]);
725 od = UNPACK_OD(factors[i]);
726 } while (i + 1 < ARRAY_SIZE(factors) &&
727 r * od == last_r * last_od);
730 f = (r * od * ratio + BIT(31)) >> 32;
734 u64 tmp = ++f * inv_ratio;
735 bool round_up = !!(tmp & BIT(31));
736 u32 goal = (tmp >> 32) + round_up;
739 /* Get the next r/od pair in factors */
740 while (r * od < goal && i + 1 < ARRAY_SIZE(factors)) {
742 r = UNPACK_R(factors[i]);
743 od = UNPACK_OD(factors[i]);
747 * This is a case of double rounding. If we rounded up
748 * above, we need to round down (in cases of ties) here.
749 * This prevents off-by-one errors resulting from
750 * choosing X+2 over X when X.Y rounds up to X+1 and
751 * there is no r * od = X+1. For the converse, when X.Y
752 * is rounded down to X, we should choose X+1 over X-1.
754 err = abs(r * od - goal);
755 last_err = abs(last_r * last_od - goal);
756 if (last_err < err || (round_up && last_err == err)) {
764 * Enforce limits on internal clock frequencies. If we
765 * aren't in spec, try swapping r and od. If everything is
766 * in-spec, calculate the relative error.
770 * Whether the intermediate frequencies are out-of-spec
772 bool out_of_spec = false;
778 * There is no way to only divide once; we need
779 * to examine the frequency with and without the
782 u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r);
784 if (vco > 1750000000 || vco < 340000000)
798 * Try looking ahead to see if there are
799 * additional factors for the same
802 if (i + 1 < ARRAY_SIZE(factors)) {
806 new_r = UNPACK_R(factors[i]);
807 new_od = UNPACK_OD(factors[i]);
808 if (r * od == new_r * new_od) {
820 error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od);
821 /* The lower 16 bits are spurious */
822 error = abs((error - BIT(32))) >> 16;
824 if (error < best_error) {
832 } while (f < 64 && i + 1 < ARRAY_SIZE(factors) && error != 0);
834 if (best_error == S64_MAX)
837 log_debug("best error %lld\n", best_error);
841 static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate,
845 const struct k210_pll_params *pll = &k210_plls[id];
846 struct k210_pll_config config = {};
852 log_debug("Calculating parameters with rate=%lu and rate_in=%lu\n",
854 err = k210_pll_calc_config(rate, rate_in, &config);
857 log_debug("Got r=%u f=%u od=%u\n", config.r, config.f, config.od);
860 * Don't use clk_disable as it might not actually disable the pll due to
863 k210_pll_disable(priv, id);
865 reg = readl(priv->base + pll->off);
866 reg &= ~K210_PLL_CLKR
870 reg |= FIELD_PREP(K210_PLL_CLKR, config.r - 1)
871 | FIELD_PREP(K210_PLL_CLKF, config.f - 1)
872 | FIELD_PREP(K210_PLL_CLKOD, config.od - 1)
873 | FIELD_PREP(K210_PLL_BWADJ, config.f - 1);
874 writel(reg, priv->base + pll->off);
876 err = k210_pll_enable(priv, id);
879 return k210_pll_get_rate(priv, id, rate);
882 static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate,
887 #endif /* CONFIG_CLK_K210_SET_RATE */
889 static ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id,
893 u32 reg = readl(priv->base + k210_plls[id].off);
895 if (rate_in < 0 || (reg & K210_PLL_BYPASS))
898 if (!(reg & K210_PLL_PWRD))
901 r = FIELD_GET(K210_PLL_CLKR, reg) + 1;
902 f = FIELD_GET(K210_PLL_CLKF, reg) + 1;
903 od = FIELD_GET(K210_PLL_CLKOD, reg) + 1;
905 return DIV_ROUND_DOWN_ULL(((u64)rate_in) * f, r * od);
909 * Wait for the PLL to be locked. If the PLL is not locked, try clearing the
910 * slip before retrying
912 static void k210_pll_waitfor_lock(struct k210_clk_priv *priv, int id)
914 const struct k210_pll_params *pll = &k210_plls[id];
915 u32 mask = (BIT(pll->width) - 1) << pll->shift;
918 u32 reg = readl(priv->base + K210_SYSCTL_PLL_LOCK);
920 if ((reg & mask) == mask)
923 reg |= BIT(pll->shift + K210_PLL_CLEAR_SLIP);
924 writel(reg, priv->base + K210_SYSCTL_PLL_LOCK);
928 /* Adapted from sysctl_pll_enable */
929 static int k210_pll_enable(struct k210_clk_priv *priv, int id)
931 const struct k210_pll_params *pll = &k210_plls[id];
932 u32 reg = readl(priv->base + pll->off);
934 if ((reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) &&
935 !(reg & K210_PLL_RESET))
938 reg |= K210_PLL_PWRD;
939 writel(reg, priv->base + pll->off);
941 /* Ensure reset is low before asserting it */
942 reg &= ~K210_PLL_RESET;
943 writel(reg, priv->base + pll->off);
944 reg |= K210_PLL_RESET;
945 writel(reg, priv->base + pll->off);
948 reg &= ~K210_PLL_RESET;
949 writel(reg, priv->base + pll->off);
951 k210_pll_waitfor_lock(priv, id);
953 reg &= ~K210_PLL_BYPASS;
955 writel(reg, priv->base + pll->off);
960 static int k210_pll_disable(struct k210_clk_priv *priv, int id)
962 const struct k210_pll_params *pll = &k210_plls[id];
963 u32 reg = readl(priv->base + pll->off);
966 * Bypassing before powering off is important so child clocks don't stop
967 * working. This is especially important for pll0, the indirect parent
970 reg |= K210_PLL_BYPASS;
971 writel(reg, priv->base + pll->off);
973 reg &= ~K210_PLL_PWRD;
975 writel(reg, priv->base + pll->off);
979 static u32 k210_clk_readl(struct k210_clk_priv *priv, u8 off, u8 shift,
982 u32 reg = readl(priv->base + off);
984 return (reg >> shift) & (BIT(width) - 1);
987 static void k210_clk_writel(struct k210_clk_priv *priv, u8 off, u8 shift,
990 u32 reg = readl(priv->base + off);
991 u32 mask = (BIT(width) - 1) << shift;
994 reg |= mask & (val << shift);
995 writel(reg, priv->base + off);
998 static int k210_clk_get_parent(struct k210_clk_priv *priv, int id)
1001 const struct k210_mux_params *mux;
1003 if (!(k210_clks[id].flags & K210_CLKF_MUX))
1004 return k210_clks[id].parent;
1005 mux = &k210_muxes[k210_clks[id].mux];
1007 sel = k210_clk_readl(priv, mux->off, mux->shift, mux->width);
1008 assert(sel < mux->num_parents);
1009 return mux->parents[sel];
1012 static ulong do_k210_clk_get_rate(struct k210_clk_priv *priv, int id)
1017 const struct k210_div_params *div;
1019 if (id == K210_CLK_IN0)
1020 return clk_get_rate(&priv->in0);
1022 parent = k210_clk_get_parent(priv, id);
1023 parent_rate = do_k210_clk_get_rate(priv, parent);
1025 if (k210_clks[id].flags & K210_CLKF_PLL)
1026 return k210_pll_get_rate(priv, k210_clks[id].pll, parent_rate);
1028 if (k210_clks[id].div == K210_CLK_DIV_NONE)
1030 div = &k210_divs[k210_clks[id].div];
1032 if (div->type == K210_DIV_FIXED)
1033 return parent_rate / div->div;
1035 val = k210_clk_readl(priv, div->off, div->shift, div->width);
1036 switch (div->type) {
1038 return parent_rate / (val + 1);
1040 return parent_rate / 2 / (val + 1);
1041 case K210_DIV_POWER:
1042 /* This is ACLK, which has no divider on IN0 */
1043 if (parent == K210_CLK_IN0)
1045 return parent_rate / (2 << val);
1052 static ulong k210_clk_get_rate(struct clk *clk)
1054 return do_k210_clk_get_rate(dev_get_priv(clk->dev), clk->id);
1057 static ulong k210_clk_set_rate(struct clk *clk, unsigned long rate)
1062 static int do_k210_clk_set_parent(struct k210_clk_priv *priv, int id, int new)
1065 const struct k210_mux_params *mux;
1067 if (!(k210_clks[id].flags & K210_CLKF_MUX))
1069 mux = &k210_muxes[k210_clks[id].mux];
1071 for (i = 0; i < mux->num_parents; i++) {
1072 if (mux->parents[i] == new) {
1073 k210_clk_writel(priv, mux->off, mux->shift, mux->width,
1081 static int k210_clk_set_parent(struct clk *clk, struct clk *parent)
1083 return do_k210_clk_set_parent(dev_get_priv(clk->dev), clk->id,
1087 static int k210_clk_endisable(struct k210_clk_priv *priv, int id, bool enable)
1089 int parent = k210_clk_get_parent(priv, id);
1090 const struct k210_gate_params *gate;
1092 if (id == K210_CLK_IN0) {
1094 return clk_enable(&priv->in0);
1096 return clk_disable(&priv->in0);
1099 /* Only recursively enable clocks since we don't track refcounts */
1101 int ret = k210_clk_endisable(priv, parent, true);
1103 if (ret && ret != -ENOSYS)
1107 if (k210_clks[id].flags & K210_CLKF_PLL) {
1109 return k210_pll_enable(priv, k210_clks[id].pll);
1111 return k210_pll_disable(priv, k210_clks[id].pll);
1114 if (k210_clks[id].gate == K210_CLK_GATE_NONE)
1116 gate = &k210_gates[k210_clks[id].gate];
1118 k210_clk_writel(priv, gate->off, gate->bit_idx, 1, enable);
1122 static int k210_clk_enable(struct clk *clk)
1124 return k210_clk_endisable(dev_get_priv(clk->dev), clk->id, true);
1127 static int k210_clk_disable(struct clk *clk)
1129 return k210_clk_endisable(dev_get_priv(clk->dev), clk->id, false);
1132 static int k210_clk_request(struct clk *clk)
1134 if (clk->id >= ARRAY_SIZE(k210_clks))
1139 static const struct clk_ops k210_clk_ops = {
1140 .request = k210_clk_request,
1141 .set_rate = k210_clk_set_rate,
1142 .get_rate = k210_clk_get_rate,
1143 .set_parent = k210_clk_set_parent,
1144 .enable = k210_clk_enable,
1145 .disable = k210_clk_disable,
1148 static int k210_clk_probe(struct udevice *dev)
1151 struct k210_clk_priv *priv = dev_get_priv(dev);
1153 priv->base = dev_read_addr_ptr(dev_get_parent(dev));
1157 ret = clk_get_by_index(dev, 0, &priv->in0);
1164 static const struct udevice_id k210_clk_ids[] = {
1165 { .compatible = "kendryte,k210-clk" },
1169 U_BOOT_DRIVER(k210_clk) = {
1172 .of_match = k210_clk_ids,
1173 .ops = &k210_clk_ops,
1174 .probe = k210_clk_probe,
1175 .priv_auto = sizeof(struct k210_clk_priv),