1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Ingenic JZ4740 SoC CGU driver
5 * Copyright (c) 2015 Imagination Technologies
6 * Author: Paul Burton <paul.burton@mips.com>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
13 #include <dt-bindings/clock/jz4740-cgu.h>
17 /* CGU register offsets */
18 #define CGU_REG_CPCCR 0x00
19 #define CGU_REG_LCR 0x04
20 #define CGU_REG_CPPCR 0x10
21 #define CGU_REG_CLKGR 0x20
22 #define CGU_REG_SCR 0x24
23 #define CGU_REG_I2SCDR 0x60
24 #define CGU_REG_LPCDR 0x64
25 #define CGU_REG_MSCCDR 0x68
26 #define CGU_REG_UHCCDR 0x6c
27 #define CGU_REG_SSICDR 0x74
29 /* bits within a PLL control register */
30 #define PLLCTL_M_SHIFT 23
31 #define PLLCTL_M_MASK (0x1ff << PLLCTL_M_SHIFT)
32 #define PLLCTL_N_SHIFT 18
33 #define PLLCTL_N_MASK (0x1f << PLLCTL_N_SHIFT)
34 #define PLLCTL_OD_SHIFT 16
35 #define PLLCTL_OD_MASK (0x3 << PLLCTL_OD_SHIFT)
36 #define PLLCTL_STABLE (1 << 10)
37 #define PLLCTL_BYPASS (1 << 9)
38 #define PLLCTL_ENABLE (1 << 8)
40 /* bits within the LCR register */
41 #define LCR_SLEEP (1 << 0)
43 /* bits within the CLKGR register */
44 #define CLKGR_UDC (1 << 11)
46 static struct ingenic_cgu *cgu;
48 static const s8 pll_od_encoding[4] = {
52 static const u8 jz4740_cgu_cpccr_div_table[] = {
53 1, 2, 3, 4, 6, 8, 12, 16, 24, 32,
56 static const u8 jz4740_cgu_pll_half_div_table[] = {
60 static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
64 [JZ4740_CLK_EXT] = { "ext", CGU_CLK_EXT },
65 [JZ4740_CLK_RTC] = { "rtc", CGU_CLK_EXT },
69 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
81 .od_encoding = pll_od_encoding,
88 /* Muxes & dividers */
90 [JZ4740_CLK_PLL_HALF] = {
91 "pll half", CGU_CLK_DIV,
92 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
94 CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
95 jz4740_cgu_pll_half_div_table,
101 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
103 CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
104 jz4740_cgu_cpccr_div_table,
108 [JZ4740_CLK_HCLK] = {
110 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
112 CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
113 jz4740_cgu_cpccr_div_table,
117 [JZ4740_CLK_PCLK] = {
119 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
121 CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
122 jz4740_cgu_cpccr_div_table,
126 [JZ4740_CLK_MCLK] = {
128 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
130 CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
131 jz4740_cgu_cpccr_div_table,
136 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
137 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
139 CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1,
140 jz4740_cgu_cpccr_div_table,
142 .gate = { CGU_REG_CLKGR, 10 },
145 [JZ4740_CLK_LCD_PCLK] = {
146 "lcd_pclk", CGU_CLK_DIV,
147 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
148 .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
152 "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
153 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
154 .mux = { CGU_REG_CPCCR, 31, 1 },
155 .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
156 .gate = { CGU_REG_CLKGR, 6 },
160 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
161 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 },
162 .mux = { CGU_REG_SSICDR, 31, 1 },
163 .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
164 .gate = { CGU_REG_CLKGR, 4 },
168 "mmc", CGU_CLK_DIV | CGU_CLK_GATE,
169 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
170 .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
171 .gate = { CGU_REG_CLKGR, 7 },
175 "uhc", CGU_CLK_DIV | CGU_CLK_GATE,
176 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
177 .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
178 .gate = { CGU_REG_CLKGR, 14 },
182 "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
183 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
184 .mux = { CGU_REG_CPCCR, 29, 1 },
185 .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
186 .gate = { CGU_REG_SCR, 6, true },
189 /* Gate-only clocks */
191 [JZ4740_CLK_UART0] = {
192 "uart0", CGU_CLK_GATE,
193 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
194 .gate = { CGU_REG_CLKGR, 0 },
197 [JZ4740_CLK_UART1] = {
198 "uart1", CGU_CLK_GATE,
199 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
200 .gate = { CGU_REG_CLKGR, 15 },
205 .parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
206 .gate = { CGU_REG_CLKGR, 12 },
211 .parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
212 .gate = { CGU_REG_CLKGR, 13 },
217 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
218 .gate = { CGU_REG_CLKGR, 8 },
223 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
224 .gate = { CGU_REG_CLKGR, 3 },
229 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
230 .gate = { CGU_REG_CLKGR, 5 },
235 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
236 .gate = { CGU_REG_CLKGR, 1 },
240 static void __init jz4740_cgu_init(struct device_node *np)
244 cgu = ingenic_cgu_new(jz4740_cgu_clocks,
245 ARRAY_SIZE(jz4740_cgu_clocks), np);
247 pr_err("%s: failed to initialise CGU\n", __func__);
251 retval = ingenic_cgu_register_clocks(cgu);
253 pr_err("%s: failed to register CGU Clocks\n", __func__);
255 ingenic_cgu_register_syscore_ops(cgu);
257 CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);