1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
6 #ifndef __MACH_IMX_CLK_H
7 #define __MACH_IMX_CLK_H
9 #include <linux/clk-provider.h>
23 enum imx_pll14xx_type {
28 /* NOTE: Rate table should be kept sorted in descending order. */
29 struct imx_pll14xx_rate_table {
37 struct imx_pll14xx_clk {
38 enum imx_pll14xx_type type;
39 const struct imx_pll14xx_rate_table *rate_table;
44 extern struct imx_pll14xx_clk imx_1416x_pll;
45 extern struct imx_pll14xx_clk imx_1443x_pll;
46 extern struct imx_pll14xx_clk imx_1443x_dram_pll;
48 struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
50 const struct imx_pll14xx_clk *pll_clk);
52 struct clk *clk_register_gate2(struct device *dev, const char *name,
53 const char *parent_name, unsigned long flags,
54 void __iomem *reg, u8 bit_idx, u8 cgr_val,
57 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
58 const char *parent_name, void __iomem *base,
61 static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
62 void __iomem *reg, u8 shift)
64 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
68 static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
69 void __iomem *reg, u8 shift)
71 return clk_register_gate2(NULL, name, parent,
72 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
76 static inline struct clk *imx_clk_gate4_flags(const char *name,
77 const char *parent, void __iomem *reg, u8 shift,
80 return clk_register_gate2(NULL, name, parent,
81 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
85 static inline struct clk *imx_clk_fixed_factor(const char *name,
86 const char *parent, unsigned int mult, unsigned int div)
88 return clk_register_fixed_factor(NULL, name, parent,
89 CLK_SET_RATE_PARENT, mult, div);
92 static inline struct clk *imx_clk_divider(const char *name, const char *parent,
93 void __iomem *reg, u8 shift, u8 width)
95 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
96 reg, shift, width, 0);
99 static inline struct clk *
100 imx_clk_busy_divider(const char *name, const char *parent, void __iomem *reg,
101 u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift)
103 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
104 reg, shift, width, 0);
107 static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
108 void __iomem *reg, u8 shift, u8 width)
110 return clk_register_divider(NULL, name, parent,
111 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
112 reg, shift, width, 0);
115 struct clk *imx_clk_pfd(const char *name, const char *parent_name,
116 void __iomem *reg, u8 idx);
118 struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
119 u8 shift, u8 width, const char * const *parents,
120 int num_parents, void (*fixup)(u32 *val));
122 static inline struct clk *imx_clk_mux_flags(const char *name,
123 void __iomem *reg, u8 shift, u8 width,
124 const char * const *parents, int num_parents,
127 return clk_register_mux(NULL, name, parents, num_parents,
128 flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
132 static inline struct clk *imx_clk_mux2_flags(const char *name,
133 void __iomem *reg, u8 shift, u8 width,
134 const char * const *parents,
135 int num_parents, unsigned long flags)
137 return clk_register_mux(NULL, name, parents, num_parents,
138 flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
139 reg, shift, width, 0);
142 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
143 u8 shift, u8 width, const char * const *parents,
146 return clk_register_mux(NULL, name, parents, num_parents,
147 CLK_SET_RATE_NO_REPARENT, reg, shift,
151 static inline struct clk *
152 imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width,
153 void __iomem *busy_reg, u8 busy_shift,
154 const char * const *parents, int num_parents)
156 return clk_register_mux(NULL, name, parents, num_parents,
157 CLK_SET_RATE_NO_REPARENT, reg, shift,
161 static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
162 u8 shift, u8 width, const char * const *parents,
165 return clk_register_mux(NULL, name, parents, num_parents,
166 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
167 reg, shift, width, 0);
170 static inline struct clk *imx_clk_gate(const char *name, const char *parent,
171 void __iomem *reg, u8 shift)
173 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
177 static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
178 void __iomem *reg, u8 shift, unsigned long flags)
180 return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
184 static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
185 void __iomem *reg, u8 shift)
187 return clk_register_gate(NULL, name, parent,
188 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
189 reg, shift, 0, NULL);
192 struct clk *imx8m_clk_composite_flags(const char *name,
193 const char * const *parent_names,
194 int num_parents, void __iomem *reg, unsigned long flags);
196 #define __imx8m_clk_composite(name, parent_names, reg, flags) \
197 imx8m_clk_composite_flags(name, parent_names, \
198 ARRAY_SIZE(parent_names), reg, \
199 flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
201 #define imx8m_clk_composite(name, parent_names, reg) \
202 __imx8m_clk_composite(name, parent_names, reg, 0)
204 #define imx8m_clk_composite_critical(name, parent_names, reg) \
205 __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
207 #endif /* __MACH_IMX_CLK_H */