1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2021 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com>
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <linux/arm-smccc.h>
9 #include <linux/bsearch.h>
10 #include <linux/clk-provider.h>
11 #include <linux/err.h>
12 #include <linux/of_platform.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_domain.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/slab.h>
20 #define IMX_SIP_CPUFREQ 0xC2000001
21 #define IMX_SIP_SET_CPUFREQ 0x00
23 static struct imx_sc_ipc *ccm_ipc_handle;
24 static struct device_node *pd_np;
25 static struct platform_driver imx_clk_scu_driver;
26 static const struct imx_clk_scu_rsrc_table *rsrc_table;
28 struct imx_scu_clk_node {
32 const char * const *parents;
36 struct list_head node;
39 struct list_head imx_scu_clks[IMX_SC_R_LAST];
42 * struct clk_scu - Description of one SCU clock
43 * @hw: the common clk_hw
44 * @rsrc_id: resource ID of this SCU clock
45 * @clk_type: type of this clock resource
52 /* for state save&restore */
53 struct clk_hw *parent;
60 * struct clk_gpr_scu - Description of one SCU GPR clock
61 * @hw: the common clk_hw
62 * @rsrc_id: resource ID of this SCU clock
63 * @gpr_id: GPR ID index to control the divider
73 #define to_clk_gpr_scu(_hw) container_of(_hw, struct clk_gpr_scu, hw)
76 * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
77 * @hdr: SCU protocol header
79 * @resource: clock resource to set rate
80 * @clk: clk type of this resource
82 * This structure describes the SCU protocol of clock rate set
84 struct imx_sc_msg_req_set_clock_rate {
85 struct imx_sc_rpc_msg hdr;
89 } __packed __aligned(4);
91 struct req_get_clock_rate {
94 } __packed __aligned(4);
96 struct resp_get_clock_rate {
101 * struct imx_sc_msg_get_clock_rate - clock get rate protocol
102 * @hdr: SCU protocol header
103 * @req: get rate request protocol
104 * @resp: get rate response protocol
106 * This structure describes the SCU protocol of clock rate get
108 struct imx_sc_msg_get_clock_rate {
109 struct imx_sc_rpc_msg hdr;
111 struct req_get_clock_rate req;
112 struct resp_get_clock_rate resp;
117 * struct imx_sc_msg_get_clock_parent - clock get parent protocol
118 * @hdr: SCU protocol header
119 * @req: get parent request protocol
120 * @resp: get parent response protocol
122 * This structure describes the SCU protocol of clock get parent
124 struct imx_sc_msg_get_clock_parent {
125 struct imx_sc_rpc_msg hdr;
127 struct req_get_clock_parent {
130 } __packed __aligned(4) req;
131 struct resp_get_clock_parent {
138 * struct imx_sc_msg_set_clock_parent - clock set parent protocol
139 * @hdr: SCU protocol header
140 * @req: set parent request protocol
142 * This structure describes the SCU protocol of clock set parent
144 struct imx_sc_msg_set_clock_parent {
145 struct imx_sc_rpc_msg hdr;
152 * struct imx_sc_msg_req_clock_enable - clock gate protocol
153 * @hdr: SCU protocol header
154 * @resource: clock resource to gate
155 * @clk: clk type of this resource
156 * @enable: whether gate off the clock
157 * @autog: HW auto gate enable
159 * This structure describes the SCU protocol of clock gate
161 struct imx_sc_msg_req_clock_enable {
162 struct imx_sc_rpc_msg hdr;
167 } __packed __aligned(4);
169 static inline struct clk_scu *to_clk_scu(struct clk_hw *hw)
171 return container_of(hw, struct clk_scu, hw);
174 static inline int imx_scu_clk_search_cmp(const void *rsrc, const void *rsrc_p)
176 return *(u32 *)rsrc - *(u32 *)rsrc_p;
179 static bool imx_scu_clk_is_valid(u32 rsrc_id)
186 p = bsearch(&rsrc_id, rsrc_table->rsrc, rsrc_table->num,
187 sizeof(rsrc_table->rsrc[0]), imx_scu_clk_search_cmp);
192 int imx_clk_scu_init(struct device_node *np,
193 const struct imx_clk_scu_rsrc_table *data)
198 ret = imx_scu_get_handle(&ccm_ipc_handle);
202 of_property_read_u32(np, "#clock-cells", &clk_cells);
204 if (clk_cells == 2) {
205 for (i = 0; i < IMX_SC_R_LAST; i++)
206 INIT_LIST_HEAD(&imx_scu_clks[i]);
208 /* pd_np will be used to attach power domains later */
209 pd_np = of_find_compatible_node(NULL, NULL, "fsl,scu-pd");
216 return platform_driver_register(&imx_clk_scu_driver);
220 * clk_scu_recalc_rate - Get clock rate for a SCU clock
221 * @hw: clock to get rate for
222 * @parent_rate: parent rate provided by common clock framework, not used
224 * Gets the current clock rate of a SCU clock. Returns the current
225 * clock rate, or zero in failure.
227 static unsigned long clk_scu_recalc_rate(struct clk_hw *hw,
228 unsigned long parent_rate)
230 struct clk_scu *clk = to_clk_scu(hw);
231 struct imx_sc_msg_get_clock_rate msg;
232 struct imx_sc_rpc_msg *hdr = &msg.hdr;
235 hdr->ver = IMX_SC_RPC_VERSION;
236 hdr->svc = IMX_SC_RPC_SVC_PM;
237 hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_RATE;
240 msg.data.req.resource = cpu_to_le16(clk->rsrc_id);
241 msg.data.req.clk = clk->clk_type;
243 ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
245 pr_err("%s: failed to get clock rate %d\n",
246 clk_hw_get_name(hw), ret);
250 return le32_to_cpu(msg.data.resp.rate);
254 * clk_scu_round_rate - Round clock rate for a SCU clock
255 * @hw: clock to round rate for
256 * @rate: rate to round
257 * @parent_rate: parent rate provided by common clock framework, not used
259 * Returns the current clock rate, or zero in failure.
261 static long clk_scu_round_rate(struct clk_hw *hw, unsigned long rate,
262 unsigned long *parent_rate)
265 * Assume we support all the requested rate and let the SCU firmware
266 * to handle the left work
271 static int clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate,
272 unsigned long parent_rate)
274 struct clk_scu *clk = to_clk_scu(hw);
275 struct arm_smccc_res res;
276 unsigned long cluster_id;
278 if (clk->rsrc_id == IMX_SC_R_A35 || clk->rsrc_id == IMX_SC_R_A53)
280 else if (clk->rsrc_id == IMX_SC_R_A72)
285 /* CPU frequency scaling can ONLY be done by ARM-Trusted-Firmware */
286 arm_smccc_smc(IMX_SIP_CPUFREQ, IMX_SIP_SET_CPUFREQ,
287 cluster_id, rate, 0, 0, 0, 0, &res);
293 * clk_scu_set_rate - Set rate for a SCU clock
294 * @hw: clock to change rate for
295 * @rate: target rate for the clock
296 * @parent_rate: rate of the clock parent, not used for SCU clocks
298 * Sets a clock frequency for a SCU clock. Returns the SCU
301 static int clk_scu_set_rate(struct clk_hw *hw, unsigned long rate,
302 unsigned long parent_rate)
304 struct clk_scu *clk = to_clk_scu(hw);
305 struct imx_sc_msg_req_set_clock_rate msg;
306 struct imx_sc_rpc_msg *hdr = &msg.hdr;
308 hdr->ver = IMX_SC_RPC_VERSION;
309 hdr->svc = IMX_SC_RPC_SVC_PM;
310 hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_RATE;
313 msg.rate = cpu_to_le32(rate);
314 msg.resource = cpu_to_le16(clk->rsrc_id);
315 msg.clk = clk->clk_type;
317 return imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
320 static u8 clk_scu_get_parent(struct clk_hw *hw)
322 struct clk_scu *clk = to_clk_scu(hw);
323 struct imx_sc_msg_get_clock_parent msg;
324 struct imx_sc_rpc_msg *hdr = &msg.hdr;
327 hdr->ver = IMX_SC_RPC_VERSION;
328 hdr->svc = IMX_SC_RPC_SVC_PM;
329 hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_PARENT;
332 msg.data.req.resource = cpu_to_le16(clk->rsrc_id);
333 msg.data.req.clk = clk->clk_type;
335 ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
337 pr_err("%s: failed to get clock parent %d\n",
338 clk_hw_get_name(hw), ret);
342 clk->parent_index = msg.data.resp.parent;
344 return msg.data.resp.parent;
347 static int clk_scu_set_parent(struct clk_hw *hw, u8 index)
349 struct clk_scu *clk = to_clk_scu(hw);
350 struct imx_sc_msg_set_clock_parent msg;
351 struct imx_sc_rpc_msg *hdr = &msg.hdr;
354 hdr->ver = IMX_SC_RPC_VERSION;
355 hdr->svc = IMX_SC_RPC_SVC_PM;
356 hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_PARENT;
359 msg.resource = cpu_to_le16(clk->rsrc_id);
360 msg.clk = clk->clk_type;
363 ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
365 pr_err("%s: failed to set clock parent %d\n",
366 clk_hw_get_name(hw), ret);
370 clk->parent_index = index;
375 static int sc_pm_clock_enable(struct imx_sc_ipc *ipc, u16 resource,
376 u8 clk, bool enable, bool autog)
378 struct imx_sc_msg_req_clock_enable msg;
379 struct imx_sc_rpc_msg *hdr = &msg.hdr;
381 hdr->ver = IMX_SC_RPC_VERSION;
382 hdr->svc = IMX_SC_RPC_SVC_PM;
383 hdr->func = IMX_SC_PM_FUNC_CLOCK_ENABLE;
386 msg.resource = cpu_to_le16(resource);
391 return imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
395 * clk_scu_prepare - Enable a SCU clock
396 * @hw: clock to enable
398 * Enable the clock at the DSC slice level
400 static int clk_scu_prepare(struct clk_hw *hw)
402 struct clk_scu *clk = to_clk_scu(hw);
404 return sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id,
405 clk->clk_type, true, false);
409 * clk_scu_unprepare - Disable a SCU clock
410 * @hw: clock to enable
412 * Disable the clock at the DSC slice level
414 static void clk_scu_unprepare(struct clk_hw *hw)
416 struct clk_scu *clk = to_clk_scu(hw);
419 ret = sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id,
420 clk->clk_type, false, false);
422 pr_warn("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),
426 static const struct clk_ops clk_scu_ops = {
427 .recalc_rate = clk_scu_recalc_rate,
428 .round_rate = clk_scu_round_rate,
429 .set_rate = clk_scu_set_rate,
430 .get_parent = clk_scu_get_parent,
431 .set_parent = clk_scu_set_parent,
432 .prepare = clk_scu_prepare,
433 .unprepare = clk_scu_unprepare,
436 static const struct clk_ops clk_scu_cpu_ops = {
437 .recalc_rate = clk_scu_recalc_rate,
438 .round_rate = clk_scu_round_rate,
439 .set_rate = clk_scu_atf_set_cpu_rate,
440 .prepare = clk_scu_prepare,
441 .unprepare = clk_scu_unprepare,
444 static const struct clk_ops clk_scu_pi_ops = {
445 .recalc_rate = clk_scu_recalc_rate,
446 .round_rate = clk_scu_round_rate,
447 .set_rate = clk_scu_set_rate,
450 struct clk_hw *__imx_clk_scu(struct device *dev, const char *name,
451 const char * const *parents, int num_parents,
452 u32 rsrc_id, u8 clk_type)
454 struct clk_init_data init;
459 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
461 return ERR_PTR(-ENOMEM);
463 clk->rsrc_id = rsrc_id;
464 clk->clk_type = clk_type;
467 init.ops = &clk_scu_ops;
468 if (rsrc_id == IMX_SC_R_A35 || rsrc_id == IMX_SC_R_A53 || rsrc_id == IMX_SC_R_A72)
469 init.ops = &clk_scu_cpu_ops;
470 else if (rsrc_id == IMX_SC_R_PI_0_PLL)
471 init.ops = &clk_scu_pi_ops;
473 init.ops = &clk_scu_ops;
474 init.parent_names = parents;
475 init.num_parents = num_parents;
478 * Note on MX8, the clocks are tightly coupled with power domain
479 * that once the power domain is off, the clock status may be
480 * lost. So we make it NOCACHE to let user to retrieve the real
481 * clock status from HW instead of using the possible invalid
484 init.flags = CLK_GET_RATE_NOCACHE;
485 clk->hw.init = &init;
488 ret = clk_hw_register(dev, hw);
496 dev_set_drvdata(dev, clk);
501 struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec,
504 unsigned int rsrc = clkspec->args[0];
505 unsigned int idx = clkspec->args[1];
506 struct list_head *scu_clks = data;
507 struct imx_scu_clk_node *clk;
509 list_for_each_entry(clk, &scu_clks[rsrc], node) {
510 if (clk->clk_type == idx)
514 return ERR_PTR(-ENODEV);
517 static int imx_clk_scu_probe(struct platform_device *pdev)
519 struct device *dev = &pdev->dev;
520 struct imx_scu_clk_node *clk = dev_get_platdata(dev);
524 if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) ||
525 (clk->rsrc == IMX_SC_R_A72))) {
526 pm_runtime_set_suspended(dev);
527 pm_runtime_set_autosuspend_delay(dev, 50);
528 pm_runtime_use_autosuspend(&pdev->dev);
529 pm_runtime_enable(dev);
531 ret = pm_runtime_resume_and_get(dev);
533 pm_genpd_remove_device(dev);
534 pm_runtime_disable(dev);
539 hw = __imx_clk_scu(dev, clk->name, clk->parents, clk->num_parents,
540 clk->rsrc, clk->clk_type);
542 pm_runtime_disable(dev);
547 list_add_tail(&clk->node, &imx_scu_clks[clk->rsrc]);
549 if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) ||
550 (clk->rsrc == IMX_SC_R_A72))) {
551 pm_runtime_mark_last_busy(&pdev->dev);
552 pm_runtime_put_autosuspend(&pdev->dev);
555 dev_dbg(dev, "register SCU clock rsrc:%d type:%d\n", clk->rsrc,
561 static int __maybe_unused imx_clk_scu_suspend(struct device *dev)
563 struct clk_scu *clk = dev_get_drvdata(dev);
564 u32 rsrc_id = clk->rsrc_id;
566 if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) ||
567 (rsrc_id == IMX_SC_R_A72))
570 clk->parent = clk_hw_get_parent(&clk->hw);
572 /* DC SS needs to handle bypass clock using non-cached clock rate */
573 if (clk->rsrc_id == IMX_SC_R_DC_0_VIDEO0 ||
574 clk->rsrc_id == IMX_SC_R_DC_0_VIDEO1 ||
575 clk->rsrc_id == IMX_SC_R_DC_1_VIDEO0 ||
576 clk->rsrc_id == IMX_SC_R_DC_1_VIDEO1)
577 clk->rate = clk_scu_recalc_rate(&clk->hw, 0);
579 clk->rate = clk_hw_get_rate(&clk->hw);
580 clk->is_enabled = clk_hw_is_enabled(&clk->hw);
583 dev_dbg(dev, "save parent %s idx %u\n", clk_hw_get_name(clk->parent),
587 dev_dbg(dev, "save rate %d\n", clk->rate);
590 dev_dbg(dev, "save enabled state\n");
595 static int __maybe_unused imx_clk_scu_resume(struct device *dev)
597 struct clk_scu *clk = dev_get_drvdata(dev);
598 u32 rsrc_id = clk->rsrc_id;
601 if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) ||
602 (rsrc_id == IMX_SC_R_A72))
606 ret = clk_scu_set_parent(&clk->hw, clk->parent_index);
607 dev_dbg(dev, "restore parent %s idx %u %s\n",
608 clk_hw_get_name(clk->parent),
609 clk->parent_index, !ret ? "success" : "failed");
613 ret = clk_scu_set_rate(&clk->hw, clk->rate, 0);
614 dev_dbg(dev, "restore rate %d %s\n", clk->rate,
615 !ret ? "success" : "failed");
618 if (clk->is_enabled && rsrc_id != IMX_SC_R_PI_0_PLL) {
619 ret = clk_scu_prepare(&clk->hw);
620 dev_dbg(dev, "restore enabled state %s\n",
621 !ret ? "success" : "failed");
627 static const struct dev_pm_ops imx_clk_scu_pm_ops = {
628 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_clk_scu_suspend,
632 static struct platform_driver imx_clk_scu_driver = {
634 .name = "imx-scu-clk",
635 .suppress_bind_attrs = true,
636 .pm = &imx_clk_scu_pm_ops,
638 .probe = imx_clk_scu_probe,
641 static int imx_clk_scu_attach_pd(struct device *dev, u32 rsrc_id)
643 struct of_phandle_args genpdspec = {
649 if (rsrc_id == IMX_SC_R_A35 || rsrc_id == IMX_SC_R_A53 ||
650 rsrc_id == IMX_SC_R_A72)
653 return of_genpd_add_device(&genpdspec, dev);
656 struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
657 const char * const *parents,
658 int num_parents, u32 rsrc_id, u8 clk_type)
660 struct imx_scu_clk_node clk = {
663 .clk_type = clk_type,
665 .num_parents = num_parents,
667 struct platform_device *pdev;
670 if (!imx_scu_clk_is_valid(rsrc_id))
671 return ERR_PTR(-EINVAL);
673 pdev = platform_device_alloc(name, PLATFORM_DEVID_NONE);
675 pr_err("%s: failed to allocate scu clk dev rsrc %d type %d\n",
676 name, rsrc_id, clk_type);
677 return ERR_PTR(-ENOMEM);
680 ret = platform_device_add_data(pdev, &clk, sizeof(clk));
682 platform_device_put(pdev);
686 ret = driver_set_override(&pdev->dev, &pdev->driver_override,
687 "imx-scu-clk", strlen("imx-scu-clk"));
689 platform_device_put(pdev);
693 ret = imx_clk_scu_attach_pd(&pdev->dev, rsrc_id);
695 pr_warn("%s: failed to attached the power domain %d\n",
698 platform_device_add(pdev);
700 /* For API backwards compatiblilty, simply return NULL for success */
704 void imx_clk_scu_unregister(void)
706 struct imx_scu_clk_node *clk;
709 for (i = 0; i < IMX_SC_R_LAST; i++) {
710 list_for_each_entry(clk, &imx_scu_clks[i], node) {
711 clk_hw_unregister(clk->hw);
717 static unsigned long clk_gpr_div_scu_recalc_rate(struct clk_hw *hw,
718 unsigned long parent_rate)
720 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
721 unsigned long rate = 0;
725 err = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
728 rate = val ? parent_rate / 2 : parent_rate;
730 return err ? 0 : rate;
733 static long clk_gpr_div_scu_round_rate(struct clk_hw *hw, unsigned long rate,
734 unsigned long *prate)
744 static int clk_gpr_div_scu_set_rate(struct clk_hw *hw, unsigned long rate,
745 unsigned long parent_rate)
747 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
751 val = (rate < parent_rate) ? 1 : 0;
752 err = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
755 return err ? -EINVAL : 0;
758 static const struct clk_ops clk_gpr_div_scu_ops = {
759 .recalc_rate = clk_gpr_div_scu_recalc_rate,
760 .round_rate = clk_gpr_div_scu_round_rate,
761 .set_rate = clk_gpr_div_scu_set_rate,
764 static u8 clk_gpr_mux_scu_get_parent(struct clk_hw *hw)
766 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
769 imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
775 static int clk_gpr_mux_scu_set_parent(struct clk_hw *hw, u8 index)
777 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
779 return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
783 static const struct clk_ops clk_gpr_mux_scu_ops = {
784 .get_parent = clk_gpr_mux_scu_get_parent,
785 .set_parent = clk_gpr_mux_scu_set_parent,
788 static int clk_gpr_gate_scu_prepare(struct clk_hw *hw)
790 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
792 return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
793 clk->gpr_id, !clk->gate_invert);
796 static void clk_gpr_gate_scu_unprepare(struct clk_hw *hw)
798 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
801 ret = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
802 clk->gpr_id, clk->gate_invert);
804 pr_err("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),
808 static int clk_gpr_gate_scu_is_prepared(struct clk_hw *hw)
810 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
814 ret = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
819 return clk->gate_invert ? !val : val;
822 static const struct clk_ops clk_gpr_gate_scu_ops = {
823 .prepare = clk_gpr_gate_scu_prepare,
824 .unprepare = clk_gpr_gate_scu_unprepare,
825 .is_prepared = clk_gpr_gate_scu_is_prepared,
828 struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
829 int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
832 struct imx_scu_clk_node *clk_node;
833 struct clk_gpr_scu *clk;
835 struct clk_init_data init;
838 if (rsrc_id >= IMX_SC_R_LAST || gpr_id >= IMX_SC_C_LAST)
839 return ERR_PTR(-EINVAL);
841 clk_node = kzalloc(sizeof(*clk_node), GFP_KERNEL);
843 return ERR_PTR(-ENOMEM);
845 if (!imx_scu_clk_is_valid(rsrc_id)) {
847 return ERR_PTR(-EINVAL);
850 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
853 return ERR_PTR(-ENOMEM);
856 clk->rsrc_id = rsrc_id;
857 clk->gpr_id = gpr_id;
859 clk->gate_invert = invert;
861 if (flags & IMX_SCU_GPR_CLK_GATE)
862 init.ops = &clk_gpr_gate_scu_ops;
864 if (flags & IMX_SCU_GPR_CLK_DIV)
865 init.ops = &clk_gpr_div_scu_ops;
867 if (flags & IMX_SCU_GPR_CLK_MUX)
868 init.ops = &clk_gpr_mux_scu_ops;
872 init.parent_names = parent_name;
873 init.num_parents = num_parents;
875 clk->hw.init = &init;
878 ret = clk_hw_register(NULL, hw);
885 clk_node->clk_type = gpr_id;
886 list_add_tail(&clk_node->node, &imx_scu_clks[rsrc_id]);