drivers/clk/imx/clk-pllv3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019 DENX Software Engineering
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <malloc.h>
  10 #include <clk-uclass.h>
  11 #include <dm/device.h>
  12 #include <dm/uclass.h>
  13 #include <clk.h>
  14 #include "clk.h"
  15
  16 #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC  "imx_clk_pllv3_generic"
  17 #define UBOOT_DM_CLK_IMX_PLLV3_SYS      "imx_clk_pllv3_sys"
  18 #define UBOOT_DM_CLK_IMX_PLLV3_USB      "imx_clk_pllv3_usb"
  19
  20 #define BM_PLL_POWER            (0x1 << 12)
  21 #define BM_PLL_LOCK             (0x1 << 31)
  22
  23 struct clk_pllv3 {
  24         struct clk      clk;
  25         void __iomem    *base;
  26         u32             power_bit;
  27         bool            powerup_set;
  28         u32             div_mask;
  29         u32             div_shift;
  30 };
  31
  32 #define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
  33
  34 static ulong clk_pllv3_generic_get_rate(struct clk *clk)
  35 {
  36         struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
  37         unsigned long parent_rate = clk_get_parent_rate(clk);
  38
  39         u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
  40
  41         return (div == 1) ? parent_rate * 22 : parent_rate * 20;
  42 }
  43
  44 static ulong clk_pllv3_generic_set_rate(struct clk *clk, ulong rate)
  45 {
  46         struct clk_pllv3 *pll = to_clk_pllv3(clk);
  47         unsigned long parent_rate = clk_get_parent_rate(clk);
  48         u32 val, div;
  49
  50         if (rate == parent_rate * 22)
  51                 div = 1;
  52         else if (rate == parent_rate * 20)
  53                 div = 0;
  54         else
  55                 return -EINVAL;
  56
  57         val = readl(pll->base);
  58         val &= ~(pll->div_mask << pll->div_shift);
  59         val |= (div << pll->div_shift);
  60         writel(val, pll->base);
  61
  62         /* Wait for PLL to lock */
  63         while (!(readl(pll->base) & BM_PLL_LOCK))
  64                 ;
  65
  66         return 0;
  67 }
  68
  69 static int clk_pllv3_generic_enable(struct clk *clk)
  70 {
  71         struct clk_pllv3 *pll = to_clk_pllv3(clk);
  72         u32 val;
  73
  74         val = readl(pll->base);
  75         if (pll->powerup_set)
  76                 val |= pll->power_bit;
  77         else
  78                 val &= ~pll->power_bit;
  79         writel(val, pll->base);
  80
  81         return 0;
  82 }
  83
  84 static int clk_pllv3_generic_disable(struct clk *clk)
  85 {
  86         struct clk_pllv3 *pll = to_clk_pllv3(clk);
  87         u32 val;
  88
  89         val = readl(pll->base);
  90         if (pll->powerup_set)
  91                 val &= ~pll->power_bit;
  92         else
  93                 val |= pll->power_bit;
  94         writel(val, pll->base);
  95
  96         return 0;
  97 }
  98
  99 static const struct clk_ops clk_pllv3_generic_ops = {
 100         .get_rate       = clk_pllv3_generic_get_rate,
 101         .enable         = clk_pllv3_generic_enable,
 102         .disable        = clk_pllv3_generic_disable,
 103         .set_rate       = clk_pllv3_generic_set_rate,
 104 };
 105
 106 static ulong clk_pllv3_sys_get_rate(struct clk *clk)
 107 {
 108         struct clk_pllv3 *pll = to_clk_pllv3(clk);
 109         unsigned long parent_rate = clk_get_parent_rate(clk);
 110         u32 div = readl(pll->base) & pll->div_mask;
 111
 112         return parent_rate * div / 2;
 113 }
 114
 115 static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)
 116 {
 117         struct clk_pllv3 *pll = to_clk_pllv3(clk);
 118         unsigned long parent_rate = clk_get_parent_rate(clk);
 119         unsigned long min_rate = parent_rate * 54 / 2;
 120         unsigned long max_rate = parent_rate * 108 / 2;
 121         u32 val, div;
 122
 123         if (rate < min_rate || rate > max_rate)
 124                 return -EINVAL;
 125
 126         div = rate * 2 / parent_rate;
 127         val = readl(pll->base);
 128         val &= ~pll->div_mask;
 129         val |= div;
 130         writel(val, pll->base);
 131
 132         /* Wait for PLL to lock */
 133         while (!(readl(pll->base) & BM_PLL_LOCK))
 134                 ;
 135
 136         return 0;
 137 }
 138
 139 static const struct clk_ops clk_pllv3_sys_ops = {
 140         .enable         = clk_pllv3_generic_enable,
 141         .disable        = clk_pllv3_generic_disable,
 142         .get_rate       = clk_pllv3_sys_get_rate,
 143         .set_rate       = clk_pllv3_sys_set_rate,
 144 };
 145
 146 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 147                           const char *parent_name, void __iomem *base,
 148                           u32 div_mask)
 149 {
 150         struct clk_pllv3 *pll;
 151         struct clk *clk;
 152         char *drv_name;
 153         int ret;
 154
 155         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 156         if (!pll)
 157                 return ERR_PTR(-ENOMEM);
 158
 159         pll->power_bit = BM_PLL_POWER;
 160
 161         switch (type) {
 162         case IMX_PLLV3_GENERIC:
 163                 drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC;
 164                 pll->div_shift = 0;
 165                 pll->powerup_set = false;
 166                 break;
 167         case IMX_PLLV3_SYS:
 168                 drv_name = UBOOT_DM_CLK_IMX_PLLV3_SYS;
 169                 pll->div_shift = 0;
 170                 pll->powerup_set = false;
 171                 break;
 172         case IMX_PLLV3_USB:
 173                 drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
 174                 pll->div_shift = 1;
 175                 pll->powerup_set = true;
 176                 break;
 177         default:
 178                 kfree(pll);
 179                 return ERR_PTR(-ENOTSUPP);
 180         }
 181
 182         pll->base = base;
 183         pll->div_mask = div_mask;
 184         clk = &pll->clk;
 185
 186         ret = clk_register(clk, drv_name, name, parent_name);
 187         if (ret) {
 188                 kfree(pll);
 189                 return ERR_PTR(ret);
 190         }
 191
 192         return clk;
 193 }
 194
 195 U_BOOT_DRIVER(clk_pllv3_generic) = {
 196         .name   = UBOOT_DM_CLK_IMX_PLLV3_GENERIC,
 197         .id     = UCLASS_CLK,
 198         .ops    = &clk_pllv3_generic_ops,
 199         .flags = DM_FLAG_PRE_RELOC,
 200 };
 201
 202 U_BOOT_DRIVER(clk_pllv3_sys) = {
 203         .name   = UBOOT_DM_CLK_IMX_PLLV3_SYS,
 204         .id     = UCLASS_CLK,
 205         .ops    = &clk_pllv3_sys_ops,
 206         .flags = DM_FLAG_PRE_RELOC,
 207 };
 208
 209 U_BOOT_DRIVER(clk_pllv3_usb) = {
 210         .name   = UBOOT_DM_CLK_IMX_PLLV3_USB,
 211         .id     = UCLASS_CLK,
 212         .ops    = &clk_pllv3_generic_ops,
 213         .flags = DM_FLAG_PRE_RELOC,
 214 };