drivers/clk/imx/clk-pllv3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019 DENX Software Engineering
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <div64.h>
  10 #include <malloc.h>
  11 #include <clk-uclass.h>
  12 #include <dm/device.h>
  13 #include <dm/uclass.h>
  14 #include <clk.h>
  15 #include "clk.h"
  16
  17 #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC  "imx_clk_pllv3_generic"
  18 #define UBOOT_DM_CLK_IMX_PLLV3_SYS      "imx_clk_pllv3_sys"
  19 #define UBOOT_DM_CLK_IMX_PLLV3_USB      "imx_clk_pllv3_usb"
  20 #define UBOOT_DM_CLK_IMX_PLLV3_AV       "imx_clk_pllv3_av"
  21
  22 #define PLL_NUM_OFFSET          0x10
  23 #define PLL_DENOM_OFFSET        0x20
  24
  25 #define BM_PLL_POWER            (0x1 << 12)
  26 #define BM_PLL_LOCK             (0x1 << 31)
  27
  28 struct clk_pllv3 {
  29         struct clk      clk;
  30         void __iomem    *base;
  31         u32             power_bit;
  32         bool            powerup_set;
  33         u32             div_mask;
  34         u32             div_shift;
  35 };
  36
  37 #define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
  38
  39 static ulong clk_pllv3_generic_get_rate(struct clk *clk)
  40 {
  41         struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
  42         unsigned long parent_rate = clk_get_parent_rate(clk);
  43
  44         u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
  45
  46         return (div == 1) ? parent_rate * 22 : parent_rate * 20;
  47 }
  48
  49 static ulong clk_pllv3_generic_set_rate(struct clk *clk, ulong rate)
  50 {
  51         struct clk_pllv3 *pll = to_clk_pllv3(clk);
  52         unsigned long parent_rate = clk_get_parent_rate(clk);
  53         u32 val, div;
  54
  55         if (rate == parent_rate * 22)
  56                 div = 1;
  57         else if (rate == parent_rate * 20)
  58                 div = 0;
  59         else
  60                 return -EINVAL;
  61
  62         val = readl(pll->base);
  63         val &= ~(pll->div_mask << pll->div_shift);
  64         val |= (div << pll->div_shift);
  65         writel(val, pll->base);
  66
  67         /* Wait for PLL to lock */
  68         while (!(readl(pll->base) & BM_PLL_LOCK))
  69                 ;
  70
  71         return 0;
  72 }
  73
  74 static int clk_pllv3_generic_enable(struct clk *clk)
  75 {
  76         struct clk_pllv3 *pll = to_clk_pllv3(clk);
  77         u32 val;
  78
  79         val = readl(pll->base);
  80         if (pll->powerup_set)
  81                 val |= pll->power_bit;
  82         else
  83                 val &= ~pll->power_bit;
  84         writel(val, pll->base);
  85
  86         return 0;
  87 }
  88
  89 static int clk_pllv3_generic_disable(struct clk *clk)
  90 {
  91         struct clk_pllv3 *pll = to_clk_pllv3(clk);
  92         u32 val;
  93
  94         val = readl(pll->base);
  95         if (pll->powerup_set)
  96                 val &= ~pll->power_bit;
  97         else
  98                 val |= pll->power_bit;
  99         writel(val, pll->base);
 100
 101         return 0;
 102 }
 103
 104 static const struct clk_ops clk_pllv3_generic_ops = {
 105         .get_rate       = clk_pllv3_generic_get_rate,
 106         .enable         = clk_pllv3_generic_enable,
 107         .disable        = clk_pllv3_generic_disable,
 108         .set_rate       = clk_pllv3_generic_set_rate,
 109 };
 110
 111 static ulong clk_pllv3_sys_get_rate(struct clk *clk)
 112 {
 113         struct clk_pllv3 *pll = to_clk_pllv3(clk);
 114         unsigned long parent_rate = clk_get_parent_rate(clk);
 115         u32 div = readl(pll->base) & pll->div_mask;
 116
 117         return parent_rate * div / 2;
 118 }
 119
 120 static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)
 121 {
 122         struct clk_pllv3 *pll = to_clk_pllv3(clk);
 123         unsigned long parent_rate = clk_get_parent_rate(clk);
 124         unsigned long min_rate;
 125         unsigned long max_rate;
 126         u32 val, div;
 127
 128         if (parent_rate == 0)
 129                 return -EINVAL;
 130
 131         min_rate = parent_rate * 54 / 2;
 132         max_rate = parent_rate * 108 / 2;
 133
 134         if (rate < min_rate || rate > max_rate)
 135                 return -EINVAL;
 136
 137         div = rate * 2 / parent_rate;
 138         val = readl(pll->base);
 139         val &= ~pll->div_mask;
 140         val |= div;
 141         writel(val, pll->base);
 142
 143         /* Wait for PLL to lock */
 144         while (!(readl(pll->base) & BM_PLL_LOCK))
 145                 ;
 146
 147         return 0;
 148 }
 149
 150 static const struct clk_ops clk_pllv3_sys_ops = {
 151         .enable         = clk_pllv3_generic_enable,
 152         .disable        = clk_pllv3_generic_disable,
 153         .get_rate       = clk_pllv3_sys_get_rate,
 154         .set_rate       = clk_pllv3_sys_set_rate,
 155 };
 156
 157 static ulong clk_pllv3_av_get_rate(struct clk *clk)
 158 {
 159         struct clk_pllv3 *pll = to_clk_pllv3(clk);
 160         unsigned long parent_rate = clk_get_parent_rate(clk);
 161         u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
 162         u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
 163         u32 div = readl(pll->base) & pll->div_mask;
 164         u64 temp64 = (u64)parent_rate;
 165
 166         if (mfd == 0)
 167                 return -EIO;
 168
 169         temp64 *= mfn;
 170         do_div(temp64, mfd);
 171
 172         return parent_rate * div + (unsigned long)temp64;
 173 }
 174
 175 static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)
 176 {
 177         struct clk_pllv3 *pll = to_clk_pllv3(clk);
 178         unsigned long parent_rate = clk_get_parent_rate(clk);
 179         unsigned long min_rate;
 180         unsigned long max_rate;
 181         u32 val, div;
 182         u32 mfn, mfd = 1000000;
 183         u32 max_mfd = 0x3FFFFFFF;
 184         u64 temp64;
 185
 186         if (parent_rate == 0)
 187                 return -EINVAL;
 188
 189         min_rate = parent_rate * 27;
 190         max_rate = parent_rate * 54;
 191
 192         if (rate < min_rate || rate > max_rate)
 193                 return -EINVAL;
 194
 195         if (parent_rate <= max_mfd)
 196                 mfd = parent_rate;
 197
 198         div = rate / parent_rate;
 199         temp64 = (u64)(rate - div * parent_rate);
 200         temp64 *= mfd;
 201         do_div(temp64, parent_rate);
 202         mfn = temp64;
 203
 204         val = readl(pll->base);
 205         val &= ~pll->div_mask;
 206         val |= div;
 207         writel(val, pll->base);
 208         writel(mfn, pll->base + PLL_NUM_OFFSET);
 209         writel(mfd, pll->base + PLL_DENOM_OFFSET);
 210
 211         /* Wait for PLL to lock */
 212         while (!(readl(pll->base) & BM_PLL_LOCK))
 213                 ;
 214
 215         return 0;
 216 }
 217
 218 static const struct clk_ops clk_pllv3_av_ops = {
 219         .enable         = clk_pllv3_generic_enable,
 220         .disable        = clk_pllv3_generic_disable,
 221         .get_rate       = clk_pllv3_av_get_rate,
 222         .set_rate       = clk_pllv3_av_set_rate,
 223 };
 224
 225 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 226                           const char *parent_name, void __iomem *base,
 227                           u32 div_mask)
 228 {
 229         struct clk_pllv3 *pll;
 230         struct clk *clk;
 231         char *drv_name;
 232         int ret;
 233
 234         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 235         if (!pll)
 236                 return ERR_PTR(-ENOMEM);
 237
 238         pll->power_bit = BM_PLL_POWER;
 239
 240         switch (type) {
 241         case IMX_PLLV3_GENERIC:
 242                 drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC;
 243                 pll->div_shift = 0;
 244                 pll->powerup_set = false;
 245                 break;
 246         case IMX_PLLV3_SYS:
 247                 drv_name = UBOOT_DM_CLK_IMX_PLLV3_SYS;
 248                 pll->div_shift = 0;
 249                 pll->powerup_set = false;
 250                 break;
 251         case IMX_PLLV3_USB:
 252                 drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
 253                 pll->div_shift = 1;
 254                 pll->powerup_set = true;
 255                 break;
 256         case IMX_PLLV3_AV:
 257                 drv_name = UBOOT_DM_CLK_IMX_PLLV3_AV;
 258                 pll->div_shift = 0;
 259                 pll->powerup_set = false;
 260                 break;
 261         default:
 262                 kfree(pll);
 263                 return ERR_PTR(-ENOTSUPP);
 264         }
 265
 266         pll->base = base;
 267         pll->div_mask = div_mask;
 268         clk = &pll->clk;
 269
 270         ret = clk_register(clk, drv_name, name, parent_name);
 271         if (ret) {
 272                 kfree(pll);
 273                 return ERR_PTR(ret);
 274         }
 275
 276         return clk;
 277 }
 278
 279 U_BOOT_DRIVER(clk_pllv3_generic) = {
 280         .name   = UBOOT_DM_CLK_IMX_PLLV3_GENERIC,
 281         .id     = UCLASS_CLK,
 282         .ops    = &clk_pllv3_generic_ops,
 283         .flags = DM_FLAG_PRE_RELOC,
 284 };
 285
 286 U_BOOT_DRIVER(clk_pllv3_sys) = {
 287         .name   = UBOOT_DM_CLK_IMX_PLLV3_SYS,
 288         .id     = UCLASS_CLK,
 289         .ops    = &clk_pllv3_sys_ops,
 290         .flags = DM_FLAG_PRE_RELOC,
 291 };
 292
 293 U_BOOT_DRIVER(clk_pllv3_usb) = {
 294         .name   = UBOOT_DM_CLK_IMX_PLLV3_USB,
 295         .id     = UCLASS_CLK,
 296         .ops    = &clk_pllv3_generic_ops,
 297         .flags = DM_FLAG_PRE_RELOC,
 298 };
 299
 300 U_BOOT_DRIVER(clk_pllv3_av) = {
 301         .name   = UBOOT_DM_CLK_IMX_PLLV3_AV,
 302         .id     = UCLASS_CLK,
 303         .ops    = &clk_pllv3_av_ops,
 304         .flags = DM_FLAG_PRE_RELOC,
 305 };