drivers/clk/imx/clk-imx8mp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2019 NXP
   4  * Peng Fan <peng.fan@nxp.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <clk-uclass.h>
  10 #include <dm.h>
  11 #include <log.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <dt-bindings/clock/imx8mp-clock.h>
  15
  16 #include "clk.h"
  17
  18 #define PLL_1416X_RATE(_rate, _m, _p, _s)               \
  19         {                                               \
  20                 .rate   =       (_rate),                \
  21                 .mdiv   =       (_m),                   \
  22                 .pdiv   =       (_p),                   \
  23                 .sdiv   =       (_s),                   \
  24         }
  25
  26 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k)           \
  27         {                                               \
  28                 .rate   =       (_rate),                \
  29                 .mdiv   =       (_m),                   \
  30                 .pdiv   =       (_p),                   \
  31                 .sdiv   =       (_s),                   \
  32                 .kdiv   =       (_k),                   \
  33         }
  34
  35 static const struct imx_pll14xx_rate_table imx8mp_pll1416x_tbl[] = {
  36         PLL_1416X_RATE(1800000000U, 225, 3, 0),
  37         PLL_1416X_RATE(1600000000U, 200, 3, 0),
  38         PLL_1416X_RATE(1200000000U, 300, 3, 1),
  39         PLL_1416X_RATE(1000000000U, 250, 3, 1),
  40         PLL_1416X_RATE(800000000U,  200, 3, 1),
  41         PLL_1416X_RATE(750000000U,  250, 2, 2),
  42         PLL_1416X_RATE(700000000U,  350, 3, 2),
  43         PLL_1416X_RATE(600000000U,  300, 3, 2),
  44 };
  45
  46 static const struct imx_pll14xx_rate_table imx8mp_drampll_tbl[] = {
  47         PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
  48 };
  49
  50 static struct imx_pll14xx_clk imx8mp_dram_pll __initdata = {
  51                 .type = PLL_1443X,
  52                 .rate_table = imx8mp_drampll_tbl,
  53                 .rate_count = ARRAY_SIZE(imx8mp_drampll_tbl),
  54 };
  55
  56 static struct imx_pll14xx_clk imx8mp_arm_pll __initdata = {
  57                 .type = PLL_1416X,
  58                 .rate_table = imx8mp_pll1416x_tbl,
  59                 .rate_count = ARRAY_SIZE(imx8mp_pll1416x_tbl),
  60 };
  61
  62 static struct imx_pll14xx_clk imx8mp_sys_pll __initdata = {
  63                 .type = PLL_1416X,
  64                 .rate_table = imx8mp_pll1416x_tbl,
  65                 .rate_count = ARRAY_SIZE(imx8mp_pll1416x_tbl),
  66 };
  67
  68 static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
  69 static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
  70 static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
  71 static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
  72 static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
  73 static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
  74
  75 static const char *imx8mp_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
  76                                         "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
  77                                         "audio_pll1_out", "sys_pll3_out", };
  78
  79 static const char *imx8mp_main_axi_sels[] = {"clock-osc-24m", "sys_pll2_333m", "sys_pll1_800m",
  80                                              "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
  81                                              "video_pll1_out", "sys_pll1_100m",};
  82
  83 static const char *imx8mp_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
  84                                                "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
  85                                                "sys_pll2_250m", "audio_pll1_out", };
  86
  87 static const char *imx8mp_noc_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out",
  88                                         "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
  89                                         "video_pll1_out", "audio_pll2_out", };
  90
  91 static const char *imx8mp_noc_io_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out",
  92                                            "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
  93                                            "video_pll1_out", "audio_pll2_out", };
  94
  95 static const char *imx8mp_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m",
  96                                         "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
  97                                         "audio_pll1_out", "video_pll1_out", };
  98
  99 static const char *imx8mp_dram_alt_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll1_100m",
 100                                              "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
 101                                              "audio_pll1_out", "sys_pll1_266m", };
 102
 103 static const char *imx8mp_dram_apb_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
 104                                              "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 105                                              "sys_pll2_250m", "audio_pll2_out", };
 106
 107 static const char *imx8mp_i2c5_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
 108                                          "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 109                                          "audio_pll2_out", "sys_pll1_133m", };
 110
 111 static const char *imx8mp_i2c6_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
 112                                          "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 113                                          "audio_pll2_out", "sys_pll1_133m", };
 114
 115 static const char *imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
 116                                            "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 117                                            "audio_pll2_out", "sys_pll1_100m", };
 118
 119 static const char *imx8mp_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
 120                                            "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 121                                            "audio_pll2_out", "sys_pll1_100m", };
 122
 123 static const char *imx8mp_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
 124                                          "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 125                                          "audio_pll2_out", "sys_pll1_133m", };
 126
 127 static const char *imx8mp_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
 128                                          "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 129                                          "audio_pll2_out", "sys_pll1_133m", };
 130
 131 static const char *imx8mp_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
 132                                          "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 133                                          "audio_pll2_out", "sys_pll1_133m", };
 134
 135 static const char *imx8mp_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
 136                                          "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 137                                          "audio_pll2_out", "sys_pll1_133m", };
 138
 139 static const char *imx8mp_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
 140                                           "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
 141                                           "clk_ext4", "audio_pll2_out", };
 142
 143 static const char *imx8mp_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
 144                                           "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
 145                                           "clk_ext3", "audio_pll2_out", };
 146
 147 static const char *imx8mp_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
 148                                           "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
 149                                           "clk_ext4", "audio_pll2_out", };
 150
 151 static const char *imx8mp_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
 152                                           "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
 153                                           "clk_ext3", "audio_pll2_out", };
 154
 155 static const char *imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
 156                                         "sys_pll2_100m", "sys_pll1_800m",
 157                                         "sys_pll2_500m", "clk_ext4", "audio_pll2_out" };
 158
 159 static const char *imx8mp_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m",
 160                                          "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
 161                                          "sys_pll1_80m", "sys_pll2_166m" };
 162
 163 static const char *imx8mp_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
 164                                            "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 165                                            "audio_pll2_out", "sys_pll1_100m", };
 166
 167 static const char *imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
 168
 169
 170 static ulong imx8mp_clk_get_rate(struct clk *clk)
 171 {
 172         struct clk *c;
 173         int ret;
 174
 175         debug("%s(#%lu)\n", __func__, clk->id);
 176
 177         ret = clk_get_by_id(clk->id, &c);
 178         if (ret)
 179                 return ret;
 180
 181         return clk_get_rate(c);
 182 }
 183
 184 static ulong imx8mp_clk_set_rate(struct clk *clk, unsigned long rate)
 185 {
 186         struct clk *c;
 187         int ret;
 188
 189         debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
 190
 191         ret = clk_get_by_id(clk->id, &c);
 192         if (ret)
 193                 return ret;
 194
 195         return clk_set_rate(c, rate);
 196 }
 197
 198 static int __imx8mp_clk_enable(struct clk *clk, bool enable)
 199 {
 200         struct clk *c;
 201         int ret;
 202
 203         debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
 204
 205         ret = clk_get_by_id(clk->id, &c);
 206         if (ret)
 207                 return ret;
 208
 209         if (enable)
 210                 ret = clk_enable(c);
 211         else
 212                 ret = clk_disable(c);
 213
 214         return ret;
 215 }
 216
 217 static int imx8mp_clk_disable(struct clk *clk)
 218 {
 219         return __imx8mp_clk_enable(clk, 0);
 220 }
 221
 222 static int imx8mp_clk_enable(struct clk *clk)
 223 {
 224         return __imx8mp_clk_enable(clk, 1);
 225 }
 226
 227 static struct clk_ops imx8mp_clk_ops = {
 228         .set_rate = imx8mp_clk_set_rate,
 229         .get_rate = imx8mp_clk_get_rate,
 230         .enable = imx8mp_clk_enable,
 231         .disable = imx8mp_clk_disable,
 232 };
 233
 234 static int imx8mp_clk_probe(struct udevice *dev)
 235 {
 236         void __iomem *base;
 237
 238         base = (void *)ANATOP_BASE_ADDR;
 239
 240         clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 241         clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 242         clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 243         clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 244         clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 245
 246         clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mp_dram_pll));
 247         clk_dm(IMX8MP_ARM_PLL, imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mp_arm_pll));
 248         clk_dm(IMX8MP_SYS_PLL1, imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mp_sys_pll));
 249         clk_dm(IMX8MP_SYS_PLL2, imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mp_sys_pll));
 250         clk_dm(IMX8MP_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mp_sys_pll));
 251
 252         clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT));
 253         clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT));
 254         clk_dm(IMX8MP_SYS_PLL1_BYPASS, imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT));
 255         clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT));
 256         clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT));
 257
 258         clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13));
 259         clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11));
 260         clk_dm(IMX8MP_SYS_PLL1_OUT, imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11));
 261         clk_dm(IMX8MP_SYS_PLL2_OUT, imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11));
 262         clk_dm(IMX8MP_SYS_PLL3_OUT, imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11));
 263
 264         clk_dm(IMX8MP_SYS_PLL1_40M, imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
 265         clk_dm(IMX8MP_SYS_PLL1_80M, imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
 266         clk_dm(IMX8MP_SYS_PLL1_100M, imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
 267         clk_dm(IMX8MP_SYS_PLL1_133M, imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
 268         clk_dm(IMX8MP_SYS_PLL1_160M, imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
 269         clk_dm(IMX8MP_SYS_PLL1_200M, imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
 270         clk_dm(IMX8MP_SYS_PLL1_266M, imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
 271         clk_dm(IMX8MP_SYS_PLL1_400M, imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
 272         clk_dm(IMX8MP_SYS_PLL1_800M, imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
 273
 274         clk_dm(IMX8MP_SYS_PLL2_50M, imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
 275         clk_dm(IMX8MP_SYS_PLL2_100M, imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
 276         clk_dm(IMX8MP_SYS_PLL2_125M, imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
 277         clk_dm(IMX8MP_SYS_PLL2_166M, imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
 278         clk_dm(IMX8MP_SYS_PLL2_200M, imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
 279         clk_dm(IMX8MP_SYS_PLL2_250M, imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
 280         clk_dm(IMX8MP_SYS_PLL2_333M, imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
 281         clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
 282         clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
 283
 284         base = dev_read_addr_ptr(dev);
 285         if (!base)
 286                 return -EINVAL;
 287
 288         clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels)));
 289         clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
 290         clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3));
 291
 292         clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, base + 0x8800));
 293         clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900));
 294         clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical("noc", imx8mp_noc_sels, base + 0x8d00));
 295         clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical("noc_io", imx8mp_noc_io_sels, base + 0x8d80));
 296
 297         clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical("ahb_root", imx8mp_ahb_sels, base + 0x9000));
 298
 299         clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2("ipg_root", "ahb_root", base + 0x9080, 0, 1));
 300
 301         clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite("dram_alt", imx8mp_dram_alt_sels, base + 0xa000));
 302         clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
 303         clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480));
 304         clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500));
 305         clk_dm(IMX8MP_CLK_USDHC1, imx8m_clk_composite("usdhc1", imx8mp_usdhc1_sels, base + 0xac00));
 306         clk_dm(IMX8MP_CLK_USDHC2, imx8m_clk_composite("usdhc2", imx8mp_usdhc2_sels, base + 0xac80));
 307         clk_dm(IMX8MP_CLK_I2C1, imx8m_clk_composite("i2c1", imx8mp_i2c1_sels, base + 0xad00));
 308         clk_dm(IMX8MP_CLK_I2C2, imx8m_clk_composite("i2c2", imx8mp_i2c2_sels, base + 0xad80));
 309         clk_dm(IMX8MP_CLK_I2C3, imx8m_clk_composite("i2c3", imx8mp_i2c3_sels, base + 0xae00));
 310         clk_dm(IMX8MP_CLK_I2C4, imx8m_clk_composite("i2c4", imx8mp_i2c4_sels, base + 0xae80));
 311
 312         clk_dm(IMX8MP_CLK_UART1, imx8m_clk_composite("uart1", imx8mp_uart1_sels, base + 0xaf00));
 313         clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite("uart2", imx8mp_uart2_sels, base + 0xaf80));
 314         clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite("uart3", imx8mp_uart3_sels, base + 0xb000));
 315         clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite("uart4", imx8mp_uart4_sels, base + 0xb080));
 316         clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic", imx8mp_gic_sels, base + 0xb200));
 317
 318         clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels, base + 0xb900));
 319         clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite("usdhc3", imx8mp_usdhc3_sels, base + 0xbc80));
 320
 321         clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4));
 322         clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL));
 323
 324         clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags("dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL));
 325         clk_dm(IMX8MP_CLK_GPIO1_ROOT, imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0));
 326         clk_dm(IMX8MP_CLK_GPIO2_ROOT, imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0));
 327         clk_dm(IMX8MP_CLK_GPIO3_ROOT, imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0));
 328         clk_dm(IMX8MP_CLK_GPIO4_ROOT, imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0));
 329         clk_dm(IMX8MP_CLK_GPIO5_ROOT, imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0));
 330         clk_dm(IMX8MP_CLK_I2C1_ROOT, imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
 331         clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
 332         clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
 333         clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
 334         clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0));
 335         clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0));
 336         clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
 337         clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
 338         clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
 339         clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
 340         clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
 341         clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
 342         clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
 343         clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
 344         clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
 345
 346         clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
 347
 348         return 0;
 349 }
 350
 351 static const struct udevice_id imx8mp_clk_ids[] = {
 352         { .compatible = "fsl,imx8mp-ccm" },
 353         { },
 354 };
 355
 356 U_BOOT_DRIVER(imx8mp_clk) = {
 357         .name = "clk_imx8mp",
 358         .id = UCLASS_CLK,
 359         .of_match = imx8mp_clk_ids,
 360         .ops = &imx8mp_clk_ops,
 361         .probe = imx8mp_clk_probe,
 362         .flags = DM_FLAG_PRE_RELOC,
 363 };