drivers/clk/imx/clk-imx8mm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2019 NXP
   4  * Peng Fan <peng.fan@nxp.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <clk-uclass.h>
  10 #include <dm.h>
  11 #include <log.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <dt-bindings/clock/imx8mm-clock.h>
  15
  16 #include "clk.h"
  17
  18 static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
  19 static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
  20 static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
  21 static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
  22 static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
  23 static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
  24
  25 static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
  26                                         "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
  27
  28 static const char *imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
  29                                         "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
  30
  31 #ifndef CONFIG_SPL_BUILD
  32 static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
  33                                              "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
  34
  35 static const char *imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
  36                                              "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
  37
  38 static const char *imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
  39                                                "clk_ext3", "clk_ext4", "video_pll1_out", };
  40
  41 static const char *imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
  42                                              "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
  43 #endif
  44
  45 static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
  46                                                "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
  47
  48 static const char *imx8mm_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m",
  49                                             "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
  50
  51 static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  52                                            "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
  53
  54 static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  55                                            "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
  56
  57 static const char *imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  58                                          "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  59
  60 static const char *imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  61                                          "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  62
  63 static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  64                                          "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  65
  66 static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  67                                          "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  68
  69 #ifndef CONFIG_SPL_BUILD
  70 static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
  71                                          "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
  72
  73 static const char *imx8mm_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
  74                                          "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
  75
  76 static const char *imx8mm_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
  77                                          "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
  78
  79 static const char *imx8mm_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
  80                                          "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
  81 #endif
  82
  83 static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
  84                                          "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
  85
  86 static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  87                                            "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
  88
  89 #if CONFIG_IS_ENABLED(NXP_FSPI)
  90 static const char *imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
  91                                            "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
  92 #endif
  93
  94 static const char *imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
  95                                              "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
  96
  97 static const char *imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
  98                                              "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
  99
 100 #if CONFIG_IS_ENABLED(DM_SPI)
 101 static const char *imx8mm_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
 102                                            "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
 103
 104 static const char *imx8mm_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
 105                                            "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
 106
 107 static const char *imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
 108                                            "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
 109 #endif
 110
 111 static int imx8mm_clk_probe(struct udevice *dev)
 112 {
 113         void __iomem *base;
 114
 115         base = (void *)ANATOP_BASE_ADDR;
 116
 117         clk_dm(IMX8MM_DRAM_PLL_REF_SEL,
 118                imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
 119                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 120         clk_dm(IMX8MM_ARM_PLL_REF_SEL,
 121                imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
 122                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 123         clk_dm(IMX8MM_SYS_PLL1_REF_SEL,
 124                imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
 125                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 126         clk_dm(IMX8MM_SYS_PLL2_REF_SEL,
 127                imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
 128                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 129         clk_dm(IMX8MM_SYS_PLL3_REF_SEL,
 130                imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
 131                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 132
 133         clk_dm(IMX8MM_DRAM_PLL,
 134                imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
 135                                base + 0x50, &imx_1443x_dram_pll));
 136         clk_dm(IMX8MM_ARM_PLL,
 137                imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
 138                                base + 0x84, &imx_1416x_pll));
 139         clk_dm(IMX8MM_SYS_PLL1,
 140                imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
 141                                base + 0x94, &imx_1416x_pll));
 142         clk_dm(IMX8MM_SYS_PLL2,
 143                imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
 144                                base + 0x104, &imx_1416x_pll));
 145         clk_dm(IMX8MM_SYS_PLL3,
 146                imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
 147                                base + 0x114, &imx_1416x_pll));
 148
 149         /* PLL bypass out */
 150         clk_dm(IMX8MM_DRAM_PLL_BYPASS,
 151                imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
 152                                  dram_pll_bypass_sels,
 153                                  ARRAY_SIZE(dram_pll_bypass_sels),
 154                                  CLK_SET_RATE_PARENT));
 155         clk_dm(IMX8MM_ARM_PLL_BYPASS,
 156                imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
 157                                  arm_pll_bypass_sels,
 158                                  ARRAY_SIZE(arm_pll_bypass_sels),
 159                                  CLK_SET_RATE_PARENT));
 160         clk_dm(IMX8MM_SYS_PLL1_BYPASS,
 161                imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
 162                                  sys_pll1_bypass_sels,
 163                                  ARRAY_SIZE(sys_pll1_bypass_sels),
 164                                  CLK_SET_RATE_PARENT));
 165         clk_dm(IMX8MM_SYS_PLL2_BYPASS,
 166                imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
 167                                  sys_pll2_bypass_sels,
 168                                  ARRAY_SIZE(sys_pll2_bypass_sels),
 169                                  CLK_SET_RATE_PARENT));
 170         clk_dm(IMX8MM_SYS_PLL3_BYPASS,
 171                imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
 172                                  sys_pll3_bypass_sels,
 173                                  ARRAY_SIZE(sys_pll3_bypass_sels),
 174                                  CLK_SET_RATE_PARENT));
 175
 176         /* PLL out gate */
 177         clk_dm(IMX8MM_DRAM_PLL_OUT,
 178                imx_clk_gate("dram_pll_out", "dram_pll_bypass",
 179                             base + 0x50, 13));
 180         clk_dm(IMX8MM_ARM_PLL_OUT,
 181                imx_clk_gate("arm_pll_out", "arm_pll_bypass",
 182                             base + 0x84, 11));
 183         clk_dm(IMX8MM_SYS_PLL1_OUT,
 184                imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
 185                             base + 0x94, 11));
 186         clk_dm(IMX8MM_SYS_PLL2_OUT,
 187                imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
 188                             base + 0x104, 11));
 189         clk_dm(IMX8MM_SYS_PLL3_OUT,
 190                imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
 191                             base + 0x114, 11));
 192
 193         /* SYS PLL fixed output */
 194         clk_dm(IMX8MM_SYS_PLL1_40M,
 195                imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
 196         clk_dm(IMX8MM_SYS_PLL1_80M,
 197                imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
 198         clk_dm(IMX8MM_SYS_PLL1_100M,
 199                imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
 200         clk_dm(IMX8MM_SYS_PLL1_133M,
 201                imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
 202         clk_dm(IMX8MM_SYS_PLL1_160M,
 203                imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
 204         clk_dm(IMX8MM_SYS_PLL1_200M,
 205                imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
 206         clk_dm(IMX8MM_SYS_PLL1_266M,
 207                imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
 208         clk_dm(IMX8MM_SYS_PLL1_400M,
 209                imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
 210         clk_dm(IMX8MM_SYS_PLL1_800M,
 211                imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
 212
 213         clk_dm(IMX8MM_SYS_PLL2_50M,
 214                imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
 215         clk_dm(IMX8MM_SYS_PLL2_100M,
 216                imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
 217         clk_dm(IMX8MM_SYS_PLL2_125M,
 218                imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
 219         clk_dm(IMX8MM_SYS_PLL2_166M,
 220                imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
 221         clk_dm(IMX8MM_SYS_PLL2_200M,
 222                imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
 223         clk_dm(IMX8MM_SYS_PLL2_250M,
 224                imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
 225         clk_dm(IMX8MM_SYS_PLL2_333M,
 226                imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
 227         clk_dm(IMX8MM_SYS_PLL2_500M,
 228                imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
 229         clk_dm(IMX8MM_SYS_PLL2_1000M,
 230                imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
 231
 232         base = dev_read_addr_ptr(dev);
 233         if (!base)
 234                 return -EINVAL;
 235
 236         clk_dm(IMX8MM_CLK_A53_SRC,
 237                imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
 238                             imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)));
 239         clk_dm(IMX8MM_CLK_A53_CG,
 240                imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
 241         clk_dm(IMX8MM_CLK_A53_DIV,
 242                imx_clk_divider2("arm_a53_div", "arm_a53_cg",
 243                                 base + 0x8000, 0, 3));
 244
 245         clk_dm(IMX8MM_CLK_AHB,
 246                imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels,
 247                                             base + 0x9000));
 248         clk_dm(IMX8MM_CLK_IPG_ROOT,
 249                imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
 250
 251         clk_dm(IMX8MM_CLK_NAND_USDHC_BUS,
 252                imx8m_clk_composite_critical("nand_usdhc_bus",
 253                                             imx8mm_nand_usdhc_sels,
 254                                             base + 0x8900));
 255         clk_dm(IMX8MM_CLK_USB_BUS,
 256                 imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
 257
 258         /* IP */
 259         clk_dm(IMX8MM_CLK_USDHC1,
 260                imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
 261                                    base + 0xac00));
 262         clk_dm(IMX8MM_CLK_USDHC2,
 263                imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels,
 264                                    base + 0xac80));
 265         clk_dm(IMX8MM_CLK_I2C1,
 266                imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00));
 267         clk_dm(IMX8MM_CLK_I2C2,
 268                imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80));
 269         clk_dm(IMX8MM_CLK_I2C3,
 270                imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
 271         clk_dm(IMX8MM_CLK_I2C4,
 272                imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
 273         clk_dm(IMX8MM_CLK_WDOG,
 274                imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
 275         clk_dm(IMX8MM_CLK_USDHC3,
 276                imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
 277                                    base + 0xbc80));
 278         clk_dm(IMX8MM_CLK_USB_CORE_REF,
 279                 imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
 280         clk_dm(IMX8MM_CLK_USB_PHY_REF,
 281                 imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
 282         clk_dm(IMX8MM_CLK_I2C1_ROOT,
 283                imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
 284         clk_dm(IMX8MM_CLK_I2C2_ROOT,
 285                imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
 286         clk_dm(IMX8MM_CLK_I2C3_ROOT,
 287                imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
 288         clk_dm(IMX8MM_CLK_I2C4_ROOT,
 289                imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
 290         clk_dm(IMX8MM_CLK_OCOTP_ROOT,
 291                imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
 292         clk_dm(IMX8MM_CLK_USDHC1_ROOT,
 293                imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
 294         clk_dm(IMX8MM_CLK_USDHC2_ROOT,
 295                imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
 296         clk_dm(IMX8MM_CLK_WDOG1_ROOT,
 297                imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
 298         clk_dm(IMX8MM_CLK_WDOG2_ROOT,
 299                imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
 300         clk_dm(IMX8MM_CLK_WDOG3_ROOT,
 301                imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
 302         clk_dm(IMX8MM_CLK_USDHC3_ROOT,
 303                imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
 304         clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
 305                 imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
 306
 307         /* clks not needed in SPL stage */
 308 #ifndef CONFIG_SPL_BUILD
 309         clk_dm(IMX8MM_CLK_ENET_AXI,
 310                imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
 311                                    base + 0x8880));
 312         clk_dm(IMX8MM_CLK_ENET_REF,
 313                imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels,
 314                base + 0xa980));
 315         clk_dm(IMX8MM_CLK_ENET_TIMER,
 316                imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels,
 317                base + 0xaa00));
 318         clk_dm(IMX8MM_CLK_ENET_PHY_REF,
 319                imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels,
 320                base + 0xaa80));
 321         clk_dm(IMX8MM_CLK_ENET1_ROOT,
 322                imx_clk_gate4("enet1_root_clk", "enet_axi",
 323                base + 0x40a0, 0));
 324         clk_dm(IMX8MM_CLK_PWM1,
 325                imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380));
 326         clk_dm(IMX8MM_CLK_PWM2,
 327                imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400));
 328         clk_dm(IMX8MM_CLK_PWM3,
 329                imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480));
 330         clk_dm(IMX8MM_CLK_PWM4,
 331                imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500));
 332         clk_dm(IMX8MM_CLK_PWM1_ROOT,
 333                imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
 334         clk_dm(IMX8MM_CLK_PWM2_ROOT,
 335                imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
 336         clk_dm(IMX8MM_CLK_PWM3_ROOT,
 337                imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
 338         clk_dm(IMX8MM_CLK_PWM4_ROOT,
 339                imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
 340 #endif
 341
 342 #if CONFIG_IS_ENABLED(DM_SPI)
 343         clk_dm(IMX8MM_CLK_ECSPI1,
 344                imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
 345         clk_dm(IMX8MM_CLK_ECSPI2,
 346                imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300));
 347         clk_dm(IMX8MM_CLK_ECSPI3,
 348                imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180));
 349
 350         clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
 351                imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
 352         clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
 353                imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
 354         clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
 355                imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
 356 #endif
 357
 358 #if CONFIG_IS_ENABLED(NXP_FSPI)
 359         clk_dm(IMX8MM_CLK_QSPI,
 360                imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80));
 361         clk_dm(IMX8MM_CLK_QSPI_ROOT,
 362                imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
 363 #endif
 364
 365         return 0;
 366 }
 367
 368 static const struct udevice_id imx8mm_clk_ids[] = {
 369         { .compatible = "fsl,imx8mm-ccm" },
 370         { },
 371 };
 372
 373 U_BOOT_DRIVER(imx8mm_clk) = {
 374         .name = "clk_imx8mm",
 375         .id = UCLASS_CLK,
 376         .of_match = imx8mm_clk_ids,
 377         .ops = &ccf_clk_ops,
 378         .probe = imx8mm_clk_probe,
 379         .flags = DM_FLAG_PRE_RELOC,
 380 };