1 // SPDX-License-Identifier: GPL-2.0
4 * Peng Fan <peng.fan@nxp.com>
9 #include <clk-uclass.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/imx-regs.h>
14 #include <dt-bindings/clock/imx8mm-clock.h>
18 static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
19 static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
20 static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
21 static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
22 static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
23 static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
25 static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
26 "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
28 static const char *imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
29 "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
31 #ifndef CONFIG_SPL_BUILD
32 static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
33 "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
35 static const char *imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
36 "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
38 static const char *imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
39 "clk_ext3", "clk_ext4", "video_pll1_out", };
41 static const char *imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
42 "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
45 static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
46 "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
48 static const char *imx8mm_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m",
49 "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
51 static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
52 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
54 static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
55 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
57 static const char *imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
58 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
60 static const char *imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
61 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
63 static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
64 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
66 static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
67 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
69 #ifndef CONFIG_SPL_BUILD
70 static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
71 "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
73 static const char *imx8mm_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
74 "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
76 static const char *imx8mm_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
77 "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
79 static const char *imx8mm_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
80 "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
83 static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
84 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
86 static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
87 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
89 static const char *imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
90 "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
92 static const char *imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
93 "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
95 static const char *imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
96 "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
98 #if CONFIG_IS_ENABLED(DM_SPI)
99 static const char *imx8mm_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
100 "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
102 static const char *imx8mm_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
103 "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
105 static const char *imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
106 "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
109 static int imx8mm_clk_probe(struct udevice *dev)
113 base = (void *)ANATOP_BASE_ADDR;
115 clk_dm(IMX8MM_DRAM_PLL_REF_SEL,
116 imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
117 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
118 clk_dm(IMX8MM_ARM_PLL_REF_SEL,
119 imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
120 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
121 clk_dm(IMX8MM_SYS_PLL1_REF_SEL,
122 imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
123 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
124 clk_dm(IMX8MM_SYS_PLL2_REF_SEL,
125 imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
126 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
127 clk_dm(IMX8MM_SYS_PLL3_REF_SEL,
128 imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
129 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
131 clk_dm(IMX8MM_DRAM_PLL,
132 imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
133 base + 0x50, &imx_1443x_dram_pll));
134 clk_dm(IMX8MM_ARM_PLL,
135 imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
136 base + 0x84, &imx_1416x_pll));
137 clk_dm(IMX8MM_SYS_PLL1,
138 imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
139 base + 0x94, &imx_1416x_pll));
140 clk_dm(IMX8MM_SYS_PLL2,
141 imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
142 base + 0x104, &imx_1416x_pll));
143 clk_dm(IMX8MM_SYS_PLL3,
144 imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
145 base + 0x114, &imx_1416x_pll));
148 clk_dm(IMX8MM_DRAM_PLL_BYPASS,
149 imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
150 dram_pll_bypass_sels,
151 ARRAY_SIZE(dram_pll_bypass_sels),
152 CLK_SET_RATE_PARENT));
153 clk_dm(IMX8MM_ARM_PLL_BYPASS,
154 imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
156 ARRAY_SIZE(arm_pll_bypass_sels),
157 CLK_SET_RATE_PARENT));
158 clk_dm(IMX8MM_SYS_PLL1_BYPASS,
159 imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
160 sys_pll1_bypass_sels,
161 ARRAY_SIZE(sys_pll1_bypass_sels),
162 CLK_SET_RATE_PARENT));
163 clk_dm(IMX8MM_SYS_PLL2_BYPASS,
164 imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
165 sys_pll2_bypass_sels,
166 ARRAY_SIZE(sys_pll2_bypass_sels),
167 CLK_SET_RATE_PARENT));
168 clk_dm(IMX8MM_SYS_PLL3_BYPASS,
169 imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
170 sys_pll3_bypass_sels,
171 ARRAY_SIZE(sys_pll3_bypass_sels),
172 CLK_SET_RATE_PARENT));
175 clk_dm(IMX8MM_DRAM_PLL_OUT,
176 imx_clk_gate("dram_pll_out", "dram_pll_bypass",
178 clk_dm(IMX8MM_ARM_PLL_OUT,
179 imx_clk_gate("arm_pll_out", "arm_pll_bypass",
181 clk_dm(IMX8MM_SYS_PLL1_OUT,
182 imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
184 clk_dm(IMX8MM_SYS_PLL2_OUT,
185 imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
187 clk_dm(IMX8MM_SYS_PLL3_OUT,
188 imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
191 /* SYS PLL fixed output */
192 clk_dm(IMX8MM_SYS_PLL1_40M,
193 imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
194 clk_dm(IMX8MM_SYS_PLL1_80M,
195 imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
196 clk_dm(IMX8MM_SYS_PLL1_100M,
197 imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
198 clk_dm(IMX8MM_SYS_PLL1_133M,
199 imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
200 clk_dm(IMX8MM_SYS_PLL1_160M,
201 imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
202 clk_dm(IMX8MM_SYS_PLL1_200M,
203 imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
204 clk_dm(IMX8MM_SYS_PLL1_266M,
205 imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
206 clk_dm(IMX8MM_SYS_PLL1_400M,
207 imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
208 clk_dm(IMX8MM_SYS_PLL1_800M,
209 imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
211 clk_dm(IMX8MM_SYS_PLL2_50M,
212 imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
213 clk_dm(IMX8MM_SYS_PLL2_100M,
214 imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
215 clk_dm(IMX8MM_SYS_PLL2_125M,
216 imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
217 clk_dm(IMX8MM_SYS_PLL2_166M,
218 imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
219 clk_dm(IMX8MM_SYS_PLL2_200M,
220 imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
221 clk_dm(IMX8MM_SYS_PLL2_250M,
222 imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
223 clk_dm(IMX8MM_SYS_PLL2_333M,
224 imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
225 clk_dm(IMX8MM_SYS_PLL2_500M,
226 imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
227 clk_dm(IMX8MM_SYS_PLL2_1000M,
228 imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
230 base = dev_read_addr_ptr(dev);
234 clk_dm(IMX8MM_CLK_A53_SRC,
235 imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
236 imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)));
237 clk_dm(IMX8MM_CLK_A53_CG,
238 imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
239 clk_dm(IMX8MM_CLK_A53_DIV,
240 imx_clk_divider2("arm_a53_div", "arm_a53_cg",
241 base + 0x8000, 0, 3));
243 clk_dm(IMX8MM_CLK_AHB,
244 imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels,
246 clk_dm(IMX8MM_CLK_IPG_ROOT,
247 imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
249 clk_dm(IMX8MM_CLK_NAND_USDHC_BUS,
250 imx8m_clk_composite_critical("nand_usdhc_bus",
251 imx8mm_nand_usdhc_sels,
253 clk_dm(IMX8MM_CLK_USB_BUS,
254 imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
257 clk_dm(IMX8MM_CLK_USDHC1,
258 imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
260 clk_dm(IMX8MM_CLK_USDHC2,
261 imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels,
263 clk_dm(IMX8MM_CLK_I2C1,
264 imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00));
265 clk_dm(IMX8MM_CLK_I2C2,
266 imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80));
267 clk_dm(IMX8MM_CLK_I2C3,
268 imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
269 clk_dm(IMX8MM_CLK_I2C4,
270 imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
271 clk_dm(IMX8MM_CLK_WDOG,
272 imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
273 clk_dm(IMX8MM_CLK_USDHC3,
274 imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
276 clk_dm(IMX8MM_CLK_QSPI,
277 imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80));
278 clk_dm(IMX8MM_CLK_USB_CORE_REF,
279 imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
280 clk_dm(IMX8MM_CLK_USB_PHY_REF,
281 imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
282 clk_dm(IMX8MM_CLK_I2C1_ROOT,
283 imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
284 clk_dm(IMX8MM_CLK_I2C2_ROOT,
285 imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
286 clk_dm(IMX8MM_CLK_I2C3_ROOT,
287 imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
288 clk_dm(IMX8MM_CLK_I2C4_ROOT,
289 imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
290 clk_dm(IMX8MM_CLK_OCOTP_ROOT,
291 imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
292 clk_dm(IMX8MM_CLK_USDHC1_ROOT,
293 imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
294 clk_dm(IMX8MM_CLK_USDHC2_ROOT,
295 imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
296 clk_dm(IMX8MM_CLK_WDOG1_ROOT,
297 imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
298 clk_dm(IMX8MM_CLK_WDOG2_ROOT,
299 imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
300 clk_dm(IMX8MM_CLK_WDOG3_ROOT,
301 imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
302 clk_dm(IMX8MM_CLK_USDHC3_ROOT,
303 imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
304 clk_dm(IMX8MM_CLK_QSPI_ROOT,
305 imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
306 clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
307 imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
309 /* clks not needed in SPL stage */
310 #ifndef CONFIG_SPL_BUILD
311 clk_dm(IMX8MM_CLK_ENET_AXI,
312 imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
314 clk_dm(IMX8MM_CLK_ENET_REF,
315 imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels,
317 clk_dm(IMX8MM_CLK_ENET_TIMER,
318 imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels,
320 clk_dm(IMX8MM_CLK_ENET_PHY_REF,
321 imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels,
323 clk_dm(IMX8MM_CLK_ENET1_ROOT,
324 imx_clk_gate4("enet1_root_clk", "enet_axi",
326 clk_dm(IMX8MM_CLK_PWM1,
327 imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380));
328 clk_dm(IMX8MM_CLK_PWM2,
329 imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400));
330 clk_dm(IMX8MM_CLK_PWM3,
331 imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480));
332 clk_dm(IMX8MM_CLK_PWM4,
333 imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500));
334 clk_dm(IMX8MM_CLK_PWM1_ROOT,
335 imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
336 clk_dm(IMX8MM_CLK_PWM2_ROOT,
337 imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
338 clk_dm(IMX8MM_CLK_PWM3_ROOT,
339 imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
340 clk_dm(IMX8MM_CLK_PWM4_ROOT,
341 imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
344 #if CONFIG_IS_ENABLED(DM_SPI)
345 clk_dm(IMX8MM_CLK_ECSPI1,
346 imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
347 clk_dm(IMX8MM_CLK_ECSPI2,
348 imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300));
349 clk_dm(IMX8MM_CLK_ECSPI3,
350 imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180));
352 clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
353 imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
354 clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
355 imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
356 clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
357 imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
363 static const struct udevice_id imx8mm_clk_ids[] = {
364 { .compatible = "fsl,imx8mm-ccm" },
368 U_BOOT_DRIVER(imx8mm_clk) = {
369 .name = "clk_imx8mm",
371 .of_match = imx8mm_clk_ids,
373 .probe = imx8mm_clk_probe,
374 .flags = DM_FLAG_PRE_RELOC,