drivers/clk/imx/clk-imx6q.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 DENX Software Engineering
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <log.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <dt-bindings/clock/imx6qdl-clock.h>
  14
  15 #include "clk.h"
  16
  17 static int imx6q_clk_request(struct clk *clk)
  18 {
  19         if (clk->id < IMX6QDL_CLK_DUMMY || clk->id >= IMX6QDL_CLK_END) {
  20                 printf("%s: Invalid clk ID #%lu\n", __func__, clk->id);
  21                 return -EINVAL;
  22         }
  23
  24         return 0;
  25 }
  26
  27 static struct clk_ops imx6q_clk_ops = {
  28         .request = imx6q_clk_request,
  29         .set_rate = ccf_clk_set_rate,
  30         .get_rate = ccf_clk_get_rate,
  31         .enable = ccf_clk_enable,
  32         .disable = ccf_clk_disable,
  33 };
  34
  35 static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
  36 static const char *const periph_sels[]  = { "periph_pre", "periph_clk2", };
  37 static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m",
  38                                                "pll2_pfd0_352m", "pll2_198m", };
  39
  40 static int imx6q_clk_probe(struct udevice *dev)
  41 {
  42         void *base;
  43
  44         /* Anatop clocks */
  45         base = (void *)ANATOP_BASE_ADDR;
  46
  47         clk_dm(IMX6QDL_CLK_PLL2,
  48                imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc",
  49                              base + 0x30, 0x1));
  50         clk_dm(IMX6QDL_CLK_PLL3_USB_OTG,
  51                imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
  52                              base + 0x10, 0x3));
  53         clk_dm(IMX6QDL_CLK_PLL3_60M,
  54                imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8));
  55         clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M,
  56                imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0));
  57         clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M,
  58                imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2));
  59         clk_dm(IMX6QDL_CLK_PLL6,
  60                imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3));
  61         clk_dm(IMX6QDL_CLK_PLL6_ENET,
  62                imx_clk_gate("pll6_enet", "pll6", base + 0xe0, 13));
  63
  64         /* CCM clocks */
  65         base = dev_read_addr_ptr(dev);
  66         if (!base)
  67                 return -EINVAL;
  68
  69         clk_dm(IMX6QDL_CLK_USDHC1_SEL,
  70                imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
  71                            usdhc_sels, ARRAY_SIZE(usdhc_sels)));
  72         clk_dm(IMX6QDL_CLK_USDHC2_SEL,
  73                imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
  74                            usdhc_sels, ARRAY_SIZE(usdhc_sels)));
  75         clk_dm(IMX6QDL_CLK_USDHC3_SEL,
  76                imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1,
  77                            usdhc_sels, ARRAY_SIZE(usdhc_sels)));
  78         clk_dm(IMX6QDL_CLK_USDHC4_SEL,
  79                imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1,
  80                            usdhc_sels, ARRAY_SIZE(usdhc_sels)));
  81
  82         clk_dm(IMX6QDL_CLK_USDHC1_PODF,
  83                imx_clk_divider("usdhc1_podf", "usdhc1_sel",
  84                                base + 0x24, 11, 3));
  85         clk_dm(IMX6QDL_CLK_USDHC2_PODF,
  86                imx_clk_divider("usdhc2_podf", "usdhc2_sel",
  87                                base + 0x24, 16, 3));
  88         clk_dm(IMX6QDL_CLK_USDHC3_PODF,
  89                imx_clk_divider("usdhc3_podf", "usdhc3_sel",
  90                                base + 0x24, 19, 3));
  91         clk_dm(IMX6QDL_CLK_USDHC4_PODF,
  92                imx_clk_divider("usdhc4_podf", "usdhc4_sel",
  93                                base + 0x24, 22, 3));
  94
  95         clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
  96                imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
  97
  98         clk_dm(IMX6QDL_CLK_ECSPI1,
  99                imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
 100         clk_dm(IMX6QDL_CLK_ECSPI2,
 101                imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2));
 102         clk_dm(IMX6QDL_CLK_ECSPI3,
 103                imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4));
 104         clk_dm(IMX6QDL_CLK_ECSPI4,
 105                imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6));
 106         clk_dm(IMX6QDL_CLK_USDHC1,
 107                imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
 108         clk_dm(IMX6QDL_CLK_USDHC2,
 109                imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
 110         clk_dm(IMX6QDL_CLK_USDHC3,
 111                imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6));
 112         clk_dm(IMX6QDL_CLK_USDHC4,
 113                imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8));
 114
 115         clk_dm(IMX6QDL_CLK_PERIPH_PRE,
 116                imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels,
 117                            ARRAY_SIZE(periph_pre_sels)));
 118         clk_dm(IMX6QDL_CLK_PERIPH,
 119                imx_clk_busy_mux("periph",  base + 0x14, 25, 1, base + 0x48,
 120                                 5, periph_sels,  ARRAY_SIZE(periph_sels)));
 121         clk_dm(IMX6QDL_CLK_AHB,
 122                imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3,
 123                                     base + 0x48, 1));
 124         clk_dm(IMX6QDL_CLK_IPG,
 125                imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2));
 126         clk_dm(IMX6QDL_CLK_IPG_PER,
 127                imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6));
 128         clk_dm(IMX6QDL_CLK_I2C1,
 129                imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6));
 130         clk_dm(IMX6QDL_CLK_I2C2,
 131                imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8));
 132
 133         clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2("enet", "ipg", base + 0x6c, 10));
 134         clk_dm(IMX6QDL_CLK_ENET_REF,
 135                imx_clk_fixed_factor("enet_ref", "pll6_enet", 1, 1));
 136
 137         return 0;
 138 }
 139
 140 static const struct udevice_id imx6q_clk_ids[] = {
 141         { .compatible = "fsl,imx6q-ccm" },
 142         { },
 143 };
 144
 145 U_BOOT_DRIVER(imx6q_clk) = {
 146         .name = "clk_imx6q",
 147         .id = UCLASS_CLK,
 148         .of_match = imx6q_clk_ids,
 149         .ops = &imx6q_clk_ops,
 150         .probe = imx6q_clk_probe,
 151         .flags = DM_FLAG_PRE_RELOC,
 152 };