1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * Gated clock implementation
9 #include <linux/clk-provider.h>
10 #include <linux/module.h>
11 #include <linux/slab.h>
13 #include <linux/err.h>
14 #include <linux/string.h>
18 * DOC: basic gatable clock which can gate and ungate it's ouput
20 * Traits of this clock:
21 * prepare - clk_(un)prepare only ensures parent is (un)prepared
22 * enable - clk_enable and clk_disable are functional & control gating
23 * rate - inherits rate from parent. No clk_set_rate support
24 * parent - fixed parent. No clk_set_parent support
34 unsigned int *share_count;
37 #define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw)
39 static int clk_gate2_enable(struct clk_hw *hw)
41 struct clk_gate2 *gate = to_clk_gate2(hw);
43 unsigned long flags = 0;
45 spin_lock_irqsave(gate->lock, flags);
47 if (gate->share_count && (*gate->share_count)++ > 0)
50 reg = readl(gate->reg);
51 reg &= ~(3 << gate->bit_idx);
52 reg |= gate->cgr_val << gate->bit_idx;
53 writel(reg, gate->reg);
56 spin_unlock_irqrestore(gate->lock, flags);
61 static void clk_gate2_disable(struct clk_hw *hw)
63 struct clk_gate2 *gate = to_clk_gate2(hw);
65 unsigned long flags = 0;
67 spin_lock_irqsave(gate->lock, flags);
69 if (gate->share_count) {
70 if (WARN_ON(*gate->share_count == 0))
72 else if (--(*gate->share_count) > 0)
76 reg = readl(gate->reg);
77 reg &= ~(3 << gate->bit_idx);
78 writel(reg, gate->reg);
81 spin_unlock_irqrestore(gate->lock, flags);
84 static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx)
88 if (((val >> bit_idx) & 1) == 1)
94 static int clk_gate2_is_enabled(struct clk_hw *hw)
96 struct clk_gate2 *gate = to_clk_gate2(hw);
98 return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
101 static void clk_gate2_disable_unused(struct clk_hw *hw)
103 struct clk_gate2 *gate = to_clk_gate2(hw);
104 unsigned long flags = 0;
107 spin_lock_irqsave(gate->lock, flags);
109 if (!gate->share_count || *gate->share_count == 0) {
110 reg = readl(gate->reg);
111 reg &= ~(3 << gate->bit_idx);
112 writel(reg, gate->reg);
115 spin_unlock_irqrestore(gate->lock, flags);
118 static const struct clk_ops clk_gate2_ops = {
119 .enable = clk_gate2_enable,
120 .disable = clk_gate2_disable,
121 .disable_unused = clk_gate2_disable_unused,
122 .is_enabled = clk_gate2_is_enabled,
125 struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
126 const char *parent_name, unsigned long flags,
127 void __iomem *reg, u8 bit_idx, u8 cgr_val,
128 u8 clk_gate2_flags, spinlock_t *lock,
129 unsigned int *share_count)
131 struct clk_gate2 *gate;
133 struct clk_init_data init;
136 gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL);
138 return ERR_PTR(-ENOMEM);
140 /* struct clk_gate2 assignments */
142 gate->bit_idx = bit_idx;
143 gate->cgr_val = cgr_val;
144 gate->flags = clk_gate2_flags;
146 gate->share_count = share_count;
149 init.ops = &clk_gate2_ops;
151 init.parent_names = parent_name ? &parent_name : NULL;
152 init.num_parents = parent_name ? 1 : 0;
154 gate->hw.init = &init;
157 ret = clk_hw_register(NULL, hw);