1 // SPDX-License-Identifier: GPL-2.0+
3 * Exynos PLL helper functions for clock drivers.
4 * Copyright (C) 2016 Samsung Electronics
5 * Thomas Abraham <thomas.ab@samsung.com>
12 #define PLL145X_MDIV_SHIFT 16
13 #define PLL145X_MDIV_MASK 0x3ff
14 #define PLL145X_PDIV_SHIFT 8
15 #define PLL145X_PDIV_MASK 0x3f
16 #define PLL145X_SDIV_SHIFT 0
17 #define PLL145X_SDIV_MASK 0x7
19 unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq)
21 unsigned long pll_con1 = readl(con1);
22 unsigned long mdiv, sdiv, pdiv;
23 uint64_t fvco = fin_freq;
25 mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
26 pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
27 sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
30 do_div(fvco, (pdiv << sdiv));
31 return (unsigned long)fvco;