drivers/clk/clk_zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * ZynqMP clock driver
   4  *
   5  * Copyright (C) 2016 Xilinx, Inc.
   6  */
   7
   8 #include <common.h>
   9 #include <log.h>
  10 #include <malloc.h>
  11 #include <dm/device_compat.h>
  12 #include <linux/bitops.h>
  13 #include <clk-uclass.h>
  14 #include <clk.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <dm.h>
  17 #include <linux/err.h>
  18
  19 static const resource_size_t zynqmp_crf_apb_clkc_base = 0xfd1a0020;
  20 static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
  21
  22 /* Full power domain clocks */
  23 #define CRF_APB_APLL_CTRL               (zynqmp_crf_apb_clkc_base + 0x00)
  24 #define CRF_APB_DPLL_CTRL               (zynqmp_crf_apb_clkc_base + 0x0c)
  25 #define CRF_APB_VPLL_CTRL               (zynqmp_crf_apb_clkc_base + 0x18)
  26 #define CRF_APB_PLL_STATUS              (zynqmp_crf_apb_clkc_base + 0x24)
  27 #define CRF_APB_APLL_TO_LPD_CTRL        (zynqmp_crf_apb_clkc_base + 0x28)
  28 #define CRF_APB_DPLL_TO_LPD_CTRL        (zynqmp_crf_apb_clkc_base + 0x2c)
  29 #define CRF_APB_VPLL_TO_LPD_CTRL        (zynqmp_crf_apb_clkc_base + 0x30)
  30 /* Peripheral clocks */
  31 #define CRF_APB_ACPU_CTRL               (zynqmp_crf_apb_clkc_base + 0x40)
  32 #define CRF_APB_DBG_TRACE_CTRL          (zynqmp_crf_apb_clkc_base + 0x44)
  33 #define CRF_APB_DBG_FPD_CTRL            (zynqmp_crf_apb_clkc_base + 0x48)
  34 #define CRF_APB_DP_VIDEO_REF_CTRL       (zynqmp_crf_apb_clkc_base + 0x50)
  35 #define CRF_APB_DP_AUDIO_REF_CTRL       (zynqmp_crf_apb_clkc_base + 0x54)
  36 #define CRF_APB_DP_STC_REF_CTRL         (zynqmp_crf_apb_clkc_base + 0x5c)
  37 #define CRF_APB_DDR_CTRL                (zynqmp_crf_apb_clkc_base + 0x60)
  38 #define CRF_APB_GPU_REF_CTRL            (zynqmp_crf_apb_clkc_base + 0x64)
  39 #define CRF_APB_SATA_REF_CTRL           (zynqmp_crf_apb_clkc_base + 0x80)
  40 #define CRF_APB_PCIE_REF_CTRL           (zynqmp_crf_apb_clkc_base + 0x94)
  41 #define CRF_APB_GDMA_REF_CTRL           (zynqmp_crf_apb_clkc_base + 0x98)
  42 #define CRF_APB_DPDMA_REF_CTRL          (zynqmp_crf_apb_clkc_base + 0x9c)
  43 #define CRF_APB_TOPSW_MAIN_CTRL         (zynqmp_crf_apb_clkc_base + 0xa0)
  44 #define CRF_APB_TOPSW_LSBUS_CTRL        (zynqmp_crf_apb_clkc_base + 0xa4)
  45 #define CRF_APB_GTGREF0_REF_CTRL        (zynqmp_crf_apb_clkc_base + 0xa8)
  46 #define CRF_APB_DBG_TSTMP_CTRL          (zynqmp_crf_apb_clkc_base + 0xd8)
  47
  48 /* Low power domain clocks */
  49 #define CRL_APB_IOPLL_CTRL              (zynqmp_crl_apb_clkc_base + 0x00)
  50 #define CRL_APB_RPLL_CTRL               (zynqmp_crl_apb_clkc_base + 0x10)
  51 #define CRL_APB_PLL_STATUS              (zynqmp_crl_apb_clkc_base + 0x20)
  52 #define CRL_APB_IOPLL_TO_FPD_CTRL       (zynqmp_crl_apb_clkc_base + 0x24)
  53 #define CRL_APB_RPLL_TO_FPD_CTRL        (zynqmp_crl_apb_clkc_base + 0x28)
  54 /* Peripheral clocks */
  55 #define CRL_APB_USB3_DUAL_REF_CTRL      (zynqmp_crl_apb_clkc_base + 0x2c)
  56 #define CRL_APB_GEM0_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x30)
  57 #define CRL_APB_GEM1_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x34)
  58 #define CRL_APB_GEM2_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x38)
  59 #define CRL_APB_GEM3_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x3c)
  60 #define CRL_APB_USB0_BUS_REF_CTRL       (zynqmp_crl_apb_clkc_base + 0x40)
  61 #define CRL_APB_USB1_BUS_REF_CTRL       (zynqmp_crl_apb_clkc_base + 0x44)
  62 #define CRL_APB_QSPI_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x48)
  63 #define CRL_APB_SDIO0_REF_CTRL          (zynqmp_crl_apb_clkc_base + 0x4c)
  64 #define CRL_APB_SDIO1_REF_CTRL          (zynqmp_crl_apb_clkc_base + 0x50)
  65 #define CRL_APB_UART0_REF_CTRL          (zynqmp_crl_apb_clkc_base + 0x54)
  66 #define CRL_APB_UART1_REF_CTRL          (zynqmp_crl_apb_clkc_base + 0x58)
  67 #define CRL_APB_SPI0_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x5c)
  68 #define CRL_APB_SPI1_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x60)
  69 #define CRL_APB_CAN0_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x64)
  70 #define CRL_APB_CAN1_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x68)
  71 #define CRL_APB_CPU_R5_CTRL             (zynqmp_crl_apb_clkc_base + 0x70)
  72 #define CRL_APB_IOU_SWITCH_CTRL         (zynqmp_crl_apb_clkc_base + 0x7c)
  73 #define CRL_APB_CSU_PLL_CTRL            (zynqmp_crl_apb_clkc_base + 0x80)
  74 #define CRL_APB_PCAP_CTRL               (zynqmp_crl_apb_clkc_base + 0x84)
  75 #define CRL_APB_LPD_SWITCH_CTRL         (zynqmp_crl_apb_clkc_base + 0x88)
  76 #define CRL_APB_LPD_LSBUS_CTRL          (zynqmp_crl_apb_clkc_base + 0x8c)
  77 #define CRL_APB_DBG_LPD_CTRL            (zynqmp_crl_apb_clkc_base + 0x90)
  78 #define CRL_APB_NAND_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x94)
  79 #define CRL_APB_ADMA_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x98)
  80 #define CRL_APB_PL0_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xa0)
  81 #define CRL_APB_PL1_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xa4)
  82 #define CRL_APB_PL2_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xa8)
  83 #define CRL_APB_PL3_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xac)
  84 #define CRL_APB_PL0_THR_CNT             (zynqmp_crl_apb_clkc_base + 0xb4)
  85 #define CRL_APB_PL1_THR_CNT             (zynqmp_crl_apb_clkc_base + 0xbc)
  86 #define CRL_APB_PL2_THR_CNT             (zynqmp_crl_apb_clkc_base + 0xc4)
  87 #define CRL_APB_PL3_THR_CNT             (zynqmp_crl_apb_clkc_base + 0xdc)
  88 #define CRL_APB_GEM_TSU_REF_CTRL        (zynqmp_crl_apb_clkc_base + 0xe0)
  89 #define CRL_APB_DLL_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xe4)
  90 #define CRL_APB_AMS_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xe8)
  91 #define CRL_APB_I2C0_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x100)
  92 #define CRL_APB_I2C1_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x104)
  93 #define CRL_APB_TIMESTAMP_REF_CTRL      (zynqmp_crl_apb_clkc_base + 0x108)
  94
  95 #define ZYNQ_CLK_MAXDIV         0x3f
  96 #define CLK_CTRL_DIV1_SHIFT     16
  97 #define CLK_CTRL_DIV1_MASK      (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
  98 #define CLK_CTRL_DIV0_SHIFT     8
  99 #define CLK_CTRL_DIV0_MASK      (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
 100 #define CLK_CTRL_SRCSEL_SHIFT   0
 101 #define CLK_CTRL_SRCSEL_MASK    (0x3 << CLK_CTRL_SRCSEL_SHIFT)
 102 #define PLLCTRL_FBDIV_MASK      0x7f00
 103 #define PLLCTRL_FBDIV_SHIFT     8
 104 #define PLLCTRL_RESET_MASK      1
 105 #define PLLCTRL_RESET_SHIFT     0
 106 #define PLLCTRL_BYPASS_MASK     0x8
 107 #define PLLCTRL_BYPASS_SHFT     3
 108 #define PLLCTRL_POST_SRC_SHFT   24
 109 #define PLLCTRL_POST_SRC_MASK   (0x7 << PLLCTRL_POST_SRC_SHFT)
 110 #define PLLCTRL_PRE_SRC_SHFT    20
 111 #define PLLCTRL_PRE_SRC_MASK    (0x7 << PLLCTRL_PRE_SRC_SHFT)
 112
 113
 114 #define NUM_MIO_PINS    77
 115
 116 enum zynqmp_clk {
 117         iopll, rpll,
 118         apll, dpll, vpll,
 119         iopll_to_fpd, rpll_to_fpd, apll_to_lpd, dpll_to_lpd, vpll_to_lpd,
 120         acpu, acpu_half,
 121         dbg_fpd, dbg_lpd, dbg_trace, dbg_tstmp,
 122         dp_video_ref, dp_audio_ref,
 123         dp_stc_ref, gdma_ref, dpdma_ref,
 124         ddr_ref, sata_ref, pcie_ref,
 125         gpu_ref, gpu_pp0_ref, gpu_pp1_ref,
 126         topsw_main, topsw_lsbus,
 127         gtgref0_ref,
 128         lpd_switch, lpd_lsbus,
 129         usb0_bus_ref, usb1_bus_ref, usb3_dual_ref, usb0, usb1,
 130         cpu_r5, cpu_r5_core,
 131         csu_spb, csu_pll, pcap,
 132         iou_switch,
 133         gem_tsu_ref, gem_tsu,
 134         gem0_ref, gem1_ref, gem2_ref, gem3_ref,
 135         gem0_rx, gem1_rx, gem2_rx, gem3_rx,
 136         qspi_ref,
 137         sdio0_ref, sdio1_ref,
 138         uart0_ref, uart1_ref,
 139         spi0_ref, spi1_ref,
 140         nand_ref,
 141         i2c0_ref, i2c1_ref, can0_ref, can1_ref, can0, can1,
 142         dll_ref,
 143         adma_ref,
 144         timestamp_ref,
 145         ams_ref,
 146         pl0, pl1, pl2, pl3,
 147         wdt,
 148         clk_max,
 149 };
 150
 151 static const char * const clk_names[clk_max] = {
 152         "iopll", "rpll", "apll", "dpll",
 153         "vpll", "iopll_to_fpd", "rpll_to_fpd",
 154         "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
 155         "acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
 156         "dbg_trace", "dbg_tstmp", "dp_video_ref",
 157         "dp_audio_ref", "dp_stc_ref", "gdma_ref",
 158         "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
 159         "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
 160         "topsw_main", "topsw_lsbus", "gtgref0_ref",
 161         "lpd_switch", "lpd_lsbus", "usb0_bus_ref",
 162         "usb1_bus_ref", "usb3_dual_ref", "usb0",
 163         "usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
 164         "csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
 165         "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
 166         "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
 167         "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
 168         "uart0_ref", "uart1_ref", "spi0_ref",
 169         "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
 170         "can0_ref", "can1_ref", "can0", "can1",
 171         "dll_ref", "adma_ref", "timestamp_ref",
 172         "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"
 173 };
 174
 175 struct zynqmp_clk_priv {
 176         unsigned long ps_clk_freq;
 177         unsigned long video_clk;
 178         unsigned long pss_alt_ref_clk;
 179         unsigned long gt_crx_ref_clk;
 180         unsigned long aux_ref_clk;
 181 };
 182
 183 static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
 184 {
 185         switch (id) {
 186         case iopll:
 187                 return CRL_APB_IOPLL_CTRL;
 188         case rpll:
 189                 return CRL_APB_RPLL_CTRL;
 190         case apll:
 191                 return CRF_APB_APLL_CTRL;
 192         case dpll:
 193                 return CRF_APB_DPLL_CTRL;
 194         case vpll:
 195                 return CRF_APB_VPLL_CTRL;
 196         case acpu:
 197                 return CRF_APB_ACPU_CTRL;
 198         case ddr_ref:
 199                 return CRF_APB_DDR_CTRL;
 200         case qspi_ref:
 201                 return CRL_APB_QSPI_REF_CTRL;
 202         case gem0_ref:
 203                 return CRL_APB_GEM0_REF_CTRL;
 204         case gem1_ref:
 205                 return CRL_APB_GEM1_REF_CTRL;
 206         case gem2_ref:
 207                 return CRL_APB_GEM2_REF_CTRL;
 208         case gem3_ref:
 209                 return CRL_APB_GEM3_REF_CTRL;
 210         case uart0_ref:
 211                 return CRL_APB_UART0_REF_CTRL;
 212         case uart1_ref:
 213                 return CRL_APB_UART1_REF_CTRL;
 214         case sdio0_ref:
 215                 return CRL_APB_SDIO0_REF_CTRL;
 216         case sdio1_ref:
 217                 return CRL_APB_SDIO1_REF_CTRL;
 218         case spi0_ref:
 219                 return CRL_APB_SPI0_REF_CTRL;
 220         case spi1_ref:
 221                 return CRL_APB_SPI1_REF_CTRL;
 222         case nand_ref:
 223                 return CRL_APB_NAND_REF_CTRL;
 224         case i2c0_ref:
 225                 return CRL_APB_I2C0_REF_CTRL;
 226         case i2c1_ref:
 227                 return CRL_APB_I2C1_REF_CTRL;
 228         case can0_ref:
 229                 return CRL_APB_CAN0_REF_CTRL;
 230         case can1_ref:
 231                 return CRL_APB_CAN1_REF_CTRL;
 232         case pl0:
 233                 return CRL_APB_PL0_REF_CTRL;
 234         case pl1:
 235                 return CRL_APB_PL1_REF_CTRL;
 236         case pl2:
 237                 return CRL_APB_PL2_REF_CTRL;
 238         case pl3:
 239                 return CRL_APB_PL3_REF_CTRL;
 240         case wdt:
 241                 return CRF_APB_TOPSW_LSBUS_CTRL;
 242         case iopll_to_fpd:
 243                 return CRL_APB_IOPLL_TO_FPD_CTRL;
 244         default:
 245                 debug("Invalid clk id%d\n", id);
 246         }
 247         return 0;
 248 }
 249
 250 static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl)
 251 {
 252         u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
 253                       CLK_CTRL_SRCSEL_SHIFT;
 254
 255         switch (srcsel) {
 256         case 2:
 257                 return dpll;
 258         case 3:
 259                 return vpll;
 260         case 0 ... 1:
 261         default:
 262                 return apll;
 263         }
 264 }
 265
 266 static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl)
 267 {
 268         u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
 269                       CLK_CTRL_SRCSEL_SHIFT;
 270
 271         switch (srcsel) {
 272         case 1:
 273                 return vpll;
 274         case 0:
 275         default:
 276                 return dpll;
 277         }
 278 }
 279
 280 static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl)
 281 {
 282         u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
 283                       CLK_CTRL_SRCSEL_SHIFT;
 284
 285         switch (srcsel) {
 286         case 2:
 287                 return rpll;
 288         case 3:
 289                 return dpll;
 290         case 0 ... 1:
 291         default:
 292                 return iopll;
 293         }
 294 }
 295
 296 static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl)
 297 {
 298         u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
 299                       CLK_CTRL_SRCSEL_SHIFT;
 300
 301         switch (srcsel) {
 302         case 2:
 303                 return iopll_to_fpd;
 304         case 3:
 305                 return dpll;
 306         case 0 ... 1:
 307         default:
 308                 return apll;
 309         }
 310 }
 311
 312 static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
 313                                     struct zynqmp_clk_priv *priv,
 314                                     bool is_pre_src)
 315 {
 316         u32 src_sel;
 317
 318         if (is_pre_src)
 319                 src_sel = (clk_ctrl & PLLCTRL_PRE_SRC_MASK) >>
 320                            PLLCTRL_PRE_SRC_SHFT;
 321         else
 322                 src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
 323                            PLLCTRL_POST_SRC_SHFT;
 324
 325         switch (src_sel) {
 326         case 4:
 327                 return priv->video_clk;
 328         case 5:
 329                 return priv->pss_alt_ref_clk;
 330         case 6:
 331                 return priv->aux_ref_clk;
 332         case 7:
 333                 return priv->gt_crx_ref_clk;
 334         case 0 ... 3:
 335         default:
 336         return priv->ps_clk_freq;
 337         }
 338 }
 339
 340 static ulong zynqmp_clk_get_pll_rate(struct zynqmp_clk_priv *priv,
 341                                      enum zynqmp_clk id)
 342 {
 343         u32 clk_ctrl, reset, mul;
 344         ulong freq;
 345         int ret;
 346
 347         ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
 348         if (ret) {
 349                 printf("%s mio read fail\n", __func__);
 350                 return -EIO;
 351         }
 352
 353         if (clk_ctrl & PLLCTRL_BYPASS_MASK)
 354                 freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 0);
 355         else
 356                 freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 1);
 357
 358         reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT;
 359         if (reset && !(clk_ctrl & PLLCTRL_BYPASS_MASK))
 360                 return 0;
 361
 362         mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
 363
 364         freq *= mul;
 365
 366         if (clk_ctrl & (1 << 16))
 367                 freq /= 2;
 368
 369         return freq;
 370 }
 371
 372 static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv,
 373                                      enum zynqmp_clk id)
 374 {
 375         u32 clk_ctrl, div;
 376         enum zynqmp_clk pll;
 377         int ret;
 378         unsigned long pllrate;
 379
 380         ret = zynqmp_mmio_read(CRF_APB_ACPU_CTRL, &clk_ctrl);
 381         if (ret) {
 382                 printf("%s mio read fail\n", __func__);
 383                 return -EIO;
 384         }
 385
 386         div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 387
 388         pll = zynqmp_clk_get_cpu_pll(clk_ctrl);
 389         pllrate = zynqmp_clk_get_pll_rate(priv, pll);
 390         if (IS_ERR_VALUE(pllrate))
 391                 return pllrate;
 392
 393         return DIV_ROUND_CLOSEST(pllrate, div);
 394 }
 395
 396 static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv)
 397 {
 398         u32 clk_ctrl, div;
 399         enum zynqmp_clk pll;
 400         int ret;
 401         ulong pllrate;
 402
 403         ret = zynqmp_mmio_read(CRF_APB_DDR_CTRL, &clk_ctrl);
 404         if (ret) {
 405                 printf("%s mio read fail\n", __func__);
 406                 return -EIO;
 407         }
 408
 409         div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 410
 411         pll = zynqmp_clk_get_ddr_pll(clk_ctrl);
 412         pllrate = zynqmp_clk_get_pll_rate(priv, pll);
 413         if (IS_ERR_VALUE(pllrate))
 414                 return pllrate;
 415
 416         return DIV_ROUND_CLOSEST(pllrate, div);
 417 }
 418
 419 static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
 420                                           enum zynqmp_clk id, bool two_divs)
 421 {
 422         enum zynqmp_clk pll;
 423         u32 clk_ctrl, div0;
 424         u32 div1 = 1;
 425         int ret;
 426         ulong pllrate;
 427
 428         ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
 429         if (ret) {
 430                 printf("%s mio read fail\n", __func__);
 431                 return -EIO;
 432         }
 433
 434         div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 435         if (!div0)
 436                 div0 = 1;
 437
 438         if (two_divs) {
 439                 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
 440                 if (!div1)
 441                         div1 = 1;
 442         }
 443
 444         pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
 445         pllrate = zynqmp_clk_get_pll_rate(priv, pll);
 446         if (IS_ERR_VALUE(pllrate))
 447                 return pllrate;
 448
 449         return
 450                 DIV_ROUND_CLOSEST(
 451                         DIV_ROUND_CLOSEST(pllrate, div0), div1);
 452 }
 453
 454 static ulong zynqmp_clk_get_wdt_rate(struct zynqmp_clk_priv *priv,
 455                                      enum zynqmp_clk id, bool two_divs)
 456 {
 457         enum zynqmp_clk pll;
 458         u32 clk_ctrl, div0;
 459         u32 div1 = 1;
 460         int ret;
 461         ulong pllrate;
 462
 463         ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
 464         if (ret) {
 465                 printf("%d %s mio read fail\n", __LINE__, __func__);
 466                 return -EIO;
 467         }
 468
 469         div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 470         if (!div0)
 471                 div0 = 1;
 472
 473         pll = zynqmp_clk_get_wdt_pll(clk_ctrl);
 474         if (two_divs) {
 475                 ret = zynqmp_mmio_read(zynqmp_clk_get_register(pll), &clk_ctrl);
 476                 if (ret) {
 477                         printf("%d %s mio read fail\n", __LINE__, __func__);
 478                         return -EIO;
 479                 }
 480                 div1 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 481                 if (!div1)
 482                         div1 = 1;
 483         }
 484
 485         if (pll == iopll_to_fpd)
 486                 pll = iopll;
 487
 488         pllrate = zynqmp_clk_get_pll_rate(priv, pll);
 489         if (IS_ERR_VALUE(pllrate))
 490                 return pllrate;
 491
 492         return
 493                 DIV_ROUND_CLOSEST(
 494                         DIV_ROUND_CLOSEST(pllrate, div0), div1);
 495 }
 496
 497 static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate,
 498                                                        ulong pll_rate,
 499                                                        u32 *div0, u32 *div1)
 500 {
 501         long new_err, best_err = (long)(~0UL >> 1);
 502         ulong new_rate, best_rate = 0;
 503         u32 d0, d1;
 504
 505         for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
 506                 for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
 507                         new_rate = DIV_ROUND_CLOSEST(
 508                                         DIV_ROUND_CLOSEST(pll_rate, d0), d1);
 509                         new_err = abs(new_rate - rate);
 510
 511                         if (new_err < best_err) {
 512                                 *div0 = d0;
 513                                 *div1 = d1;
 514                                 best_err = new_err;
 515                                 best_rate = new_rate;
 516                         }
 517                 }
 518         }
 519
 520         return best_rate;
 521 }
 522
 523 static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv,
 524                                           enum zynqmp_clk id, ulong rate,
 525                                           bool two_divs)
 526 {
 527         enum zynqmp_clk pll;
 528         u32 clk_ctrl, div0 = 0, div1 = 0;
 529         ulong pll_rate, new_rate;
 530         u32 reg;
 531         int ret;
 532         u32 mask;
 533
 534         reg = zynqmp_clk_get_register(id);
 535         ret = zynqmp_mmio_read(reg, &clk_ctrl);
 536         if (ret) {
 537                 printf("%s mio read fail\n", __func__);
 538                 return -EIO;
 539         }
 540
 541         pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
 542         pll_rate = zynqmp_clk_get_pll_rate(priv, pll);
 543         if (IS_ERR_VALUE(pll_rate))
 544                 return pll_rate;
 545
 546         clk_ctrl &= ~CLK_CTRL_DIV0_MASK;
 547         if (two_divs) {
 548                 clk_ctrl &= ~CLK_CTRL_DIV1_MASK;
 549                 new_rate = zynqmp_clk_calc_peripheral_two_divs(rate, pll_rate,
 550                                 &div0, &div1);
 551                 clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
 552         } else {
 553                 div0 = DIV_ROUND_CLOSEST(pll_rate, rate);
 554                 if (div0 > ZYNQ_CLK_MAXDIV)
 555                         div0 = ZYNQ_CLK_MAXDIV;
 556                 new_rate = DIV_ROUND_CLOSEST(rate, div0);
 557         }
 558         clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
 559
 560         mask = (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) |
 561                (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT);
 562
 563         ret = zynqmp_mmio_write(reg, mask, clk_ctrl);
 564         if (ret) {
 565                 printf("%s mio write fail\n", __func__);
 566                 return -EIO;
 567         }
 568
 569         return new_rate;
 570 }
 571
 572 static ulong zynqmp_clk_get_rate(struct clk *clk)
 573 {
 574         struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
 575         enum zynqmp_clk id = clk->id;
 576         bool two_divs = false;
 577
 578         switch (id) {
 579         case iopll ... vpll:
 580                 return zynqmp_clk_get_pll_rate(priv, id);
 581         case acpu:
 582                 return zynqmp_clk_get_cpu_rate(priv, id);
 583         case ddr_ref:
 584                 return zynqmp_clk_get_ddr_rate(priv);
 585         case gem0_ref ... gem3_ref:
 586         case qspi_ref ... can1_ref:
 587         case pl0 ... pl3:
 588                 two_divs = true;
 589                 return zynqmp_clk_get_peripheral_rate(priv, id, two_divs);
 590         case wdt:
 591                 two_divs = true;
 592                 return zynqmp_clk_get_wdt_rate(priv, id, two_divs);
 593         default:
 594                 return -ENXIO;
 595         }
 596 }
 597
 598 static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
 599 {
 600         struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
 601         enum zynqmp_clk id = clk->id;
 602         bool two_divs = true;
 603
 604         switch (id) {
 605         case gem0_ref ... gem3_ref:
 606         case qspi_ref ... can1_ref:
 607                 return zynqmp_clk_set_peripheral_rate(priv, id,
 608                                                       rate, two_divs);
 609         default:
 610                 return -ENXIO;
 611         }
 612 }
 613
 614 int soc_clk_dump(void)
 615 {
 616         struct udevice *dev;
 617         int i, ret;
 618
 619         ret = uclass_get_device_by_driver(UCLASS_CLK,
 620                 DM_GET_DRIVER(zynqmp_clk), &dev);
 621         if (ret)
 622                 return ret;
 623
 624         printf("clk\t\tfrequency\n");
 625         for (i = 0; i < clk_max; i++) {
 626                 const char *name = clk_names[i];
 627                 if (name) {
 628                         struct clk clk;
 629                         unsigned long rate;
 630
 631                         clk.id = i;
 632                         ret = clk_request(dev, &clk);
 633                         if (ret < 0)
 634                                 return ret;
 635
 636                         rate = clk_get_rate(&clk);
 637
 638                         clk_free(&clk);
 639
 640                         if ((rate == (unsigned long)-ENOSYS) ||
 641                             (rate == (unsigned long)-ENXIO) ||
 642                             (rate == (unsigned long)-EIO))
 643                                 printf("%10s%20s\n", name, "unknown");
 644                         else
 645                                 printf("%10s%20lu\n", name, rate);
 646                 }
 647         }
 648
 649         return 0;
 650 }
 651
 652 static int zynqmp_get_freq_by_name(char *name, struct udevice *dev, ulong *freq)
 653 {
 654         struct clk clk;
 655         int ret;
 656
 657         ret = clk_get_by_name(dev, name, &clk);
 658         if (ret < 0) {
 659                 dev_err(dev, "failed to get %s\n", name);
 660                 return ret;
 661         }
 662
 663         *freq = clk_get_rate(&clk);
 664         if (IS_ERR_VALUE(*freq)) {
 665                 dev_err(dev, "failed to get rate %s\n", name);
 666                 return -EINVAL;
 667         }
 668
 669         return 0;
 670 }
 671 static int zynqmp_clk_probe(struct udevice *dev)
 672 {
 673         int ret;
 674         struct zynqmp_clk_priv *priv = dev_get_priv(dev);
 675
 676         debug("%s\n", __func__);
 677         ret = zynqmp_get_freq_by_name("pss_ref_clk", dev, &priv->ps_clk_freq);
 678         if (ret < 0)
 679                 return -EINVAL;
 680
 681         ret = zynqmp_get_freq_by_name("video_clk", dev, &priv->video_clk);
 682         if (ret < 0)
 683                 return -EINVAL;
 684
 685         ret = zynqmp_get_freq_by_name("pss_alt_ref_clk", dev,
 686                                       &priv->pss_alt_ref_clk);
 687         if (ret < 0)
 688                 return -EINVAL;
 689
 690         ret = zynqmp_get_freq_by_name("aux_ref_clk", dev, &priv->aux_ref_clk);
 691         if (ret < 0)
 692                 return -EINVAL;
 693
 694         ret = zynqmp_get_freq_by_name("gt_crx_ref_clk", dev,
 695                                       &priv->gt_crx_ref_clk);
 696         if (ret < 0)
 697                 return -EINVAL;
 698
 699         return 0;
 700 }
 701
 702 static struct clk_ops zynqmp_clk_ops = {
 703         .set_rate = zynqmp_clk_set_rate,
 704         .get_rate = zynqmp_clk_get_rate,
 705 };
 706
 707 static const struct udevice_id zynqmp_clk_ids[] = {
 708         { .compatible = "xlnx,zynqmp-clk" },
 709         { }
 710 };
 711
 712 U_BOOT_DRIVER(zynqmp_clk) = {
 713         .name = "zynqmp_clk",
 714         .id = UCLASS_CLK,
 715         .of_match = zynqmp_clk_ids,
 716         .probe = zynqmp_clk_probe,
 717         .ops = &zynqmp_clk_ops,
 718         .priv_auto      = sizeof(struct zynqmp_clk_priv),
 719 };