1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2019 Xilinx, Inc.
4 * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
10 #include <asm/ptrace.h>
11 #include <dm/device_compat.h>
12 #include <linux/bitops.h>
13 #include <linux/bitfield.h>
15 #include <clk-uclass.h>
18 #include <asm/arch/sys_proto.h>
19 #include <zynqmp_firmware.h>
20 #include <linux/err.h>
22 #define MAX_PARENT 100
24 #define MAX_NAME_LEN 50
26 #define CLK_TYPE_SHIFT 2
28 #define PM_API_PAYLOAD_LEN 3
30 #define NA_PARENT 0xFFFFFFFF
31 #define DUMMY_PARENT 0xFFFFFFFE
33 #define CLK_TYPE_FIELD_LEN 4
34 #define CLK_TOPOLOGY_NODE_OFFSET 16
35 #define NODES_PER_RESP 3
37 #define CLK_TYPE_FIELD_MASK 0xF
38 #define CLK_FLAG_FIELD_MASK GENMASK(21, 8)
39 #define CLK_TYPE_FLAG_FIELD_MASK GENMASK(31, 24)
40 #define CLK_TYPE_FLAG2_FIELD_MASK GENMASK(7, 4)
41 #define CLK_TYPE_FLAG_BITS 8
43 #define CLK_PARENTS_ID_LEN 16
44 #define CLK_PARENTS_ID_MASK 0xFFFF
46 #define END_OF_TOPOLOGY_NODE 1
47 #define END_OF_PARENTS 1
49 #define CLK_VALID_MASK 0x1
50 #define NODE_CLASS_SHIFT 26U
51 #define NODE_SUBCLASS_SHIFT 20U
52 #define NODE_TYPE_SHIFT 14U
53 #define NODE_INDEX_SHIFT 0U
55 #define CLK_GET_NAME_RESP_LEN 16
56 #define CLK_GET_TOPOLOGY_RESP_WORDS 3
57 #define CLK_GET_PARENTS_RESP_WORDS 3
58 #define CLK_GET_ATTR_RESP_WORDS 1
60 #define NODE_SUBCLASS_CLOCK_PLL 1
61 #define NODE_SUBCLASS_CLOCK_OUT 2
62 #define NODE_SUBCLASS_CLOCK_REF 3
64 #define NODE_CLASS_CLOCK 2
65 #define NODE_CLASS_MASK 0x3F
67 #define CLOCK_NODE_TYPE_MUX 1
68 #define CLOCK_NODE_TYPE_DIV 4
69 #define CLOCK_NODE_TYPE_GATE 6
73 PM_QID_CLOCK_GET_NAME,
74 PM_QID_CLOCK_GET_TOPOLOGY,
75 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
76 PM_QID_CLOCK_GET_PARENTS,
77 PM_QID_CLOCK_GET_ATTRIBUTES,
78 PM_QID_PINCTRL_GET_NUM_PINS,
79 PM_QID_PINCTRL_GET_NUM_FUNCTIONS,
80 PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
81 PM_QID_PINCTRL_GET_FUNCTION_NAME,
82 PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
83 PM_QID_PINCTRL_GET_PIN_GROUPS,
84 PM_QID_CLOCK_GET_NUM_CLOCKS,
85 PM_QID_CLOCK_GET_MAX_DIVISOR,
94 char name[MAX_NAME_LEN];
99 struct clock_topology {
105 struct versal_clock {
106 char clk_name[MAX_NAME_LEN];
109 struct clock_topology node[MAX_NODES];
111 struct clock_parent parent[MAX_PARENT];
116 struct versal_clk_priv {
117 struct versal_clock *clk;
120 static ulong pl_alt_ref_clk;
121 static ulong ref_clk;
123 struct versal_pm_query_data {
130 static struct versal_clock *clock;
131 static unsigned int clock_max_idx;
133 #define PM_QUERY_DATA 35
135 static int versal_pm_query(struct versal_pm_query_data qdata, u32 *ret_payload)
139 regs.regs[0] = PM_SIP_SVC | PM_QUERY_DATA;
140 regs.regs[1] = ((u64)qdata.arg1 << 32) | qdata.qid;
141 regs.regs[2] = ((u64)qdata.arg3 << 32) | qdata.arg2;
146 ret_payload[0] = (u32)regs.regs[0];
147 ret_payload[1] = upper_32_bits(regs.regs[0]);
148 ret_payload[2] = (u32)regs.regs[1];
149 ret_payload[3] = upper_32_bits(regs.regs[1]);
150 ret_payload[4] = (u32)regs.regs[2];
153 return qdata.qid == PM_QID_CLOCK_GET_NAME ? 0 : regs.regs[0];
156 static inline int versal_is_valid_clock(u32 clk_id)
158 if (clk_id >= clock_max_idx)
161 return clock[clk_id].valid;
164 static int versal_get_clock_name(u32 clk_id, char *clk_name)
168 ret = versal_is_valid_clock(clk_id);
170 strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN);
174 return ret == 0 ? -EINVAL : ret;
177 static int versal_get_clock_type(u32 clk_id, u32 *type)
181 ret = versal_is_valid_clock(clk_id);
183 *type = clock[clk_id].type;
187 return ret == 0 ? -EINVAL : ret;
190 static int versal_pm_clock_get_num_clocks(u32 *nclocks)
192 struct versal_pm_query_data qdata = {0};
193 u32 ret_payload[PAYLOAD_ARG_CNT];
196 qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS;
198 ret = versal_pm_query(qdata, ret_payload);
199 *nclocks = ret_payload[1];
204 static int versal_pm_clock_get_name(u32 clock_id, char *name)
206 struct versal_pm_query_data qdata = {0};
207 u32 ret_payload[PAYLOAD_ARG_CNT];
210 qdata.qid = PM_QID_CLOCK_GET_NAME;
211 qdata.arg1 = clock_id;
213 ret = versal_pm_query(qdata, ret_payload);
216 memcpy(name, ret_payload, CLK_GET_NAME_RESP_LEN);
221 static int versal_pm_clock_get_topology(u32 clock_id, u32 index, u32 *topology)
223 struct versal_pm_query_data qdata = {0};
224 u32 ret_payload[PAYLOAD_ARG_CNT];
227 qdata.qid = PM_QID_CLOCK_GET_TOPOLOGY;
228 qdata.arg1 = clock_id;
231 ret = versal_pm_query(qdata, ret_payload);
232 memcpy(topology, &ret_payload[1], CLK_GET_TOPOLOGY_RESP_WORDS * 4);
237 static int versal_pm_clock_get_parents(u32 clock_id, u32 index, u32 *parents)
239 struct versal_pm_query_data qdata = {0};
240 u32 ret_payload[PAYLOAD_ARG_CNT];
243 qdata.qid = PM_QID_CLOCK_GET_PARENTS;
244 qdata.arg1 = clock_id;
247 ret = versal_pm_query(qdata, ret_payload);
248 memcpy(parents, &ret_payload[1], CLK_GET_PARENTS_RESP_WORDS * 4);
253 static int versal_pm_clock_get_attributes(u32 clock_id, u32 *attr)
255 struct versal_pm_query_data qdata = {0};
256 u32 ret_payload[PAYLOAD_ARG_CNT];
259 qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES;
260 qdata.arg1 = clock_id;
262 ret = versal_pm_query(qdata, ret_payload);
263 memcpy(attr, &ret_payload[1], CLK_GET_ATTR_RESP_WORDS * 4);
268 static int __versal_clock_get_topology(struct clock_topology *topology,
269 u32 *data, u32 *nnodes)
273 for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
274 if (!(data[i] & CLK_TYPE_FIELD_MASK))
275 return END_OF_TOPOLOGY_NODE;
276 topology[*nnodes].type = data[i] & CLK_TYPE_FIELD_MASK;
277 topology[*nnodes].flag = FIELD_GET(CLK_FLAG_FIELD_MASK,
279 topology[*nnodes].type_flag =
280 FIELD_GET(CLK_TYPE_FLAG_FIELD_MASK, data[i]);
281 topology[*nnodes].type_flag |=
282 FIELD_GET(CLK_TYPE_FLAG2_FIELD_MASK, data[i]) <<
284 debug("topology type:0x%x, flag:0x%x, type_flag:0x%x\n",
285 topology[*nnodes].type, topology[*nnodes].flag,
286 topology[*nnodes].type_flag);
293 static int versal_clock_get_topology(u32 clk_id,
294 struct clock_topology *topology,
298 u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
301 for (j = 0; j <= MAX_NODES; j += 3) {
302 ret = versal_pm_clock_get_topology(clock[clk_id].clk_id, j,
306 ret = __versal_clock_get_topology(topology, pm_resp, num_nodes);
307 if (ret == END_OF_TOPOLOGY_NODE)
314 static int __versal_clock_get_parents(struct clock_parent *parents, u32 *data,
318 struct clock_parent *parent;
320 for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
321 if (data[i] == NA_PARENT)
322 return END_OF_PARENTS;
324 parent = &parents[i];
325 parent->id = data[i] & CLK_PARENTS_ID_MASK;
326 if (data[i] == DUMMY_PARENT) {
327 strcpy(parent->name, "dummy_name");
330 parent->flag = data[i] >> CLK_PARENTS_ID_LEN;
331 if (versal_get_clock_name(parent->id, parent->name))
334 debug("parent name:%s\n", parent->name);
341 static int versal_clock_get_parents(u32 clk_id, struct clock_parent *parents,
345 u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
349 /* Get parents from firmware */
350 ret = versal_pm_clock_get_parents(clock[clk_id].clk_id, j,
355 ret = __versal_clock_get_parents(&parents[j], pm_resp,
357 if (ret == END_OF_PARENTS)
359 j += PM_API_PAYLOAD_LEN;
360 } while (*num_parents <= MAX_PARENT);
365 static u32 versal_clock_get_div(u32 clk_id)
367 u32 ret_payload[PAYLOAD_ARG_CNT];
370 xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
371 div = ret_payload[1];
376 static u32 versal_clock_set_div(u32 clk_id, u32 div)
378 u32 ret_payload[PAYLOAD_ARG_CNT];
380 xilinx_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
385 static u64 versal_clock_ref(u32 clk_id)
387 u32 ret_payload[PAYLOAD_ARG_CNT];
390 xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
391 ref = ret_payload[0];
395 return pl_alt_ref_clk;
399 static u64 versal_clock_get_pll_rate(u32 clk_id)
401 u32 ret_payload[PAYLOAD_ARG_CNT];
406 u32 parent_rate, parent_id;
407 u32 id = clk_id & 0xFFF;
409 xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
410 res = ret_payload[1];
412 printf("0%x PLL not enabled\n", clk_id);
416 parent_id = clock[clock[id].parent[0].id].clk_id;
417 parent_rate = versal_clock_ref(parent_id);
419 xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
420 fbdiv = ret_payload[1];
421 xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
422 frac = ret_payload[1];
424 freq = (fbdiv * parent_rate) >> (1 << frac);
429 static u32 versal_clock_mux(u32 clk_id)
432 u32 id = clk_id & 0xFFF;
434 for (i = 0; i < clock[id].num_nodes; i++)
435 if (clock[id].node[i].type == CLOCK_NODE_TYPE_MUX)
441 static u32 versal_clock_get_parentid(u32 clk_id)
444 u32 ret_payload[PAYLOAD_ARG_CNT];
445 u32 id = clk_id & 0xFFF;
447 if (versal_clock_mux(clk_id)) {
448 xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
450 parent_id = ret_payload[1];
453 debug("parent_id:0x%x\n", clock[clock[id].parent[parent_id].id].clk_id);
454 return clock[clock[id].parent[parent_id].id].clk_id;
457 static u32 versal_clock_gate(u32 clk_id)
459 u32 id = clk_id & 0xFFF;
462 for (i = 0; i < clock[id].num_nodes; i++)
463 if (clock[id].node[i].type == CLOCK_NODE_TYPE_GATE)
469 static u32 versal_clock_div(u32 clk_id)
472 u32 id = clk_id & 0xFFF;
474 for (i = 0; i < clock[id].num_nodes; i++)
475 if (clock[id].node[i].type == CLOCK_NODE_TYPE_DIV)
481 static u32 versal_clock_pll(u32 clk_id, u64 *clk_rate)
483 if (((clk_id >> NODE_SUBCLASS_SHIFT) & NODE_CLASS_MASK) ==
484 NODE_SUBCLASS_CLOCK_PLL &&
485 ((clk_id >> NODE_CLASS_SHIFT) & NODE_CLASS_MASK) ==
487 *clk_rate = versal_clock_get_pll_rate(clk_id);
494 static u64 versal_clock_calc(u32 clk_id)
500 if (versal_clock_pll(clk_id, &clk_rate))
503 parent_id = versal_clock_get_parentid(clk_id);
504 if (((parent_id >> NODE_SUBCLASS_SHIFT) &
505 NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
506 return versal_clock_ref(clk_id);
511 clk_rate = versal_clock_calc(parent_id);
513 if (versal_clock_div(clk_id)) {
514 div = versal_clock_get_div(clk_id);
515 clk_rate = DIV_ROUND_CLOSEST(clk_rate, div);
521 static int versal_clock_get_rate(u32 clk_id, u64 *clk_rate)
523 if (((clk_id >> NODE_SUBCLASS_SHIFT) &
524 NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
525 *clk_rate = versal_clock_ref(clk_id);
527 if (versal_clock_pll(clk_id, clk_rate))
530 if (((clk_id >> NODE_SUBCLASS_SHIFT) &
531 NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_OUT &&
532 ((clk_id >> NODE_CLASS_SHIFT) &
533 NODE_CLASS_MASK) == NODE_CLASS_CLOCK) {
534 if (!versal_clock_gate(clk_id) && !versal_clock_mux(clk_id))
536 *clk_rate = versal_clock_calc(clk_id);
543 int soc_clk_dump(void)
546 u32 type, ret, i = 0;
548 printf("\n ****** VERSAL CLOCKS *****\n");
550 printf("pl_alt_ref_clk:%ld ref_clk:%ld\n", pl_alt_ref_clk, ref_clk);
551 for (i = 0; i < clock_max_idx; i++) {
552 debug("%s\n", clock[i].clk_name);
553 ret = versal_get_clock_type(i, &type);
554 if (ret || type != CLK_TYPE_OUTPUT)
557 ret = versal_clock_get_rate(clock[i].clk_id, &clk_rate);
560 printf("clk: %s freq:%lld\n",
561 clock[i].clk_name, clk_rate);
567 static void versal_get_clock_info(void)
570 u32 attr, type = 0, nodetype, subclass, class;
572 for (i = 0; i < clock_max_idx; i++) {
573 ret = versal_pm_clock_get_attributes(i, &attr);
577 clock[i].valid = attr & CLK_VALID_MASK;
579 /* skip query for Invalid clock */
580 ret = versal_is_valid_clock(i);
581 if (ret != CLK_VALID_MASK)
584 clock[i].type = ((attr >> CLK_TYPE_SHIFT) & 0x1) ?
585 CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT;
586 nodetype = (attr >> NODE_TYPE_SHIFT) & NODE_CLASS_MASK;
587 subclass = (attr >> NODE_SUBCLASS_SHIFT) & NODE_CLASS_MASK;
588 class = (attr >> NODE_CLASS_SHIFT) & NODE_CLASS_MASK;
590 clock[i].clk_id = (class << NODE_CLASS_SHIFT) |
591 (subclass << NODE_SUBCLASS_SHIFT) |
592 (nodetype << NODE_TYPE_SHIFT) |
593 (i << NODE_INDEX_SHIFT);
595 ret = versal_pm_clock_get_name(clock[i].clk_id,
599 debug("clk name:%s, Valid:%d, type:%d, clk_id:0x%x\n",
600 clock[i].clk_name, clock[i].valid,
601 clock[i].type, clock[i].clk_id);
604 /* Get topology of all clock */
605 for (i = 0; i < clock_max_idx; i++) {
606 ret = versal_get_clock_type(i, &type);
607 if (ret || type != CLK_TYPE_OUTPUT)
609 debug("clk name:%s\n", clock[i].clk_name);
610 ret = versal_clock_get_topology(i, clock[i].node,
611 &clock[i].num_nodes);
615 ret = versal_clock_get_parents(i, clock[i].parent,
616 &clock[i].num_parents);
622 int versal_clock_setup(void)
626 ret = versal_pm_clock_get_num_clocks(&clock_max_idx);
630 debug("%s, clock_max_idx:0x%x\n", __func__, clock_max_idx);
631 clock = calloc(clock_max_idx, sizeof(*clock));
635 versal_get_clock_info();
640 static int versal_clock_get_freq_by_name(char *name, struct udevice *dev,
646 ret = clk_get_by_name(dev, name, &clk);
648 dev_err(dev, "failed to get %s\n", name);
652 *freq = clk_get_rate(&clk);
653 if (IS_ERR_VALUE(*freq)) {
654 dev_err(dev, "failed to get rate %s\n", name);
661 static int versal_clk_probe(struct udevice *dev)
664 struct versal_clk_priv *priv = dev_get_priv(dev);
666 debug("%s\n", __func__);
668 ret = versal_clock_get_freq_by_name("pl_alt_ref_clk",
669 dev, &pl_alt_ref_clk);
673 ret = versal_clock_get_freq_by_name("ref_clk", dev, &ref_clk);
677 versal_clock_setup();
684 static ulong versal_clk_get_rate(struct clk *clk)
686 struct versal_clk_priv *priv = dev_get_priv(clk->dev);
691 debug("%s\n", __func__);
693 clk_id = priv->clk[id].clk_id;
695 versal_clock_get_rate(clk_id, &clk_rate);
700 static ulong versal_clk_set_rate(struct clk *clk, ulong rate)
702 struct versal_clk_priv *priv = dev_get_priv(clk->dev);
709 debug("%s\n", __func__);
711 clk_id = priv->clk[id].clk_id;
713 ret = versal_clock_get_rate(clk_id, &clk_rate);
715 printf("Clock is not a Gate:0x%x\n", clk_id);
720 if (versal_clock_div(clk_id)) {
721 div = versal_clock_get_div(clk_id);
723 div = DIV_ROUND_CLOSEST(clk_rate, rate);
724 versal_clock_set_div(clk_id, div);
725 debug("%s, div:%d, newrate:%lld\n", __func__,
726 div, DIV_ROUND_CLOSEST(clk_rate, div));
727 return DIV_ROUND_CLOSEST(clk_rate, div);
729 clk_id = versal_clock_get_parentid(clk_id);
730 } while (((clk_id >> NODE_SUBCLASS_SHIFT) &
731 NODE_CLASS_MASK) != NODE_SUBCLASS_CLOCK_REF);
733 printf("Clock didn't has Divisors:0x%x\n", priv->clk[id].clk_id);
738 static struct clk_ops versal_clk_ops = {
739 .set_rate = versal_clk_set_rate,
740 .get_rate = versal_clk_get_rate,
743 static const struct udevice_id versal_clk_ids[] = {
744 { .compatible = "xlnx,versal-clk" },
748 U_BOOT_DRIVER(versal_clk) = {
749 .name = "versal-clk",
751 .of_match = versal_clk_ids,
752 .probe = versal_clk_probe,
753 .ops = &versal_clk_ops,
754 .priv_auto_alloc_size = sizeof(struct versal_clk_priv),