drivers/clk/clk_stm32mp1.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #define LOG_CATEGORY UCLASS_CLK
   7
   8 #include <common.h>
   9 #include <clk-uclass.h>
  10 #include <div64.h>
  11 #include <dm.h>
  12 #include <init.h>
  13 #include <log.h>
  14 #include <regmap.h>
  15 #include <spl.h>
  16 #include <syscon.h>
  17 #include <time.h>
  18 #include <vsprintf.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <dm/device_compat.h>
  21 #include <dt-bindings/clock/stm32mp1-clks.h>
  22 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  23 #include <linux/bitops.h>
  24 #include <linux/io.h>
  25 #include <linux/iopoll.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifndef CONFIG_TFABOOT
  30 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  31 /* activate clock tree initialization in the driver */
  32 #define STM32MP1_CLOCK_TREE_INIT
  33 #endif
  34 #endif
  35
  36 #define MAX_HSI_HZ              64000000
  37
  38 /* TIMEOUT */
  39 #define TIMEOUT_200MS           200000
  40 #define TIMEOUT_1S              1000000
  41
  42 /* STGEN registers */
  43 #define STGENC_CNTCR            0x00
  44 #define STGENC_CNTSR            0x04
  45 #define STGENC_CNTCVL           0x08
  46 #define STGENC_CNTCVU           0x0C
  47 #define STGENC_CNTFID0          0x20
  48
  49 #define STGENC_CNTCR_EN         BIT(0)
  50
  51 /* RCC registers */
  52 #define RCC_OCENSETR            0x0C
  53 #define RCC_OCENCLRR            0x10
  54 #define RCC_HSICFGR             0x18
  55 #define RCC_MPCKSELR            0x20
  56 #define RCC_ASSCKSELR           0x24
  57 #define RCC_RCK12SELR           0x28
  58 #define RCC_MPCKDIVR            0x2C
  59 #define RCC_AXIDIVR             0x30
  60 #define RCC_APB4DIVR            0x3C
  61 #define RCC_APB5DIVR            0x40
  62 #define RCC_RTCDIVR             0x44
  63 #define RCC_MSSCKSELR           0x48
  64 #define RCC_PLL1CR              0x80
  65 #define RCC_PLL1CFGR1           0x84
  66 #define RCC_PLL1CFGR2           0x88
  67 #define RCC_PLL1FRACR           0x8C
  68 #define RCC_PLL1CSGR            0x90
  69 #define RCC_PLL2CR              0x94
  70 #define RCC_PLL2CFGR1           0x98
  71 #define RCC_PLL2CFGR2           0x9C
  72 #define RCC_PLL2FRACR           0xA0
  73 #define RCC_PLL2CSGR            0xA4
  74 #define RCC_I2C46CKSELR         0xC0
  75 #define RCC_CPERCKSELR          0xD0
  76 #define RCC_STGENCKSELR         0xD4
  77 #define RCC_DDRITFCR            0xD8
  78 #define RCC_BDCR                0x140
  79 #define RCC_RDLSICR             0x144
  80 #define RCC_MP_APB4ENSETR       0x200
  81 #define RCC_MP_APB5ENSETR       0x208
  82 #define RCC_MP_AHB5ENSETR       0x210
  83 #define RCC_MP_AHB6ENSETR       0x218
  84 #define RCC_OCRDYR              0x808
  85 #define RCC_DBGCFGR             0x80C
  86 #define RCC_RCK3SELR            0x820
  87 #define RCC_RCK4SELR            0x824
  88 #define RCC_MCUDIVR             0x830
  89 #define RCC_APB1DIVR            0x834
  90 #define RCC_APB2DIVR            0x838
  91 #define RCC_APB3DIVR            0x83C
  92 #define RCC_PLL3CR              0x880
  93 #define RCC_PLL3CFGR1           0x884
  94 #define RCC_PLL3CFGR2           0x888
  95 #define RCC_PLL3FRACR           0x88C
  96 #define RCC_PLL3CSGR            0x890
  97 #define RCC_PLL4CR              0x894
  98 #define RCC_PLL4CFGR1           0x898
  99 #define RCC_PLL4CFGR2           0x89C
 100 #define RCC_PLL4FRACR           0x8A0
 101 #define RCC_PLL4CSGR            0x8A4
 102 #define RCC_I2C12CKSELR         0x8C0
 103 #define RCC_I2C35CKSELR         0x8C4
 104 #define RCC_SPI2S1CKSELR        0x8D8
 105 #define RCC_SPI45CKSELR         0x8E0
 106 #define RCC_UART6CKSELR         0x8E4
 107 #define RCC_UART24CKSELR        0x8E8
 108 #define RCC_UART35CKSELR        0x8EC
 109 #define RCC_UART78CKSELR        0x8F0
 110 #define RCC_SDMMC12CKSELR       0x8F4
 111 #define RCC_SDMMC3CKSELR        0x8F8
 112 #define RCC_ETHCKSELR           0x8FC
 113 #define RCC_QSPICKSELR          0x900
 114 #define RCC_FMCCKSELR           0x904
 115 #define RCC_USBCKSELR           0x91C
 116 #define RCC_DSICKSELR           0x924
 117 #define RCC_ADCCKSELR           0x928
 118 #define RCC_MP_APB1ENSETR       0xA00
 119 #define RCC_MP_APB2ENSETR       0XA08
 120 #define RCC_MP_APB3ENSETR       0xA10
 121 #define RCC_MP_AHB2ENSETR       0xA18
 122 #define RCC_MP_AHB3ENSETR       0xA20
 123 #define RCC_MP_AHB4ENSETR       0xA28
 124
 125 /* used for most of SELR register */
 126 #define RCC_SELR_SRC_MASK       GENMASK(2, 0)
 127 #define RCC_SELR_SRCRDY         BIT(31)
 128
 129 /* Values of RCC_MPCKSELR register */
 130 #define RCC_MPCKSELR_HSI        0
 131 #define RCC_MPCKSELR_HSE        1
 132 #define RCC_MPCKSELR_PLL        2
 133 #define RCC_MPCKSELR_PLL_MPUDIV 3
 134
 135 /* Values of RCC_ASSCKSELR register */
 136 #define RCC_ASSCKSELR_HSI       0
 137 #define RCC_ASSCKSELR_HSE       1
 138 #define RCC_ASSCKSELR_PLL       2
 139
 140 /* Values of RCC_MSSCKSELR register */
 141 #define RCC_MSSCKSELR_HSI       0
 142 #define RCC_MSSCKSELR_HSE       1
 143 #define RCC_MSSCKSELR_CSI       2
 144 #define RCC_MSSCKSELR_PLL       3
 145
 146 /* Values of RCC_CPERCKSELR register */
 147 #define RCC_CPERCKSELR_HSI      0
 148 #define RCC_CPERCKSELR_CSI      1
 149 #define RCC_CPERCKSELR_HSE      2
 150
 151 /* used for most of DIVR register : max div for RTC */
 152 #define RCC_DIVR_DIV_MASK       GENMASK(5, 0)
 153 #define RCC_DIVR_DIVRDY         BIT(31)
 154
 155 /* Masks for specific DIVR registers */
 156 #define RCC_APBXDIV_MASK        GENMASK(2, 0)
 157 #define RCC_MPUDIV_MASK         GENMASK(2, 0)
 158 #define RCC_AXIDIV_MASK         GENMASK(2, 0)
 159 #define RCC_MCUDIV_MASK         GENMASK(3, 0)
 160
 161 /*  offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
 162 #define RCC_MP_ENCLRR_OFFSET    4
 163
 164 /* Fields of RCC_BDCR register */
 165 #define RCC_BDCR_LSEON          BIT(0)
 166 #define RCC_BDCR_LSEBYP         BIT(1)
 167 #define RCC_BDCR_LSERDY         BIT(2)
 168 #define RCC_BDCR_DIGBYP         BIT(3)
 169 #define RCC_BDCR_LSEDRV_MASK    GENMASK(5, 4)
 170 #define RCC_BDCR_LSEDRV_SHIFT   4
 171 #define RCC_BDCR_LSECSSON       BIT(8)
 172 #define RCC_BDCR_RTCCKEN        BIT(20)
 173 #define RCC_BDCR_RTCSRC_MASK    GENMASK(17, 16)
 174 #define RCC_BDCR_RTCSRC_SHIFT   16
 175
 176 /* Fields of RCC_RDLSICR register */
 177 #define RCC_RDLSICR_LSION       BIT(0)
 178 #define RCC_RDLSICR_LSIRDY      BIT(1)
 179
 180 /* used for ALL PLLNCR registers */
 181 #define RCC_PLLNCR_PLLON        BIT(0)
 182 #define RCC_PLLNCR_PLLRDY       BIT(1)
 183 #define RCC_PLLNCR_SSCG_CTRL    BIT(2)
 184 #define RCC_PLLNCR_DIVPEN       BIT(4)
 185 #define RCC_PLLNCR_DIVQEN       BIT(5)
 186 #define RCC_PLLNCR_DIVREN       BIT(6)
 187 #define RCC_PLLNCR_DIVEN_SHIFT  4
 188
 189 /* used for ALL PLLNCFGR1 registers */
 190 #define RCC_PLLNCFGR1_DIVM_SHIFT        16
 191 #define RCC_PLLNCFGR1_DIVM_MASK         GENMASK(21, 16)
 192 #define RCC_PLLNCFGR1_DIVN_SHIFT        0
 193 #define RCC_PLLNCFGR1_DIVN_MASK         GENMASK(8, 0)
 194 /* only for PLL3 and PLL4 */
 195 #define RCC_PLLNCFGR1_IFRGE_SHIFT       24
 196 #define RCC_PLLNCFGR1_IFRGE_MASK        GENMASK(25, 24)
 197
 198 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
 199 #define RCC_PLLNCFGR2_SHIFT(div_id)     ((div_id) * 8)
 200 #define RCC_PLLNCFGR2_DIVX_MASK         GENMASK(6, 0)
 201 #define RCC_PLLNCFGR2_DIVP_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_P)
 202 #define RCC_PLLNCFGR2_DIVP_MASK         GENMASK(6, 0)
 203 #define RCC_PLLNCFGR2_DIVQ_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_Q)
 204 #define RCC_PLLNCFGR2_DIVQ_MASK         GENMASK(14, 8)
 205 #define RCC_PLLNCFGR2_DIVR_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_R)
 206 #define RCC_PLLNCFGR2_DIVR_MASK         GENMASK(22, 16)
 207
 208 /* used for ALL PLLNFRACR registers */
 209 #define RCC_PLLNFRACR_FRACV_SHIFT       3
 210 #define RCC_PLLNFRACR_FRACV_MASK        GENMASK(15, 3)
 211 #define RCC_PLLNFRACR_FRACLE            BIT(16)
 212
 213 /* used for ALL PLLNCSGR registers */
 214 #define RCC_PLLNCSGR_INC_STEP_SHIFT     16
 215 #define RCC_PLLNCSGR_INC_STEP_MASK      GENMASK(30, 16)
 216 #define RCC_PLLNCSGR_MOD_PER_SHIFT      0
 217 #define RCC_PLLNCSGR_MOD_PER_MASK       GENMASK(12, 0)
 218 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT    15
 219 #define RCC_PLLNCSGR_SSCG_MODE_MASK     BIT(15)
 220
 221 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
 222 #define RCC_OCENR_HSION                 BIT(0)
 223 #define RCC_OCENR_CSION                 BIT(4)
 224 #define RCC_OCENR_DIGBYP                BIT(7)
 225 #define RCC_OCENR_HSEON                 BIT(8)
 226 #define RCC_OCENR_HSEBYP                BIT(10)
 227 #define RCC_OCENR_HSECSSON              BIT(11)
 228
 229 /* Fields of RCC_OCRDYR register */
 230 #define RCC_OCRDYR_HSIRDY               BIT(0)
 231 #define RCC_OCRDYR_HSIDIVRDY            BIT(2)
 232 #define RCC_OCRDYR_CSIRDY               BIT(4)
 233 #define RCC_OCRDYR_HSERDY               BIT(8)
 234
 235 /* Fields of DDRITFCR register */
 236 #define RCC_DDRITFCR_DDRCKMOD_MASK      GENMASK(22, 20)
 237 #define RCC_DDRITFCR_DDRCKMOD_SHIFT     20
 238 #define RCC_DDRITFCR_DDRCKMOD_SSR       0
 239
 240 /* Fields of RCC_HSICFGR register */
 241 #define RCC_HSICFGR_HSIDIV_MASK         GENMASK(1, 0)
 242
 243 /* used for MCO related operations */
 244 #define RCC_MCOCFG_MCOON                BIT(12)
 245 #define RCC_MCOCFG_MCODIV_MASK          GENMASK(7, 4)
 246 #define RCC_MCOCFG_MCODIV_SHIFT         4
 247 #define RCC_MCOCFG_MCOSRC_MASK          GENMASK(2, 0)
 248
 249 enum stm32mp1_parent_id {
 250 /*
 251  * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
 252  * they are used as index in osc[] as entry point
 253  */
 254         _HSI,
 255         _HSE,
 256         _CSI,
 257         _LSI,
 258         _LSE,
 259         _I2S_CKIN,
 260         NB_OSC,
 261
 262 /* other parent source */
 263         _HSI_KER = NB_OSC,
 264         _HSE_KER,
 265         _HSE_KER_DIV2,
 266         _CSI_KER,
 267         _PLL1_P,
 268         _PLL1_Q,
 269         _PLL1_R,
 270         _PLL2_P,
 271         _PLL2_Q,
 272         _PLL2_R,
 273         _PLL3_P,
 274         _PLL3_Q,
 275         _PLL3_R,
 276         _PLL4_P,
 277         _PLL4_Q,
 278         _PLL4_R,
 279         _ACLK,
 280         _PCLK1,
 281         _PCLK2,
 282         _PCLK3,
 283         _PCLK4,
 284         _PCLK5,
 285         _HCLK6,
 286         _HCLK2,
 287         _CK_PER,
 288         _CK_MPU,
 289         _CK_MCU,
 290         _DSI_PHY,
 291         _USB_PHY_48,
 292         _PARENT_NB,
 293         _UNKNOWN_ID = 0xff,
 294 };
 295
 296 enum stm32mp1_parent_sel {
 297         _I2C12_SEL,
 298         _I2C35_SEL,
 299         _I2C46_SEL,
 300         _UART6_SEL,
 301         _UART24_SEL,
 302         _UART35_SEL,
 303         _UART78_SEL,
 304         _SDMMC12_SEL,
 305         _SDMMC3_SEL,
 306         _ETH_SEL,
 307         _QSPI_SEL,
 308         _FMC_SEL,
 309         _USBPHY_SEL,
 310         _USBO_SEL,
 311         _STGEN_SEL,
 312         _DSI_SEL,
 313         _ADC12_SEL,
 314         _SPI1_SEL,
 315         _SPI45_SEL,
 316         _RTC_SEL,
 317         _PARENT_SEL_NB,
 318         _UNKNOWN_SEL = 0xff,
 319 };
 320
 321 enum stm32mp1_pll_id {
 322         _PLL1,
 323         _PLL2,
 324         _PLL3,
 325         _PLL4,
 326         _PLL_NB
 327 };
 328
 329 enum stm32mp1_div_id {
 330         _DIV_P,
 331         _DIV_Q,
 332         _DIV_R,
 333         _DIV_NB,
 334 };
 335
 336 enum stm32mp1_clksrc_id {
 337         CLKSRC_MPU,
 338         CLKSRC_AXI,
 339         CLKSRC_MCU,
 340         CLKSRC_PLL12,
 341         CLKSRC_PLL3,
 342         CLKSRC_PLL4,
 343         CLKSRC_RTC,
 344         CLKSRC_MCO1,
 345         CLKSRC_MCO2,
 346         CLKSRC_NB
 347 };
 348
 349 enum stm32mp1_clkdiv_id {
 350         CLKDIV_MPU,
 351         CLKDIV_AXI,
 352         CLKDIV_MCU,
 353         CLKDIV_APB1,
 354         CLKDIV_APB2,
 355         CLKDIV_APB3,
 356         CLKDIV_APB4,
 357         CLKDIV_APB5,
 358         CLKDIV_RTC,
 359         CLKDIV_MCO1,
 360         CLKDIV_MCO2,
 361         CLKDIV_NB
 362 };
 363
 364 enum stm32mp1_pllcfg {
 365         PLLCFG_M,
 366         PLLCFG_N,
 367         PLLCFG_P,
 368         PLLCFG_Q,
 369         PLLCFG_R,
 370         PLLCFG_O,
 371         PLLCFG_NB
 372 };
 373
 374 enum stm32mp1_pllcsg {
 375         PLLCSG_MOD_PER,
 376         PLLCSG_INC_STEP,
 377         PLLCSG_SSCG_MODE,
 378         PLLCSG_NB
 379 };
 380
 381 enum stm32mp1_plltype {
 382         PLL_800,
 383         PLL_1600,
 384         PLL_TYPE_NB
 385 };
 386
 387 struct stm32mp1_pll {
 388         u8 refclk_min;
 389         u8 refclk_max;
 390         u8 divn_max;
 391 };
 392
 393 struct stm32mp1_clk_gate {
 394         u16 offset;
 395         u8 bit;
 396         u8 index;
 397         u8 set_clr;
 398         u8 sel;
 399         u8 fixed;
 400 };
 401
 402 struct stm32mp1_clk_sel {
 403         u16 offset;
 404         u8 src;
 405         u8 msk;
 406         u8 nb_parent;
 407         const u8 *parent;
 408 };
 409
 410 #define REFCLK_SIZE 4
 411 struct stm32mp1_clk_pll {
 412         enum stm32mp1_plltype plltype;
 413         u16 rckxselr;
 414         u16 pllxcfgr1;
 415         u16 pllxcfgr2;
 416         u16 pllxfracr;
 417         u16 pllxcr;
 418         u16 pllxcsgr;
 419         u8 refclk[REFCLK_SIZE];
 420 };
 421
 422 struct stm32mp1_clk_data {
 423         const struct stm32mp1_clk_gate *gate;
 424         const struct stm32mp1_clk_sel *sel;
 425         const struct stm32mp1_clk_pll *pll;
 426         const int nb_gate;
 427 };
 428
 429 struct stm32mp1_clk_priv {
 430         fdt_addr_t base;
 431         const struct stm32mp1_clk_data *data;
 432         ulong osc[NB_OSC];
 433         struct udevice *osc_dev[NB_OSC];
 434 };
 435
 436 #define STM32MP1_CLK(off, b, idx, s)            \
 437         {                                       \
 438                 .offset = (off),                \
 439                 .bit = (b),                     \
 440                 .index = (idx),                 \
 441                 .set_clr = 0,                   \
 442                 .sel = (s),                     \
 443                 .fixed = _UNKNOWN_ID,           \
 444         }
 445
 446 #define STM32MP1_CLK_F(off, b, idx, f)          \
 447         {                                       \
 448                 .offset = (off),                \
 449                 .bit = (b),                     \
 450                 .index = (idx),                 \
 451                 .set_clr = 0,                   \
 452                 .sel = _UNKNOWN_SEL,            \
 453                 .fixed = (f),                   \
 454         }
 455
 456 #define STM32MP1_CLK_SET_CLR(off, b, idx, s)    \
 457         {                                       \
 458                 .offset = (off),                \
 459                 .bit = (b),                     \
 460                 .index = (idx),                 \
 461                 .set_clr = 1,                   \
 462                 .sel = (s),                     \
 463                 .fixed = _UNKNOWN_ID,           \
 464         }
 465
 466 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f)  \
 467         {                                       \
 468                 .offset = (off),                \
 469                 .bit = (b),                     \
 470                 .index = (idx),                 \
 471                 .set_clr = 1,                   \
 472                 .sel = _UNKNOWN_SEL,            \
 473                 .fixed = (f),                   \
 474         }
 475
 476 #define STM32MP1_CLK_PARENT(idx, off, s, m, p)   \
 477         [(idx)] = {                             \
 478                 .offset = (off),                \
 479                 .src = (s),                     \
 480                 .msk = (m),                     \
 481                 .parent = (p),                  \
 482                 .nb_parent = ARRAY_SIZE((p))    \
 483         }
 484
 485 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
 486                         p1, p2, p3, p4) \
 487         [(idx)] = {                             \
 488                 .plltype = (type),                      \
 489                 .rckxselr = (off1),             \
 490                 .pllxcfgr1 = (off2),            \
 491                 .pllxcfgr2 = (off3),            \
 492                 .pllxfracr = (off4),            \
 493                 .pllxcr = (off5),               \
 494                 .pllxcsgr = (off6),             \
 495                 .refclk[0] = (p1),              \
 496                 .refclk[1] = (p2),              \
 497                 .refclk[2] = (p3),              \
 498                 .refclk[3] = (p4),              \
 499         }
 500
 501 static const u8 stm32mp1_clks[][2] = {
 502         {CK_PER, _CK_PER},
 503         {CK_MPU, _CK_MPU},
 504         {CK_AXI, _ACLK},
 505         {CK_MCU, _CK_MCU},
 506         {CK_HSE, _HSE},
 507         {CK_CSI, _CSI},
 508         {CK_LSI, _LSI},
 509         {CK_LSE, _LSE},
 510         {CK_HSI, _HSI},
 511         {CK_HSE_DIV2, _HSE_KER_DIV2},
 512 };
 513
 514 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 515         STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
 516         STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
 517         STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
 518         STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
 519         STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
 520         STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
 521         STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
 522         STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
 523         STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
 524         STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
 525         STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
 526
 527         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
 528         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
 529         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
 530         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
 531         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
 532         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
 533         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
 534         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
 535         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
 536         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
 537
 538         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
 539         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL),
 540         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 541
 542         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
 543
 544         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
 545         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
 546         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
 547         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
 548         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
 549         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
 550
 551         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
 552         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
 553         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
 554         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
 555
 556         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
 557         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
 558         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
 559         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
 560
 561         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
 562         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
 563
 564         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
 565         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
 566         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
 567         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
 568         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
 569         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
 570         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
 571         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
 572         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
 573         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
 574         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 575
 576         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
 577         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _UNKNOWN_SEL),
 578
 579         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
 580         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
 581         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
 582         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
 583         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
 584         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
 585         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
 586         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
 587         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
 588
 589         STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
 590
 591         STM32MP1_CLK(RCC_BDCR, 20, RTC, _RTC_SEL),
 592 };
 593
 594 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 595 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 596 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
 597 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
 598                                         _HSE_KER};
 599 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 600                                          _HSE_KER};
 601 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 602                                          _HSE_KER};
 603 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 604                                          _HSE_KER};
 605 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
 606 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
 607 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
 608 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 609 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 610 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
 611 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
 612 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
 613 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
 614 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
 615 static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
 616                                  _PLL3_R};
 617 static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
 618                                    _HSE_KER};
 619 static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
 620
 621 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
 622         STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
 623         STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
 624         STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
 625         STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
 626         STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
 627                             uart24_parents),
 628         STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
 629                             uart35_parents),
 630         STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
 631                             uart78_parents),
 632         STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
 633                             sdmmc12_parents),
 634         STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
 635                             sdmmc3_parents),
 636         STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
 637         STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0x3, qspi_parents),
 638         STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0x3, fmc_parents),
 639         STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
 640         STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
 641         STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
 642         STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
 643         STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents),
 644         STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
 645         STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents),
 646         STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
 647                             (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
 648                             rtc_parents),
 649 };
 650
 651 #ifdef STM32MP1_CLOCK_TREE_INIT
 652
 653 /* define characteristic of PLL according type */
 654 #define DIVM_MIN        0
 655 #define DIVM_MAX        63
 656 #define DIVN_MIN        24
 657 #define DIVP_MIN        0
 658 #define DIVP_MAX        127
 659 #define FRAC_MAX        8192
 660
 661 #define PLL1600_VCO_MIN 800000000
 662 #define PLL1600_VCO_MAX 1600000000
 663
 664 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
 665         [PLL_800] = {
 666                 .refclk_min = 4,
 667                 .refclk_max = 16,
 668                 .divn_max = 99,
 669                 },
 670         [PLL_1600] = {
 671                 .refclk_min = 8,
 672                 .refclk_max = 16,
 673                 .divn_max = 199,
 674                 },
 675 };
 676 #endif /* STM32MP1_CLOCK_TREE_INIT */
 677
 678 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
 679         STM32MP1_CLK_PLL(_PLL1, PLL_1600,
 680                          RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
 681                          RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
 682                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 683         STM32MP1_CLK_PLL(_PLL2, PLL_1600,
 684                          RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
 685                          RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
 686                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 687         STM32MP1_CLK_PLL(_PLL3, PLL_800,
 688                          RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
 689                          RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
 690                          _HSI, _HSE, _CSI, _UNKNOWN_ID),
 691         STM32MP1_CLK_PLL(_PLL4, PLL_800,
 692                          RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
 693                          RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
 694                          _HSI, _HSE, _CSI, _I2S_CKIN),
 695 };
 696
 697 /* Prescaler table lookups for clock computation */
 698 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
 699 static const u8 stm32mp1_mcu_div[16] = {
 700         0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
 701 };
 702
 703 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
 704 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
 705 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
 706 static const u8 stm32mp1_mpu_apbx_div[8] = {
 707         0, 1, 2, 3, 4, 4, 4, 4
 708 };
 709
 710 /* div = /1 /2 /3 /4 */
 711 static const u8 stm32mp1_axi_div[8] = {
 712         1, 2, 3, 4, 4, 4, 4, 4
 713 };
 714
 715 static const __maybe_unused
 716 char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
 717         [_HSI] = "HSI",
 718         [_HSE] = "HSE",
 719         [_CSI] = "CSI",
 720         [_LSI] = "LSI",
 721         [_LSE] = "LSE",
 722         [_I2S_CKIN] = "I2S_CKIN",
 723         [_HSI_KER] = "HSI_KER",
 724         [_HSE_KER] = "HSE_KER",
 725         [_HSE_KER_DIV2] = "HSE_KER_DIV2",
 726         [_CSI_KER] = "CSI_KER",
 727         [_PLL1_P] = "PLL1_P",
 728         [_PLL1_Q] = "PLL1_Q",
 729         [_PLL1_R] = "PLL1_R",
 730         [_PLL2_P] = "PLL2_P",
 731         [_PLL2_Q] = "PLL2_Q",
 732         [_PLL2_R] = "PLL2_R",
 733         [_PLL3_P] = "PLL3_P",
 734         [_PLL3_Q] = "PLL3_Q",
 735         [_PLL3_R] = "PLL3_R",
 736         [_PLL4_P] = "PLL4_P",
 737         [_PLL4_Q] = "PLL4_Q",
 738         [_PLL4_R] = "PLL4_R",
 739         [_ACLK] = "ACLK",
 740         [_PCLK1] = "PCLK1",
 741         [_PCLK2] = "PCLK2",
 742         [_PCLK3] = "PCLK3",
 743         [_PCLK4] = "PCLK4",
 744         [_PCLK5] = "PCLK5",
 745         [_HCLK6] = "KCLK6",
 746         [_HCLK2] = "HCLK2",
 747         [_CK_PER] = "CK_PER",
 748         [_CK_MPU] = "CK_MPU",
 749         [_CK_MCU] = "CK_MCU",
 750         [_USB_PHY_48] = "USB_PHY_48",
 751         [_DSI_PHY] = "DSI_PHY_PLL",
 752 };
 753
 754 static const __maybe_unused
 755 char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
 756         [_I2C12_SEL] = "I2C12",
 757         [_I2C35_SEL] = "I2C35",
 758         [_I2C46_SEL] = "I2C46",
 759         [_UART6_SEL] = "UART6",
 760         [_UART24_SEL] = "UART24",
 761         [_UART35_SEL] = "UART35",
 762         [_UART78_SEL] = "UART78",
 763         [_SDMMC12_SEL] = "SDMMC12",
 764         [_SDMMC3_SEL] = "SDMMC3",
 765         [_ETH_SEL] = "ETH",
 766         [_QSPI_SEL] = "QSPI",
 767         [_FMC_SEL] = "FMC",
 768         [_USBPHY_SEL] = "USBPHY",
 769         [_USBO_SEL] = "USBO",
 770         [_STGEN_SEL] = "STGEN",
 771         [_DSI_SEL] = "DSI",
 772         [_ADC12_SEL] = "ADC12",
 773         [_SPI1_SEL] = "SPI1",
 774         [_SPI45_SEL] = "SPI45",
 775         [_RTC_SEL] = "RTC",
 776 };
 777
 778 static const struct stm32mp1_clk_data stm32mp1_data = {
 779         .gate = stm32mp1_clk_gate,
 780         .sel = stm32mp1_clk_sel,
 781         .pll = stm32mp1_clk_pll,
 782         .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
 783 };
 784
 785 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
 786 {
 787         if (idx >= NB_OSC) {
 788                 log_debug("clk id %d not found\n", idx);
 789                 return 0;
 790         }
 791
 792         return priv->osc[idx];
 793 }
 794
 795 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
 796 {
 797         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 798         int i, nb_clks = priv->data->nb_gate;
 799
 800         for (i = 0; i < nb_clks; i++) {
 801                 if (gate[i].index == id)
 802                         break;
 803         }
 804
 805         if (i == nb_clks) {
 806                 log_err("clk id %d not found\n", (u32)id);
 807                 return -EINVAL;
 808         }
 809
 810         return i;
 811 }
 812
 813 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
 814                                 int i)
 815 {
 816         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 817
 818         if (gate[i].sel > _PARENT_SEL_NB) {
 819                 log_err("parents for clk id %d not found\n", i);
 820                 return -EINVAL;
 821         }
 822
 823         return gate[i].sel;
 824 }
 825
 826 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
 827                                          int i)
 828 {
 829         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 830
 831         if (gate[i].fixed == _UNKNOWN_ID)
 832                 return -ENOENT;
 833
 834         return gate[i].fixed;
 835 }
 836
 837 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
 838                                    unsigned long id)
 839 {
 840         const struct stm32mp1_clk_sel *sel = priv->data->sel;
 841         int i;
 842         int s, p;
 843         unsigned int idx;
 844
 845         for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++)
 846                 if (stm32mp1_clks[idx][0] == id)
 847                         return stm32mp1_clks[idx][1];
 848
 849         i = stm32mp1_clk_get_id(priv, id);
 850         if (i < 0)
 851                 return i;
 852
 853         p = stm32mp1_clk_get_fixed_parent(priv, i);
 854         if (p >= 0 && p < _PARENT_NB)
 855                 return p;
 856
 857         s = stm32mp1_clk_get_sel(priv, i);
 858         if (s < 0)
 859                 return s;
 860
 861         p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
 862
 863         if (p < sel[s].nb_parent) {
 864                 log_content("%s clock is the parent %s of clk id %d\n",
 865                             stm32mp1_clk_parent_name[sel[s].parent[p]],
 866                             stm32mp1_clk_parent_sel_name[s],
 867                             (u32)id);
 868                 return sel[s].parent[p];
 869         }
 870
 871         log_err("no parents defined for clk id %d\n", (u32)id);
 872
 873         return -EINVAL;
 874 }
 875
 876 static ulong  pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
 877                               int pll_id)
 878 {
 879         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 880         u32 selr;
 881         int src;
 882         ulong refclk;
 883
 884         /* Get current refclk */
 885         selr = readl(priv->base + pll[pll_id].rckxselr);
 886         src = selr & RCC_SELR_SRC_MASK;
 887
 888         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
 889
 890         return refclk;
 891 }
 892
 893 /*
 894  * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
 895  * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
 896  * - PLL3 & PLL4 => return VCO     with Fpll_y_ck = FVCO / (DIVy + 1)
 897  * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
 898  */
 899 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
 900                           int pll_id)
 901 {
 902         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 903         int divm, divn;
 904         ulong refclk, fvco;
 905         u32 cfgr1, fracr;
 906
 907         cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
 908         fracr = readl(priv->base + pll[pll_id].pllxfracr);
 909
 910         divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
 911         divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
 912
 913         refclk = pll_get_fref_ck(priv, pll_id);
 914
 915         /* with FRACV :
 916          *   Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
 917          * without FRACV
 918          *   Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
 919          */
 920         if (fracr & RCC_PLLNFRACR_FRACLE) {
 921                 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
 922                             >> RCC_PLLNFRACR_FRACV_SHIFT;
 923                 fvco = (ulong)lldiv((unsigned long long)refclk *
 924                                      (((divn + 1) << 13) + fracv),
 925                                      ((unsigned long long)(divm + 1)) << 13);
 926         } else {
 927                 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
 928         }
 929
 930         return fvco;
 931 }
 932
 933 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
 934                                     int pll_id, int div_id)
 935 {
 936         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 937         int divy;
 938         ulong dfout;
 939         u32 cfgr2;
 940
 941         if (div_id >= _DIV_NB)
 942                 return 0;
 943
 944         cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
 945         divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
 946
 947         dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
 948
 949         return dfout;
 950 }
 951
 952 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
 953 {
 954         u32 reg;
 955         ulong clock = 0;
 956
 957         switch (p) {
 958         case _CK_MPU:
 959         /* MPU sub system */
 960                 reg = readl(priv->base + RCC_MPCKSELR);
 961                 switch (reg & RCC_SELR_SRC_MASK) {
 962                 case RCC_MPCKSELR_HSI:
 963                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 964                         break;
 965                 case RCC_MPCKSELR_HSE:
 966                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 967                         break;
 968                 case RCC_MPCKSELR_PLL:
 969                 case RCC_MPCKSELR_PLL_MPUDIV:
 970                         clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
 971                         if ((reg & RCC_SELR_SRC_MASK) ==
 972                             RCC_MPCKSELR_PLL_MPUDIV) {
 973                                 reg = readl(priv->base + RCC_MPCKDIVR);
 974                                 clock >>= stm32mp1_mpu_div[reg &
 975                                         RCC_MPUDIV_MASK];
 976                         }
 977                         break;
 978                 }
 979                 break;
 980         /* AXI sub system */
 981         case _ACLK:
 982         case _HCLK2:
 983         case _HCLK6:
 984         case _PCLK4:
 985         case _PCLK5:
 986                 reg = readl(priv->base + RCC_ASSCKSELR);
 987                 switch (reg & RCC_SELR_SRC_MASK) {
 988                 case RCC_ASSCKSELR_HSI:
 989                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 990                         break;
 991                 case RCC_ASSCKSELR_HSE:
 992                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 993                         break;
 994                 case RCC_ASSCKSELR_PLL:
 995                         clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
 996                         break;
 997                 }
 998
 999                 /* System clock divider */
1000                 reg = readl(priv->base + RCC_AXIDIVR);
1001                 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
1002
1003                 switch (p) {
1004                 case _PCLK4:
1005                         reg = readl(priv->base + RCC_APB4DIVR);
1006                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1007                         break;
1008                 case _PCLK5:
1009                         reg = readl(priv->base + RCC_APB5DIVR);
1010                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1011                         break;
1012                 default:
1013                         break;
1014                 }
1015                 break;
1016         /* MCU sub system */
1017         case _CK_MCU:
1018         case _PCLK1:
1019         case _PCLK2:
1020         case _PCLK3:
1021                 reg = readl(priv->base + RCC_MSSCKSELR);
1022                 switch (reg & RCC_SELR_SRC_MASK) {
1023                 case RCC_MSSCKSELR_HSI:
1024                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1025                         break;
1026                 case RCC_MSSCKSELR_HSE:
1027                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1028                         break;
1029                 case RCC_MSSCKSELR_CSI:
1030                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1031                         break;
1032                 case RCC_MSSCKSELR_PLL:
1033                         clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
1034                         break;
1035                 }
1036
1037                 /* MCU clock divider */
1038                 reg = readl(priv->base + RCC_MCUDIVR);
1039                 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1040
1041                 switch (p) {
1042                 case _PCLK1:
1043                         reg = readl(priv->base + RCC_APB1DIVR);
1044                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1045                         break;
1046                 case _PCLK2:
1047                         reg = readl(priv->base + RCC_APB2DIVR);
1048                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1049                         break;
1050                 case _PCLK3:
1051                         reg = readl(priv->base + RCC_APB3DIVR);
1052                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1053                         break;
1054                 case _CK_MCU:
1055                 default:
1056                         break;
1057                 }
1058                 break;
1059         case _CK_PER:
1060                 reg = readl(priv->base + RCC_CPERCKSELR);
1061                 switch (reg & RCC_SELR_SRC_MASK) {
1062                 case RCC_CPERCKSELR_HSI:
1063                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1064                         break;
1065                 case RCC_CPERCKSELR_HSE:
1066                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1067                         break;
1068                 case RCC_CPERCKSELR_CSI:
1069                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1070                         break;
1071                 }
1072                 break;
1073         case _HSI:
1074         case _HSI_KER:
1075                 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1076                 break;
1077         case _CSI:
1078         case _CSI_KER:
1079                 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1080                 break;
1081         case _HSE:
1082         case _HSE_KER:
1083         case _HSE_KER_DIV2:
1084                 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1085                 if (p == _HSE_KER_DIV2)
1086                         clock >>= 1;
1087                 break;
1088         case _LSI:
1089                 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1090                 break;
1091         case _LSE:
1092                 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1093                 break;
1094         /* PLL */
1095         case _PLL1_P:
1096         case _PLL1_Q:
1097         case _PLL1_R:
1098                 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1099                 break;
1100         case _PLL2_P:
1101         case _PLL2_Q:
1102         case _PLL2_R:
1103                 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1104                 break;
1105         case _PLL3_P:
1106         case _PLL3_Q:
1107         case _PLL3_R:
1108                 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1109                 break;
1110         case _PLL4_P:
1111         case _PLL4_Q:
1112         case _PLL4_R:
1113                 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1114                 break;
1115         /* other */
1116         case _USB_PHY_48:
1117                 clock = 48000000;
1118                 break;
1119         case _DSI_PHY:
1120         {
1121                 struct clk clk;
1122                 struct udevice *dev = NULL;
1123
1124                 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1125                                                &dev)) {
1126                         if (clk_request(dev, &clk)) {
1127                                 log_err("ck_dsi_phy request");
1128                         } else {
1129                                 clk.id = 0;
1130                                 clock = clk_get_rate(&clk);
1131                         }
1132                 }
1133                 break;
1134         }
1135         default:
1136                 break;
1137         }
1138
1139         log_debug("id=%d clock = %lx : %ld kHz\n", p, clock, clock / 1000);
1140
1141         return clock;
1142 }
1143
1144 static int stm32mp1_clk_enable(struct clk *clk)
1145 {
1146         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1147         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1148         int i = stm32mp1_clk_get_id(priv, clk->id);
1149
1150         if (i < 0)
1151                 return i;
1152
1153         if (gate[i].set_clr)
1154                 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1155         else
1156                 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1157
1158         dev_dbg(clk->dev, "%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1159
1160         return 0;
1161 }
1162
1163 static int stm32mp1_clk_disable(struct clk *clk)
1164 {
1165         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1166         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1167         int i = stm32mp1_clk_get_id(priv, clk->id);
1168
1169         if (i < 0)
1170                 return i;
1171
1172         if (gate[i].set_clr)
1173                 writel(BIT(gate[i].bit),
1174                        priv->base + gate[i].offset
1175                        + RCC_MP_ENCLRR_OFFSET);
1176         else
1177                 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1178
1179         dev_dbg(clk->dev, "%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1180
1181         return 0;
1182 }
1183
1184 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1185 {
1186         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1187         int p = stm32mp1_clk_get_parent(priv, clk->id);
1188         ulong rate;
1189
1190         if (p < 0)
1191                 return 0;
1192
1193         rate = stm32mp1_clk_get(priv, p);
1194
1195         dev_vdbg(clk->dev, "computed rate for id clock %d is %d (parent is %s)\n",
1196                  (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1197
1198         return rate;
1199 }
1200
1201 #ifdef STM32MP1_CLOCK_TREE_INIT
1202
1203 bool stm32mp1_supports_opp(u32 opp_id, u32 cpu_type)
1204 {
1205         unsigned int id;
1206
1207         switch (opp_id) {
1208         case 1:
1209         case 2:
1210                 id = opp_id;
1211                 break;
1212         default:
1213                 id = 1; /* default value */
1214                 break;
1215         }
1216
1217         switch (cpu_type) {
1218         case CPU_STM32MP157Fxx:
1219         case CPU_STM32MP157Dxx:
1220         case CPU_STM32MP153Fxx:
1221         case CPU_STM32MP153Dxx:
1222         case CPU_STM32MP151Fxx:
1223         case CPU_STM32MP151Dxx:
1224                 return true;
1225         default:
1226                 return id == 1;
1227         }
1228 }
1229
1230 __weak void board_vddcore_init(u32 voltage_mv)
1231 {
1232 }
1233
1234 /*
1235  * gets OPP parameters (frequency in KHz and voltage in mV) from
1236  * an OPP table subnode. Platform HW support capabilities are also checked.
1237  * Returns 0 on success and a negative FDT error code on failure.
1238  */
1239 static int stm32mp1_get_opp(u32 cpu_type, ofnode subnode,
1240                             u32 *freq_khz, u32 *voltage_mv)
1241 {
1242         u32 opp_hw;
1243         u64 read_freq_64;
1244         u32 read_voltage_32;
1245
1246         *freq_khz = 0;
1247         *voltage_mv = 0;
1248
1249         opp_hw = ofnode_read_u32_default(subnode, "opp-supported-hw", 0);
1250         if (opp_hw)
1251                 if (!stm32mp1_supports_opp(opp_hw, cpu_type))
1252                         return -FDT_ERR_BADVALUE;
1253
1254         read_freq_64 = ofnode_read_u64_default(subnode, "opp-hz", 0) /
1255                        1000ULL;
1256         read_voltage_32 = ofnode_read_u32_default(subnode, "opp-microvolt", 0) /
1257                           1000U;
1258
1259         if (!read_voltage_32 || !read_freq_64)
1260                 return -FDT_ERR_NOTFOUND;
1261
1262         /* Frequency value expressed in KHz must fit on 32 bits */
1263         if (read_freq_64 > U32_MAX)
1264                 return -FDT_ERR_BADVALUE;
1265
1266         /* Millivolt value must fit on 16 bits */
1267         if (read_voltage_32 > U16_MAX)
1268                 return -FDT_ERR_BADVALUE;
1269
1270         *freq_khz = (u32)read_freq_64;
1271         *voltage_mv = read_voltage_32;
1272
1273         return 0;
1274 }
1275
1276 /*
1277  * parses OPP table in DT and finds the parameters for the
1278  * highest frequency supported by the HW platform.
1279  * Returns 0 on success and a negative FDT error code on failure.
1280  */
1281 int stm32mp1_get_max_opp_freq(struct stm32mp1_clk_priv *priv, u64 *freq_hz)
1282 {
1283         ofnode node, subnode;
1284         int ret;
1285         u32 freq = 0U, voltage = 0U;
1286         u32 cpu_type = get_cpu_type();
1287
1288         node = ofnode_by_compatible(ofnode_null(), "operating-points-v2");
1289         if (!ofnode_valid(node))
1290                 return -FDT_ERR_NOTFOUND;
1291
1292         ofnode_for_each_subnode(subnode, node) {
1293                 unsigned int read_freq;
1294                 unsigned int read_voltage;
1295
1296                 ret = stm32mp1_get_opp(cpu_type, subnode,
1297                                        &read_freq, &read_voltage);
1298                 if (ret)
1299                         continue;
1300
1301                 if (read_freq > freq) {
1302                         freq = read_freq;
1303                         voltage = read_voltage;
1304                 }
1305         }
1306
1307         if (!freq || !voltage)
1308                 return -FDT_ERR_NOTFOUND;
1309
1310         *freq_hz = (u64)1000U * freq;
1311         board_vddcore_init(voltage);
1312
1313         return 0;
1314 }
1315
1316 static int stm32mp1_pll1_opp(struct stm32mp1_clk_priv *priv, int clksrc,
1317                              u32 *pllcfg, u32 *fracv)
1318 {
1319         u32 post_divm;
1320         u32 input_freq;
1321         u64 output_freq;
1322         u64 freq;
1323         u64 vco;
1324         u32 divm, divn, divp, frac;
1325         int i, ret;
1326         u32 diff;
1327         u32 best_diff = U32_MAX;
1328
1329         /* PLL1 is 1600 */
1330         const u32 DIVN_MAX = stm32mp1_pll[PLL_1600].divn_max;
1331         const u32 POST_DIVM_MIN = stm32mp1_pll[PLL_1600].refclk_min * 1000000U;
1332         const u32 POST_DIVM_MAX = stm32mp1_pll[PLL_1600].refclk_max * 1000000U;
1333
1334         ret = stm32mp1_get_max_opp_freq(priv, &output_freq);
1335         if (ret) {
1336                 log_debug("PLL1 OPP configuration not found (%d).\n", ret);
1337                 return ret;
1338         }
1339
1340         switch (clksrc) {
1341         case CLK_PLL12_HSI:
1342                 input_freq = stm32mp1_clk_get_fixed(priv, _HSI);
1343                 break;
1344         case CLK_PLL12_HSE:
1345                 input_freq = stm32mp1_clk_get_fixed(priv, _HSE);
1346                 break;
1347         default:
1348                 return -EINTR;
1349         }
1350
1351         /* Following parameters have always the same value */
1352         pllcfg[PLLCFG_Q] = 0;
1353         pllcfg[PLLCFG_R] = 0;
1354         pllcfg[PLLCFG_O] = PQR(1, 0, 0);
1355
1356         for (divm = DIVM_MAX; divm >= DIVM_MIN; divm--) {
1357                 post_divm = (u32)(input_freq / (divm + 1));
1358                 if (post_divm < POST_DIVM_MIN || post_divm > POST_DIVM_MAX)
1359                         continue;
1360
1361                 for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) {
1362                         freq = output_freq * (divm + 1) * (divp + 1);
1363                         divn = (u32)((freq / input_freq) - 1);
1364                         if (divn < DIVN_MIN || divn > DIVN_MAX)
1365                                 continue;
1366
1367                         frac = (u32)(((freq * FRAC_MAX) / input_freq) -
1368                                      ((divn + 1) * FRAC_MAX));
1369                         /* 2 loops to refine the fractional part */
1370                         for (i = 2; i != 0; i--) {
1371                                 if (frac > FRAC_MAX)
1372                                         break;
1373
1374                                 vco = (post_divm * (divn + 1)) +
1375                                       ((post_divm * (u64)frac) /
1376                                        FRAC_MAX);
1377                                 if (vco < (PLL1600_VCO_MIN / 2) ||
1378                                     vco > (PLL1600_VCO_MAX / 2)) {
1379                                         frac++;
1380                                         continue;
1381                                 }
1382                                 freq = vco / (divp + 1);
1383                                 if (output_freq < freq)
1384                                         diff = (u32)(freq - output_freq);
1385                                 else
1386                                         diff = (u32)(output_freq - freq);
1387                                 if (diff < best_diff)  {
1388                                         pllcfg[PLLCFG_M] = divm;
1389                                         pllcfg[PLLCFG_N] = divn;
1390                                         pllcfg[PLLCFG_P] = divp;
1391                                         *fracv = frac;
1392
1393                                         if (diff == 0)
1394                                                 return 0;
1395
1396                                         best_diff = diff;
1397                                 }
1398                                 frac++;
1399                         }
1400                 }
1401         }
1402
1403         if (best_diff == U32_MAX)
1404                 return -1;
1405
1406         return 0;
1407 }
1408
1409 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1410                                 u32 mask_on)
1411 {
1412         u32 address = rcc + offset;
1413
1414         if (enable)
1415                 setbits_le32(address, mask_on);
1416         else
1417                 clrbits_le32(address, mask_on);
1418 }
1419
1420 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1421 {
1422         writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
1423 }
1424
1425 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1426                              u32 mask_rdy)
1427 {
1428         u32 mask_test = 0;
1429         u32 address = rcc + offset;
1430         u32 val;
1431         int ret;
1432
1433         if (enable)
1434                 mask_test = mask_rdy;
1435
1436         ret = readl_poll_timeout(address, val,
1437                                  (val & mask_rdy) == mask_test,
1438                                  TIMEOUT_1S);
1439
1440         if (ret)
1441                 log_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1442                         mask_rdy, address, enable, readl(address));
1443
1444         return ret;
1445 }
1446
1447 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
1448                                 u32 lsedrv)
1449 {
1450         u32 value;
1451
1452         if (digbyp)
1453                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
1454
1455         if (bypass || digbyp)
1456                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1457
1458         /*
1459          * warning: not recommended to switch directly from "high drive"
1460          * to "medium low drive", and vice-versa.
1461          */
1462         value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1463                 >> RCC_BDCR_LSEDRV_SHIFT;
1464
1465         while (value != lsedrv) {
1466                 if (value > lsedrv)
1467                         value--;
1468                 else
1469                         value++;
1470
1471                 clrsetbits_le32(rcc + RCC_BDCR,
1472                                 RCC_BDCR_LSEDRV_MASK,
1473                                 value << RCC_BDCR_LSEDRV_SHIFT);
1474         }
1475
1476         stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1477 }
1478
1479 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1480 {
1481         stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1482 }
1483
1484 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1485 {
1486         stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1487         stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1488 }
1489
1490 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
1491 {
1492         if (digbyp)
1493                 writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
1494         if (bypass || digbyp)
1495                 writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
1496
1497         stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1498         stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1499
1500         if (css)
1501                 writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
1502 }
1503
1504 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1505 {
1506         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
1507         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1508 }
1509
1510 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1511 {
1512         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1513         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1514 }
1515
1516 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1517 {
1518         u32 address = rcc + RCC_OCRDYR;
1519         u32 val;
1520         int ret;
1521
1522         clrsetbits_le32(rcc + RCC_HSICFGR,
1523                         RCC_HSICFGR_HSIDIV_MASK,
1524                         RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1525
1526         ret = readl_poll_timeout(address, val,
1527                                  val & RCC_OCRDYR_HSIDIVRDY,
1528                                  TIMEOUT_200MS);
1529         if (ret)
1530                 log_err("HSIDIV failed @ 0x%x: 0x%x\n",
1531                         address, readl(address));
1532
1533         return ret;
1534 }
1535
1536 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1537 {
1538         u8 hsidiv;
1539         u32 hsidivfreq = MAX_HSI_HZ;
1540
1541         for (hsidiv = 0; hsidiv < 4; hsidiv++,
1542              hsidivfreq = hsidivfreq / 2)
1543                 if (hsidivfreq == hsifreq)
1544                         break;
1545
1546         if (hsidiv == 4) {
1547                 log_err("clk-hsi frequency invalid");
1548                 return -1;
1549         }
1550
1551         if (hsidiv > 0)
1552                 return stm32mp1_set_hsidiv(rcc, hsidiv);
1553
1554         return 0;
1555 }
1556
1557 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1558 {
1559         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1560
1561         clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
1562                         RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1563                         RCC_PLLNCR_DIVREN,
1564                         RCC_PLLNCR_PLLON);
1565 }
1566
1567 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1568 {
1569         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1570         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1571         u32 val;
1572         int ret;
1573
1574         ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1575                                  TIMEOUT_200MS);
1576
1577         if (ret) {
1578                 log_err("PLL%d start failed @ 0x%x: 0x%x\n",
1579                         pll_id, pllxcr, readl(pllxcr));
1580                 return ret;
1581         }
1582
1583         /* start the requested output */
1584         setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1585
1586         return 0;
1587 }
1588
1589 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1590 {
1591         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1592         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1593         u32 val;
1594
1595         /* stop all output */
1596         clrbits_le32(pllxcr,
1597                      RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1598
1599         /* stop PLL */
1600         clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1601
1602         /* wait PLL stopped */
1603         return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1604                                   TIMEOUT_200MS);
1605 }
1606
1607 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1608                               int pll_id, u32 *pllcfg)
1609 {
1610         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1611         fdt_addr_t rcc = priv->base;
1612         u32 value;
1613
1614         value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1615                 & RCC_PLLNCFGR2_DIVP_MASK;
1616         value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1617                  & RCC_PLLNCFGR2_DIVQ_MASK;
1618         value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1619                  & RCC_PLLNCFGR2_DIVR_MASK;
1620         writel(value, rcc + pll[pll_id].pllxcfgr2);
1621 }
1622
1623 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1624                       u32 *pllcfg, u32 fracv)
1625 {
1626         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1627         fdt_addr_t rcc = priv->base;
1628         enum stm32mp1_plltype type = pll[pll_id].plltype;
1629         int src;
1630         ulong refclk;
1631         u8 ifrge = 0;
1632         u32 value;
1633
1634         src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1635
1636         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1637                  (pllcfg[PLLCFG_M] + 1);
1638
1639         if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1640             refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1641                 log_err("invalid refclk = %x\n", (u32)refclk);
1642                 return -EINVAL;
1643         }
1644         if (type == PLL_800 && refclk >= 8000000)
1645                 ifrge = 1;
1646
1647         value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1648                  & RCC_PLLNCFGR1_DIVN_MASK;
1649         value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1650                  & RCC_PLLNCFGR1_DIVM_MASK;
1651         value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1652                  & RCC_PLLNCFGR1_IFRGE_MASK;
1653         writel(value, rcc + pll[pll_id].pllxcfgr1);
1654
1655         /* fractional configuration: load sigma-delta modulator (SDM) */
1656
1657         /* Write into FRACV the new fractional value , and FRACLE to 0 */
1658         writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1659                rcc + pll[pll_id].pllxfracr);
1660
1661         /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1662         setbits_le32(rcc + pll[pll_id].pllxfracr,
1663                      RCC_PLLNFRACR_FRACLE);
1664
1665         pll_config_output(priv, pll_id, pllcfg);
1666
1667         return 0;
1668 }
1669
1670 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1671 {
1672         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1673         u32 pllxcsg;
1674
1675         pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1676                     RCC_PLLNCSGR_MOD_PER_MASK) |
1677                   ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1678                     RCC_PLLNCSGR_INC_STEP_MASK) |
1679                   ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1680                     RCC_PLLNCSGR_SSCG_MODE_MASK);
1681
1682         writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1683
1684         setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
1685 }
1686
1687 static  __maybe_unused int pll_set_rate(struct udevice *dev,
1688                                         int pll_id,
1689                                         int div_id,
1690                                         unsigned long clk_rate)
1691 {
1692         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1693         unsigned int pllcfg[PLLCFG_NB];
1694         ofnode plloff;
1695         char name[12];
1696         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1697         enum stm32mp1_plltype type = pll[pll_id].plltype;
1698         int divm, divn, divy;
1699         int ret;
1700         ulong fck_ref;
1701         u32 fracv;
1702         u64 value;
1703
1704         if (div_id > _DIV_NB)
1705                 return -EINVAL;
1706
1707         sprintf(name, "st,pll@%d", pll_id);
1708         plloff = dev_read_subnode(dev, name);
1709         if (!ofnode_valid(plloff))
1710                 return -FDT_ERR_NOTFOUND;
1711
1712         ret = ofnode_read_u32_array(plloff, "cfg",
1713                                     pllcfg, PLLCFG_NB);
1714         if (ret < 0)
1715                 return -FDT_ERR_NOTFOUND;
1716
1717         fck_ref = pll_get_fref_ck(priv, pll_id);
1718
1719         divm = pllcfg[PLLCFG_M];
1720         /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
1721         divy = pllcfg[PLLCFG_P + div_id];
1722
1723         /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
1724          * So same final result than PLL2 et 4
1725          * with FRACV
1726          * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
1727          *             / (DIVy + 1) * (DIVM + 1)
1728          * value = (DIVN + 1) * 2^13 + FRACV / 2^13
1729          *       = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
1730          */
1731         value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
1732         value = lldiv(value, fck_ref);
1733
1734         divn = (value >> 13) - 1;
1735         if (divn < DIVN_MIN ||
1736             divn > stm32mp1_pll[type].divn_max) {
1737                 dev_err(dev, "divn invalid = %d", divn);
1738                 return -EINVAL;
1739         }
1740         fracv = value - ((divn + 1) << 13);
1741         pllcfg[PLLCFG_N] = divn;
1742
1743         /* reconfigure PLL */
1744         pll_stop(priv, pll_id);
1745         pll_config(priv, pll_id, pllcfg, fracv);
1746         pll_start(priv, pll_id);
1747         pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
1748
1749         return 0;
1750 }
1751
1752 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1753 {
1754         u32 address = priv->base + (clksrc >> 4);
1755         u32 val;
1756         int ret;
1757
1758         clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1759         ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1760                                  TIMEOUT_200MS);
1761         if (ret)
1762                 log_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1763                         clksrc, address, readl(address));
1764
1765         return ret;
1766 }
1767
1768 static void stgen_config(struct stm32mp1_clk_priv *priv)
1769 {
1770         int p;
1771         u32 stgenc, cntfid0;
1772         ulong rate;
1773
1774         stgenc = STM32_STGEN_BASE;
1775         cntfid0 = readl(stgenc + STGENC_CNTFID0);
1776         p = stm32mp1_clk_get_parent(priv, STGEN_K);
1777         rate = stm32mp1_clk_get(priv, p);
1778
1779         if (cntfid0 != rate) {
1780                 u64 counter;
1781
1782                 log_debug("System Generic Counter (STGEN) update\n");
1783                 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1784                 counter = (u64)readl(stgenc + STGENC_CNTCVL);
1785                 counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
1786                 counter = lldiv(counter * (u64)rate, cntfid0);
1787                 writel((u32)counter, stgenc + STGENC_CNTCVL);
1788                 writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
1789                 writel(rate, stgenc + STGENC_CNTFID0);
1790                 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1791
1792                 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1793
1794                 /* need to update gd->arch.timer_rate_hz with new frequency */
1795                 timer_init();
1796         }
1797 }
1798
1799 static int set_clkdiv(unsigned int clkdiv, u32 address)
1800 {
1801         u32 val;
1802         int ret;
1803
1804         clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1805         ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1806                                  TIMEOUT_200MS);
1807         if (ret)
1808                 log_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1809                         clkdiv, address, readl(address));
1810
1811         return ret;
1812 }
1813
1814 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1815                              u32 clksrc, u32 clkdiv)
1816 {
1817         u32 address = priv->base + (clksrc >> 4);
1818
1819         /*
1820          * binding clksrc : bit15-4 offset
1821          *                  bit3:   disable
1822          *                  bit2-0: MCOSEL[2:0]
1823          */
1824         if (clksrc & 0x8) {
1825                 clrbits_le32(address, RCC_MCOCFG_MCOON);
1826         } else {
1827                 clrsetbits_le32(address,
1828                                 RCC_MCOCFG_MCOSRC_MASK,
1829                                 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1830                 clrsetbits_le32(address,
1831                                 RCC_MCOCFG_MCODIV_MASK,
1832                                 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1833                 setbits_le32(address, RCC_MCOCFG_MCOON);
1834         }
1835 }
1836
1837 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1838                        unsigned int clksrc,
1839                        int lse_css)
1840 {
1841         u32 address = priv->base + RCC_BDCR;
1842
1843         if (readl(address) & RCC_BDCR_RTCCKEN)
1844                 goto skip_rtc;
1845
1846         if (clksrc == CLK_RTC_DISABLED)
1847                 goto skip_rtc;
1848
1849         clrsetbits_le32(address,
1850                         RCC_BDCR_RTCSRC_MASK,
1851                         clksrc << RCC_BDCR_RTCSRC_SHIFT);
1852
1853         setbits_le32(address, RCC_BDCR_RTCCKEN);
1854
1855 skip_rtc:
1856         if (lse_css)
1857                 setbits_le32(address, RCC_BDCR_LSECSSON);
1858 }
1859
1860 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1861 {
1862         u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1863         u32 value = pkcs & 0xF;
1864         u32 mask = 0xF;
1865
1866         if (pkcs & BIT(31)) {
1867                 mask <<= 4;
1868                 value <<= 4;
1869         }
1870         clrsetbits_le32(address, mask, value);
1871 }
1872
1873 static int stm32mp1_clktree(struct udevice *dev)
1874 {
1875         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1876         fdt_addr_t rcc = priv->base;
1877         unsigned int clksrc[CLKSRC_NB];
1878         unsigned int clkdiv[CLKDIV_NB];
1879         unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1880         unsigned int pllfracv[_PLL_NB];
1881         unsigned int pllcsg[_PLL_NB][PLLCSG_NB];
1882         bool pllcfg_valid[_PLL_NB];
1883         bool pllcsg_set[_PLL_NB];
1884         int ret;
1885         int i, len;
1886         int lse_css = 0;
1887         const u32 *pkcs_cell;
1888
1889         /* check mandatory field */
1890         ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1891         if (ret < 0) {
1892                 dev_dbg(dev, "field st,clksrc invalid: error %d\n", ret);
1893                 return -FDT_ERR_NOTFOUND;
1894         }
1895
1896         ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1897         if (ret < 0) {
1898                 dev_dbg(dev, "field st,clkdiv invalid: error %d\n", ret);
1899                 return -FDT_ERR_NOTFOUND;
1900         }
1901
1902         /* check mandatory field in each pll */
1903         for (i = 0; i < _PLL_NB; i++) {
1904                 char name[12];
1905                 ofnode node;
1906
1907                 sprintf(name, "st,pll@%d", i);
1908                 node = dev_read_subnode(dev, name);
1909                 pllcfg_valid[i] = ofnode_valid(node);
1910                 pllcsg_set[i] = false;
1911                 if (pllcfg_valid[i]) {
1912                         dev_dbg(dev, "DT for PLL %d @ %s\n", i, name);
1913                         ret = ofnode_read_u32_array(node, "cfg",
1914                                                     pllcfg[i], PLLCFG_NB);
1915                         if (ret < 0) {
1916                                 dev_dbg(dev, "field cfg invalid: error %d\n", ret);
1917                                 return -FDT_ERR_NOTFOUND;
1918                         }
1919                         pllfracv[i] = ofnode_read_u32_default(node, "frac", 0);
1920
1921                         ret = ofnode_read_u32_array(node, "csg", pllcsg[i],
1922                                                     PLLCSG_NB);
1923                         if (!ret) {
1924                                 pllcsg_set[i] = true;
1925                         } else if (ret != -FDT_ERR_NOTFOUND) {
1926                                 dev_dbg(dev, "invalid csg node for pll@%d res=%d\n",
1927                                         i, ret);
1928                                 return ret;
1929                         }
1930                 } else if (i == _PLL1)  {
1931                         /* use OPP for PLL1 for A7 CPU */
1932                         dev_dbg(dev, "DT for PLL %d with OPP\n", i);
1933                         ret = stm32mp1_pll1_opp(priv,
1934                                                 clksrc[CLKSRC_PLL12],
1935                                                 pllcfg[i],
1936                                                 &pllfracv[i]);
1937                         if (ret) {
1938                                 dev_dbg(dev, "PLL %d with OPP error = %d\n", i, ret);
1939                                 return ret;
1940                         }
1941                         pllcfg_valid[i] = true;
1942                 }
1943         }
1944
1945         dev_dbg(dev, "configuration MCO\n");
1946         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1947         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1948
1949         dev_dbg(dev, "switch ON osillator\n");
1950         /*
1951          * switch ON oscillator found in device-tree,
1952          * HSI already ON after bootrom
1953          */
1954         if (priv->osc[_LSI])
1955                 stm32mp1_lsi_set(rcc, 1);
1956
1957         if (priv->osc[_LSE]) {
1958                 int bypass, digbyp;
1959                 u32 lsedrv;
1960                 struct udevice *dev = priv->osc_dev[_LSE];
1961
1962                 bypass = dev_read_bool(dev, "st,bypass");
1963                 digbyp = dev_read_bool(dev, "st,digbypass");
1964                 lse_css = dev_read_bool(dev, "st,css");
1965                 lsedrv = dev_read_u32_default(dev, "st,drive",
1966                                               LSEDRV_MEDIUM_HIGH);
1967
1968                 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
1969         }
1970
1971         if (priv->osc[_HSE]) {
1972                 int bypass, digbyp, css;
1973                 struct udevice *dev = priv->osc_dev[_HSE];
1974
1975                 bypass = dev_read_bool(dev, "st,bypass");
1976                 digbyp = dev_read_bool(dev, "st,digbypass");
1977                 css = dev_read_bool(dev, "st,css");
1978
1979                 stm32mp1_hse_enable(rcc, bypass, digbyp, css);
1980         }
1981         /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1982          * => switch on CSI even if node is not present in device tree
1983          */
1984         stm32mp1_csi_set(rcc, 1);
1985
1986         /* come back to HSI */
1987         dev_dbg(dev, "come back to HSI\n");
1988         set_clksrc(priv, CLK_MPU_HSI);
1989         set_clksrc(priv, CLK_AXI_HSI);
1990         set_clksrc(priv, CLK_MCU_HSI);
1991
1992         dev_dbg(dev, "pll stop\n");
1993         for (i = 0; i < _PLL_NB; i++)
1994                 pll_stop(priv, i);
1995
1996         /* configure HSIDIV */
1997         dev_dbg(dev, "configure HSIDIV\n");
1998         if (priv->osc[_HSI]) {
1999                 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
2000                 stgen_config(priv);
2001         }
2002
2003         /* select DIV */
2004         dev_dbg(dev, "select DIV\n");
2005         /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
2006         writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
2007         set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
2008         set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
2009         set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
2010         set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
2011         set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
2012         set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
2013         set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
2014
2015         /* no ready bit for RTC */
2016         writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
2017
2018         /* configure PLLs source */
2019         dev_dbg(dev, "configure PLLs source\n");
2020         set_clksrc(priv, clksrc[CLKSRC_PLL12]);
2021         set_clksrc(priv, clksrc[CLKSRC_PLL3]);
2022         set_clksrc(priv, clksrc[CLKSRC_PLL4]);
2023
2024         /* configure and start PLLs */
2025         dev_dbg(dev, "configure PLLs\n");
2026         for (i = 0; i < _PLL_NB; i++) {
2027                 if (!pllcfg_valid[i])
2028                         continue;
2029                 dev_dbg(dev, "configure PLL %d\n", i);
2030                 pll_config(priv, i, pllcfg[i], pllfracv[i]);
2031                 if (pllcsg_set[i])
2032                         pll_csg(priv, i, pllcsg[i]);
2033                 pll_start(priv, i);
2034         }
2035
2036         /* wait and start PLLs ouptut when ready */
2037         for (i = 0; i < _PLL_NB; i++) {
2038                 if (!pllcfg_valid[i])
2039                         continue;
2040                 dev_dbg(dev, "output PLL %d\n", i);
2041                 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
2042         }
2043
2044         /* wait LSE ready before to use it */
2045         if (priv->osc[_LSE])
2046                 stm32mp1_lse_wait(rcc);
2047
2048         /* configure with expected clock source */
2049         dev_dbg(dev, "CLKSRC\n");
2050         set_clksrc(priv, clksrc[CLKSRC_MPU]);
2051         set_clksrc(priv, clksrc[CLKSRC_AXI]);
2052         set_clksrc(priv, clksrc[CLKSRC_MCU]);
2053         set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
2054
2055         /* configure PKCK */
2056         dev_dbg(dev, "PKCK\n");
2057         pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
2058         if (pkcs_cell) {
2059                 bool ckper_disabled = false;
2060
2061                 for (i = 0; i < len / sizeof(u32); i++) {
2062                         u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
2063
2064                         if (pkcs == CLK_CKPER_DISABLED) {
2065                                 ckper_disabled = true;
2066                                 continue;
2067                         }
2068                         pkcs_config(priv, pkcs);
2069                 }
2070                 /* CKPER is source for some peripheral clock
2071                  * (FMC-NAND / QPSI-NOR) and switching source is allowed
2072                  * only if previous clock is still ON
2073                  * => deactivated CKPER only after switching clock
2074                  */
2075                 if (ckper_disabled)
2076                         pkcs_config(priv, CLK_CKPER_DISABLED);
2077         }
2078
2079         /* STGEN clock source can change with CLK_STGEN_XXX */
2080         stgen_config(priv);
2081
2082         dev_dbg(dev, "oscillator off\n");
2083         /* switch OFF HSI if not found in device-tree */
2084         if (!priv->osc[_HSI])
2085                 stm32mp1_hsi_set(rcc, 0);
2086
2087         /* Software Self-Refresh mode (SSR) during DDR initilialization */
2088         clrsetbits_le32(priv->base + RCC_DDRITFCR,
2089                         RCC_DDRITFCR_DDRCKMOD_MASK,
2090                         RCC_DDRITFCR_DDRCKMOD_SSR <<
2091                         RCC_DDRITFCR_DDRCKMOD_SHIFT);
2092
2093         return 0;
2094 }
2095 #endif /* STM32MP1_CLOCK_TREE_INIT */
2096
2097 static int pll_set_output_rate(struct udevice *dev,
2098                                int pll_id,
2099                                int div_id,
2100                                unsigned long clk_rate)
2101 {
2102         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2103         const struct stm32mp1_clk_pll *pll = priv->data->pll;
2104         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
2105         int div;
2106         ulong fvco;
2107
2108         if (div_id > _DIV_NB)
2109                 return -EINVAL;
2110
2111         fvco = pll_get_fvco(priv, pll_id);
2112
2113         if (fvco <= clk_rate)
2114                 div = 1;
2115         else
2116                 div = DIV_ROUND_UP(fvco, clk_rate);
2117
2118         if (div > 128)
2119                 div = 128;
2120
2121         /* stop the requested output */
2122         clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
2123         /* change divider */
2124         clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
2125                         RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
2126                         (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
2127         /* start the requested output */
2128         setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
2129
2130         return 0;
2131 }
2132
2133 static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
2134 {
2135         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
2136         int p;
2137
2138         switch (clk->id) {
2139 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
2140         defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
2141         case DDRPHYC:
2142                 break;
2143 #endif
2144         case LTDC_PX:
2145         case DSI_PX:
2146                 break;
2147         default:
2148                 dev_err(clk->dev, "Set of clk %ld not supported", clk->id);
2149                 return -EINVAL;
2150         }
2151
2152         p = stm32mp1_clk_get_parent(priv, clk->id);
2153         dev_vdbg(clk->dev, "parent = %d:%s\n", p, stm32mp1_clk_parent_name[p]);
2154         if (p < 0)
2155                 return -EINVAL;
2156
2157         switch (p) {
2158 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
2159         defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
2160         case _PLL2_R: /* DDRPHYC */
2161         {
2162                 /* only for change DDR clock in interactive mode */
2163                 ulong result;
2164
2165                 set_clksrc(priv, CLK_AXI_HSI);
2166                 result = pll_set_rate(clk->dev,  _PLL2, _DIV_R, clk_rate);
2167                 set_clksrc(priv, CLK_AXI_PLL2P);
2168                 return result;
2169         }
2170 #endif
2171
2172         case _PLL4_Q:
2173                 /* for LTDC_PX and DSI_PX case */
2174                 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
2175         }
2176
2177         return -EINVAL;
2178 }
2179
2180 static void stm32mp1_osc_clk_init(const char *name,
2181                                   struct stm32mp1_clk_priv *priv,
2182                                   int index)
2183 {
2184         struct clk clk;
2185         struct udevice *dev = NULL;
2186
2187         priv->osc[index] = 0;
2188         clk.id = 0;
2189         if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
2190                 if (clk_request(dev, &clk))
2191                         log_err("%s request", name);
2192                 else
2193                         priv->osc[index] = clk_get_rate(&clk);
2194         }
2195         priv->osc_dev[index] = dev;
2196 }
2197
2198 static void stm32mp1_osc_init(struct udevice *dev)
2199 {
2200         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2201         int i;
2202         const char *name[NB_OSC] = {
2203                 [_LSI] = "clk-lsi",
2204                 [_LSE] = "clk-lse",
2205                 [_HSI] = "clk-hsi",
2206                 [_HSE] = "clk-hse",
2207                 [_CSI] = "clk-csi",
2208                 [_I2S_CKIN] = "i2s_ckin",
2209         };
2210
2211         for (i = 0; i < NB_OSC; i++) {
2212                 stm32mp1_osc_clk_init(name[i], priv, i);
2213                 dev_dbg(dev, "%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
2214         }
2215 }
2216
2217 static void  __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
2218 {
2219         char buf[32];
2220         int i, s, p;
2221
2222         printf("Clocks:\n");
2223         for (i = 0; i < _PARENT_NB; i++) {
2224                 printf("- %s : %s MHz\n",
2225                        stm32mp1_clk_parent_name[i],
2226                        strmhz(buf, stm32mp1_clk_get(priv, i)));
2227         }
2228         printf("Source Clocks:\n");
2229         for (i = 0; i < _PARENT_SEL_NB; i++) {
2230                 p = (readl(priv->base + priv->data->sel[i].offset) >>
2231                      priv->data->sel[i].src) & priv->data->sel[i].msk;
2232                 if (p < priv->data->sel[i].nb_parent) {
2233                         s = priv->data->sel[i].parent[p];
2234                         printf("- %s(%d) => parent %s(%d)\n",
2235                                stm32mp1_clk_parent_sel_name[i], i,
2236                                stm32mp1_clk_parent_name[s], s);
2237                 } else {
2238                         printf("- %s(%d) => parent index %d is invalid\n",
2239                                stm32mp1_clk_parent_sel_name[i], i, p);
2240                 }
2241         }
2242 }
2243
2244 #ifdef CONFIG_CMD_CLK
2245 int soc_clk_dump(void)
2246 {
2247         struct udevice *dev;
2248         struct stm32mp1_clk_priv *priv;
2249         int ret;
2250
2251         ret = uclass_get_device_by_driver(UCLASS_CLK,
2252                                           DM_DRIVER_GET(stm32mp1_clock),
2253                                           &dev);
2254         if (ret)
2255                 return ret;
2256
2257         priv = dev_get_priv(dev);
2258
2259         stm32mp1_clk_dump(priv);
2260
2261         return 0;
2262 }
2263 #endif
2264
2265 static int stm32mp1_clk_probe(struct udevice *dev)
2266 {
2267         int result = 0;
2268         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2269
2270         priv->base = dev_read_addr(dev->parent);
2271         if (priv->base == FDT_ADDR_T_NONE)
2272                 return -EINVAL;
2273
2274         priv->data = (void *)&stm32mp1_data;
2275
2276         if (!priv->data->gate || !priv->data->sel ||
2277             !priv->data->pll)
2278                 return -EINVAL;
2279
2280         stm32mp1_osc_init(dev);
2281
2282 #ifdef STM32MP1_CLOCK_TREE_INIT
2283         /* clock tree init is done only one time, before relocation */
2284         if (!(gd->flags & GD_FLG_RELOC))
2285                 result = stm32mp1_clktree(dev);
2286         if (result)
2287                 dev_err(dev, "clock tree initialization failed (%d)\n", result);
2288 #endif
2289
2290 #ifndef CONFIG_SPL_BUILD
2291 #if defined(VERBOSE_DEBUG)
2292         /* display debug information for probe after relocation */
2293         if (gd->flags & GD_FLG_RELOC)
2294                 stm32mp1_clk_dump(priv);
2295 #endif
2296
2297         gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU);
2298         gd->bus_clk = stm32mp1_clk_get(priv, _ACLK);
2299         /* DDRPHYC father */
2300         gd->mem_clk = stm32mp1_clk_get(priv, _PLL2_R);
2301 #if defined(CONFIG_DISPLAY_CPUINFO)
2302         if (gd->flags & GD_FLG_RELOC) {
2303                 char buf[32];
2304
2305                 log_info("Clocks:\n");
2306                 log_info("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
2307                 log_info("- MCU : %s MHz\n",
2308                          strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
2309                 log_info("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
2310                 log_info("- PER : %s MHz\n",
2311                          strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
2312                 log_info("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
2313         }
2314 #endif /* CONFIG_DISPLAY_CPUINFO */
2315 #endif
2316
2317         return result;
2318 }
2319
2320 static const struct clk_ops stm32mp1_clk_ops = {
2321         .enable = stm32mp1_clk_enable,
2322         .disable = stm32mp1_clk_disable,
2323         .get_rate = stm32mp1_clk_get_rate,
2324         .set_rate = stm32mp1_clk_set_rate,
2325 };
2326
2327 U_BOOT_DRIVER(stm32mp1_clock) = {
2328         .name = "stm32mp1_clk",
2329         .id = UCLASS_CLK,
2330         .ops = &stm32mp1_clk_ops,
2331         .priv_auto      = sizeof(struct stm32mp1_clk_priv),
2332         .probe = stm32mp1_clk_probe,
2333 };