drivers/clk/clk_stm32mp1.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk-uclass.h>
   8 #include <div64.h>
   9 #include <dm.h>
  10 #include <init.h>
  11 #include <log.h>
  12 #include <regmap.h>
  13 #include <spl.h>
  14 #include <syscon.h>
  15 #include <time.h>
  16 #include <vsprintf.h>
  17 #include <linux/bitops.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <dt-bindings/clock/stm32mp1-clks.h>
  21 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #ifndef CONFIG_TFABOOT
  26 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  27 /* activate clock tree initialization in the driver */
  28 #define STM32MP1_CLOCK_TREE_INIT
  29 #endif
  30 #endif
  31
  32 #define MAX_HSI_HZ              64000000
  33
  34 /* TIMEOUT */
  35 #define TIMEOUT_200MS           200000
  36 #define TIMEOUT_1S              1000000
  37
  38 /* STGEN registers */
  39 #define STGENC_CNTCR            0x00
  40 #define STGENC_CNTSR            0x04
  41 #define STGENC_CNTCVL           0x08
  42 #define STGENC_CNTCVU           0x0C
  43 #define STGENC_CNTFID0          0x20
  44
  45 #define STGENC_CNTCR_EN         BIT(0)
  46
  47 /* RCC registers */
  48 #define RCC_OCENSETR            0x0C
  49 #define RCC_OCENCLRR            0x10
  50 #define RCC_HSICFGR             0x18
  51 #define RCC_MPCKSELR            0x20
  52 #define RCC_ASSCKSELR           0x24
  53 #define RCC_RCK12SELR           0x28
  54 #define RCC_MPCKDIVR            0x2C
  55 #define RCC_AXIDIVR             0x30
  56 #define RCC_APB4DIVR            0x3C
  57 #define RCC_APB5DIVR            0x40
  58 #define RCC_RTCDIVR             0x44
  59 #define RCC_MSSCKSELR           0x48
  60 #define RCC_PLL1CR              0x80
  61 #define RCC_PLL1CFGR1           0x84
  62 #define RCC_PLL1CFGR2           0x88
  63 #define RCC_PLL1FRACR           0x8C
  64 #define RCC_PLL1CSGR            0x90
  65 #define RCC_PLL2CR              0x94
  66 #define RCC_PLL2CFGR1           0x98
  67 #define RCC_PLL2CFGR2           0x9C
  68 #define RCC_PLL2FRACR           0xA0
  69 #define RCC_PLL2CSGR            0xA4
  70 #define RCC_I2C46CKSELR         0xC0
  71 #define RCC_CPERCKSELR          0xD0
  72 #define RCC_STGENCKSELR         0xD4
  73 #define RCC_DDRITFCR            0xD8
  74 #define RCC_BDCR                0x140
  75 #define RCC_RDLSICR             0x144
  76 #define RCC_MP_APB4ENSETR       0x200
  77 #define RCC_MP_APB5ENSETR       0x208
  78 #define RCC_MP_AHB5ENSETR       0x210
  79 #define RCC_MP_AHB6ENSETR       0x218
  80 #define RCC_OCRDYR              0x808
  81 #define RCC_DBGCFGR             0x80C
  82 #define RCC_RCK3SELR            0x820
  83 #define RCC_RCK4SELR            0x824
  84 #define RCC_MCUDIVR             0x830
  85 #define RCC_APB1DIVR            0x834
  86 #define RCC_APB2DIVR            0x838
  87 #define RCC_APB3DIVR            0x83C
  88 #define RCC_PLL3CR              0x880
  89 #define RCC_PLL3CFGR1           0x884
  90 #define RCC_PLL3CFGR2           0x888
  91 #define RCC_PLL3FRACR           0x88C
  92 #define RCC_PLL3CSGR            0x890
  93 #define RCC_PLL4CR              0x894
  94 #define RCC_PLL4CFGR1           0x898
  95 #define RCC_PLL4CFGR2           0x89C
  96 #define RCC_PLL4FRACR           0x8A0
  97 #define RCC_PLL4CSGR            0x8A4
  98 #define RCC_I2C12CKSELR         0x8C0
  99 #define RCC_I2C35CKSELR         0x8C4
 100 #define RCC_SPI2S1CKSELR        0x8D8
 101 #define RCC_SPI45CKSELR         0x8E0
 102 #define RCC_UART6CKSELR         0x8E4
 103 #define RCC_UART24CKSELR        0x8E8
 104 #define RCC_UART35CKSELR        0x8EC
 105 #define RCC_UART78CKSELR        0x8F0
 106 #define RCC_SDMMC12CKSELR       0x8F4
 107 #define RCC_SDMMC3CKSELR        0x8F8
 108 #define RCC_ETHCKSELR           0x8FC
 109 #define RCC_QSPICKSELR          0x900
 110 #define RCC_FMCCKSELR           0x904
 111 #define RCC_USBCKSELR           0x91C
 112 #define RCC_DSICKSELR           0x924
 113 #define RCC_ADCCKSELR           0x928
 114 #define RCC_MP_APB1ENSETR       0xA00
 115 #define RCC_MP_APB2ENSETR       0XA08
 116 #define RCC_MP_APB3ENSETR       0xA10
 117 #define RCC_MP_AHB2ENSETR       0xA18
 118 #define RCC_MP_AHB3ENSETR       0xA20
 119 #define RCC_MP_AHB4ENSETR       0xA28
 120
 121 /* used for most of SELR register */
 122 #define RCC_SELR_SRC_MASK       GENMASK(2, 0)
 123 #define RCC_SELR_SRCRDY         BIT(31)
 124
 125 /* Values of RCC_MPCKSELR register */
 126 #define RCC_MPCKSELR_HSI        0
 127 #define RCC_MPCKSELR_HSE        1
 128 #define RCC_MPCKSELR_PLL        2
 129 #define RCC_MPCKSELR_PLL_MPUDIV 3
 130
 131 /* Values of RCC_ASSCKSELR register */
 132 #define RCC_ASSCKSELR_HSI       0
 133 #define RCC_ASSCKSELR_HSE       1
 134 #define RCC_ASSCKSELR_PLL       2
 135
 136 /* Values of RCC_MSSCKSELR register */
 137 #define RCC_MSSCKSELR_HSI       0
 138 #define RCC_MSSCKSELR_HSE       1
 139 #define RCC_MSSCKSELR_CSI       2
 140 #define RCC_MSSCKSELR_PLL       3
 141
 142 /* Values of RCC_CPERCKSELR register */
 143 #define RCC_CPERCKSELR_HSI      0
 144 #define RCC_CPERCKSELR_CSI      1
 145 #define RCC_CPERCKSELR_HSE      2
 146
 147 /* used for most of DIVR register : max div for RTC */
 148 #define RCC_DIVR_DIV_MASK       GENMASK(5, 0)
 149 #define RCC_DIVR_DIVRDY         BIT(31)
 150
 151 /* Masks for specific DIVR registers */
 152 #define RCC_APBXDIV_MASK        GENMASK(2, 0)
 153 #define RCC_MPUDIV_MASK         GENMASK(2, 0)
 154 #define RCC_AXIDIV_MASK         GENMASK(2, 0)
 155 #define RCC_MCUDIV_MASK         GENMASK(3, 0)
 156
 157 /*  offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
 158 #define RCC_MP_ENCLRR_OFFSET    4
 159
 160 /* Fields of RCC_BDCR register */
 161 #define RCC_BDCR_LSEON          BIT(0)
 162 #define RCC_BDCR_LSEBYP         BIT(1)
 163 #define RCC_BDCR_LSERDY         BIT(2)
 164 #define RCC_BDCR_DIGBYP         BIT(3)
 165 #define RCC_BDCR_LSEDRV_MASK    GENMASK(5, 4)
 166 #define RCC_BDCR_LSEDRV_SHIFT   4
 167 #define RCC_BDCR_LSECSSON       BIT(8)
 168 #define RCC_BDCR_RTCCKEN        BIT(20)
 169 #define RCC_BDCR_RTCSRC_MASK    GENMASK(17, 16)
 170 #define RCC_BDCR_RTCSRC_SHIFT   16
 171
 172 /* Fields of RCC_RDLSICR register */
 173 #define RCC_RDLSICR_LSION       BIT(0)
 174 #define RCC_RDLSICR_LSIRDY      BIT(1)
 175
 176 /* used for ALL PLLNCR registers */
 177 #define RCC_PLLNCR_PLLON        BIT(0)
 178 #define RCC_PLLNCR_PLLRDY       BIT(1)
 179 #define RCC_PLLNCR_SSCG_CTRL    BIT(2)
 180 #define RCC_PLLNCR_DIVPEN       BIT(4)
 181 #define RCC_PLLNCR_DIVQEN       BIT(5)
 182 #define RCC_PLLNCR_DIVREN       BIT(6)
 183 #define RCC_PLLNCR_DIVEN_SHIFT  4
 184
 185 /* used for ALL PLLNCFGR1 registers */
 186 #define RCC_PLLNCFGR1_DIVM_SHIFT        16
 187 #define RCC_PLLNCFGR1_DIVM_MASK         GENMASK(21, 16)
 188 #define RCC_PLLNCFGR1_DIVN_SHIFT        0
 189 #define RCC_PLLNCFGR1_DIVN_MASK         GENMASK(8, 0)
 190 /* only for PLL3 and PLL4 */
 191 #define RCC_PLLNCFGR1_IFRGE_SHIFT       24
 192 #define RCC_PLLNCFGR1_IFRGE_MASK        GENMASK(25, 24)
 193
 194 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
 195 #define RCC_PLLNCFGR2_SHIFT(div_id)     ((div_id) * 8)
 196 #define RCC_PLLNCFGR2_DIVX_MASK         GENMASK(6, 0)
 197 #define RCC_PLLNCFGR2_DIVP_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_P)
 198 #define RCC_PLLNCFGR2_DIVP_MASK         GENMASK(6, 0)
 199 #define RCC_PLLNCFGR2_DIVQ_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_Q)
 200 #define RCC_PLLNCFGR2_DIVQ_MASK         GENMASK(14, 8)
 201 #define RCC_PLLNCFGR2_DIVR_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_R)
 202 #define RCC_PLLNCFGR2_DIVR_MASK         GENMASK(22, 16)
 203
 204 /* used for ALL PLLNFRACR registers */
 205 #define RCC_PLLNFRACR_FRACV_SHIFT       3
 206 #define RCC_PLLNFRACR_FRACV_MASK        GENMASK(15, 3)
 207 #define RCC_PLLNFRACR_FRACLE            BIT(16)
 208
 209 /* used for ALL PLLNCSGR registers */
 210 #define RCC_PLLNCSGR_INC_STEP_SHIFT     16
 211 #define RCC_PLLNCSGR_INC_STEP_MASK      GENMASK(30, 16)
 212 #define RCC_PLLNCSGR_MOD_PER_SHIFT      0
 213 #define RCC_PLLNCSGR_MOD_PER_MASK       GENMASK(12, 0)
 214 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT    15
 215 #define RCC_PLLNCSGR_SSCG_MODE_MASK     BIT(15)
 216
 217 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
 218 #define RCC_OCENR_HSION                 BIT(0)
 219 #define RCC_OCENR_CSION                 BIT(4)
 220 #define RCC_OCENR_DIGBYP                BIT(7)
 221 #define RCC_OCENR_HSEON                 BIT(8)
 222 #define RCC_OCENR_HSEBYP                BIT(10)
 223 #define RCC_OCENR_HSECSSON              BIT(11)
 224
 225 /* Fields of RCC_OCRDYR register */
 226 #define RCC_OCRDYR_HSIRDY               BIT(0)
 227 #define RCC_OCRDYR_HSIDIVRDY            BIT(2)
 228 #define RCC_OCRDYR_CSIRDY               BIT(4)
 229 #define RCC_OCRDYR_HSERDY               BIT(8)
 230
 231 /* Fields of DDRITFCR register */
 232 #define RCC_DDRITFCR_DDRCKMOD_MASK      GENMASK(22, 20)
 233 #define RCC_DDRITFCR_DDRCKMOD_SHIFT     20
 234 #define RCC_DDRITFCR_DDRCKMOD_SSR       0
 235
 236 /* Fields of RCC_HSICFGR register */
 237 #define RCC_HSICFGR_HSIDIV_MASK         GENMASK(1, 0)
 238
 239 /* used for MCO related operations */
 240 #define RCC_MCOCFG_MCOON                BIT(12)
 241 #define RCC_MCOCFG_MCODIV_MASK          GENMASK(7, 4)
 242 #define RCC_MCOCFG_MCODIV_SHIFT         4
 243 #define RCC_MCOCFG_MCOSRC_MASK          GENMASK(2, 0)
 244
 245 enum stm32mp1_parent_id {
 246 /*
 247  * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
 248  * they are used as index in osc[] as entry point
 249  */
 250         _HSI,
 251         _HSE,
 252         _CSI,
 253         _LSI,
 254         _LSE,
 255         _I2S_CKIN,
 256         NB_OSC,
 257
 258 /* other parent source */
 259         _HSI_KER = NB_OSC,
 260         _HSE_KER,
 261         _HSE_KER_DIV2,
 262         _CSI_KER,
 263         _PLL1_P,
 264         _PLL1_Q,
 265         _PLL1_R,
 266         _PLL2_P,
 267         _PLL2_Q,
 268         _PLL2_R,
 269         _PLL3_P,
 270         _PLL3_Q,
 271         _PLL3_R,
 272         _PLL4_P,
 273         _PLL4_Q,
 274         _PLL4_R,
 275         _ACLK,
 276         _PCLK1,
 277         _PCLK2,
 278         _PCLK3,
 279         _PCLK4,
 280         _PCLK5,
 281         _HCLK6,
 282         _HCLK2,
 283         _CK_PER,
 284         _CK_MPU,
 285         _CK_MCU,
 286         _DSI_PHY,
 287         _USB_PHY_48,
 288         _PARENT_NB,
 289         _UNKNOWN_ID = 0xff,
 290 };
 291
 292 enum stm32mp1_parent_sel {
 293         _I2C12_SEL,
 294         _I2C35_SEL,
 295         _I2C46_SEL,
 296         _UART6_SEL,
 297         _UART24_SEL,
 298         _UART35_SEL,
 299         _UART78_SEL,
 300         _SDMMC12_SEL,
 301         _SDMMC3_SEL,
 302         _ETH_SEL,
 303         _QSPI_SEL,
 304         _FMC_SEL,
 305         _USBPHY_SEL,
 306         _USBO_SEL,
 307         _STGEN_SEL,
 308         _DSI_SEL,
 309         _ADC12_SEL,
 310         _SPI1_SEL,
 311         _SPI45_SEL,
 312         _RTC_SEL,
 313         _PARENT_SEL_NB,
 314         _UNKNOWN_SEL = 0xff,
 315 };
 316
 317 enum stm32mp1_pll_id {
 318         _PLL1,
 319         _PLL2,
 320         _PLL3,
 321         _PLL4,
 322         _PLL_NB
 323 };
 324
 325 enum stm32mp1_div_id {
 326         _DIV_P,
 327         _DIV_Q,
 328         _DIV_R,
 329         _DIV_NB,
 330 };
 331
 332 enum stm32mp1_clksrc_id {
 333         CLKSRC_MPU,
 334         CLKSRC_AXI,
 335         CLKSRC_MCU,
 336         CLKSRC_PLL12,
 337         CLKSRC_PLL3,
 338         CLKSRC_PLL4,
 339         CLKSRC_RTC,
 340         CLKSRC_MCO1,
 341         CLKSRC_MCO2,
 342         CLKSRC_NB
 343 };
 344
 345 enum stm32mp1_clkdiv_id {
 346         CLKDIV_MPU,
 347         CLKDIV_AXI,
 348         CLKDIV_MCU,
 349         CLKDIV_APB1,
 350         CLKDIV_APB2,
 351         CLKDIV_APB3,
 352         CLKDIV_APB4,
 353         CLKDIV_APB5,
 354         CLKDIV_RTC,
 355         CLKDIV_MCO1,
 356         CLKDIV_MCO2,
 357         CLKDIV_NB
 358 };
 359
 360 enum stm32mp1_pllcfg {
 361         PLLCFG_M,
 362         PLLCFG_N,
 363         PLLCFG_P,
 364         PLLCFG_Q,
 365         PLLCFG_R,
 366         PLLCFG_O,
 367         PLLCFG_NB
 368 };
 369
 370 enum stm32mp1_pllcsg {
 371         PLLCSG_MOD_PER,
 372         PLLCSG_INC_STEP,
 373         PLLCSG_SSCG_MODE,
 374         PLLCSG_NB
 375 };
 376
 377 enum stm32mp1_plltype {
 378         PLL_800,
 379         PLL_1600,
 380         PLL_TYPE_NB
 381 };
 382
 383 struct stm32mp1_pll {
 384         u8 refclk_min;
 385         u8 refclk_max;
 386         u8 divn_max;
 387 };
 388
 389 struct stm32mp1_clk_gate {
 390         u16 offset;
 391         u8 bit;
 392         u8 index;
 393         u8 set_clr;
 394         u8 sel;
 395         u8 fixed;
 396 };
 397
 398 struct stm32mp1_clk_sel {
 399         u16 offset;
 400         u8 src;
 401         u8 msk;
 402         u8 nb_parent;
 403         const u8 *parent;
 404 };
 405
 406 #define REFCLK_SIZE 4
 407 struct stm32mp1_clk_pll {
 408         enum stm32mp1_plltype plltype;
 409         u16 rckxselr;
 410         u16 pllxcfgr1;
 411         u16 pllxcfgr2;
 412         u16 pllxfracr;
 413         u16 pllxcr;
 414         u16 pllxcsgr;
 415         u8 refclk[REFCLK_SIZE];
 416 };
 417
 418 struct stm32mp1_clk_data {
 419         const struct stm32mp1_clk_gate *gate;
 420         const struct stm32mp1_clk_sel *sel;
 421         const struct stm32mp1_clk_pll *pll;
 422         const int nb_gate;
 423 };
 424
 425 struct stm32mp1_clk_priv {
 426         fdt_addr_t base;
 427         const struct stm32mp1_clk_data *data;
 428         ulong osc[NB_OSC];
 429         struct udevice *osc_dev[NB_OSC];
 430 };
 431
 432 #define STM32MP1_CLK(off, b, idx, s)            \
 433         {                                       \
 434                 .offset = (off),                \
 435                 .bit = (b),                     \
 436                 .index = (idx),                 \
 437                 .set_clr = 0,                   \
 438                 .sel = (s),                     \
 439                 .fixed = _UNKNOWN_ID,           \
 440         }
 441
 442 #define STM32MP1_CLK_F(off, b, idx, f)          \
 443         {                                       \
 444                 .offset = (off),                \
 445                 .bit = (b),                     \
 446                 .index = (idx),                 \
 447                 .set_clr = 0,                   \
 448                 .sel = _UNKNOWN_SEL,            \
 449                 .fixed = (f),                   \
 450         }
 451
 452 #define STM32MP1_CLK_SET_CLR(off, b, idx, s)    \
 453         {                                       \
 454                 .offset = (off),                \
 455                 .bit = (b),                     \
 456                 .index = (idx),                 \
 457                 .set_clr = 1,                   \
 458                 .sel = (s),                     \
 459                 .fixed = _UNKNOWN_ID,           \
 460         }
 461
 462 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f)  \
 463         {                                       \
 464                 .offset = (off),                \
 465                 .bit = (b),                     \
 466                 .index = (idx),                 \
 467                 .set_clr = 1,                   \
 468                 .sel = _UNKNOWN_SEL,            \
 469                 .fixed = (f),                   \
 470         }
 471
 472 #define STM32MP1_CLK_PARENT(idx, off, s, m, p)   \
 473         [(idx)] = {                             \
 474                 .offset = (off),                \
 475                 .src = (s),                     \
 476                 .msk = (m),                     \
 477                 .parent = (p),                  \
 478                 .nb_parent = ARRAY_SIZE((p))    \
 479         }
 480
 481 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
 482                         p1, p2, p3, p4) \
 483         [(idx)] = {                             \
 484                 .plltype = (type),                      \
 485                 .rckxselr = (off1),             \
 486                 .pllxcfgr1 = (off2),            \
 487                 .pllxcfgr2 = (off3),            \
 488                 .pllxfracr = (off4),            \
 489                 .pllxcr = (off5),               \
 490                 .pllxcsgr = (off6),             \
 491                 .refclk[0] = (p1),              \
 492                 .refclk[1] = (p2),              \
 493                 .refclk[2] = (p3),              \
 494                 .refclk[3] = (p4),              \
 495         }
 496
 497 static const u8 stm32mp1_clks[][2] = {
 498         {CK_PER, _CK_PER},
 499         {CK_MPU, _CK_MPU},
 500         {CK_AXI, _ACLK},
 501         {CK_MCU, _CK_MCU},
 502         {CK_HSE, _HSE},
 503         {CK_CSI, _CSI},
 504         {CK_LSI, _LSI},
 505         {CK_LSE, _LSE},
 506         {CK_HSI, _HSI},
 507         {CK_HSE_DIV2, _HSE_KER_DIV2},
 508 };
 509
 510 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 511         STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
 512         STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
 513         STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
 514         STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
 515         STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
 516         STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
 517         STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
 518         STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
 519         STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
 520         STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
 521         STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
 522
 523         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
 524         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
 525         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
 526         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
 527         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
 528         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
 529         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
 530         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
 531         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
 532         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
 533
 534         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
 535         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL),
 536         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 537
 538         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
 539
 540         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
 541         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
 542         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
 543         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
 544         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
 545         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
 546
 547         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
 548         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
 549         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
 550
 551         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
 552         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
 553         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
 554         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
 555
 556         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
 557         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
 558
 559         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
 560         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
 561         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
 562         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
 563         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
 564         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
 565         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
 566         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
 567         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
 568         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
 569         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 570
 571         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
 572         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _UNKNOWN_SEL),
 573
 574         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
 575         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
 576         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
 577         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
 578         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
 579         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
 580         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
 581         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
 582         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
 583
 584         STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
 585
 586         STM32MP1_CLK(RCC_BDCR, 20, RTC, _RTC_SEL),
 587 };
 588
 589 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 590 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 591 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
 592 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
 593                                         _HSE_KER};
 594 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 595                                          _HSE_KER};
 596 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 597                                          _HSE_KER};
 598 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 599                                          _HSE_KER};
 600 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
 601 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
 602 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
 603 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 604 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 605 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
 606 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
 607 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
 608 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
 609 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
 610 static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
 611                                  _PLL3_R};
 612 static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
 613                                    _HSE_KER};
 614 static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
 615
 616 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
 617         STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
 618         STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
 619         STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
 620         STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
 621         STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
 622                             uart24_parents),
 623         STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
 624                             uart35_parents),
 625         STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
 626                             uart78_parents),
 627         STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
 628                             sdmmc12_parents),
 629         STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
 630                             sdmmc3_parents),
 631         STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
 632         STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0x3, qspi_parents),
 633         STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0x3, fmc_parents),
 634         STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
 635         STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
 636         STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
 637         STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
 638         STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents),
 639         STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
 640         STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents),
 641         STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
 642                             (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
 643                             rtc_parents),
 644 };
 645
 646 #ifdef STM32MP1_CLOCK_TREE_INIT
 647 /* define characteristic of PLL according type */
 648 #define DIVN_MIN        24
 649 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
 650         [PLL_800] = {
 651                 .refclk_min = 4,
 652                 .refclk_max = 16,
 653                 .divn_max = 99,
 654                 },
 655         [PLL_1600] = {
 656                 .refclk_min = 8,
 657                 .refclk_max = 16,
 658                 .divn_max = 199,
 659                 },
 660 };
 661 #endif /* STM32MP1_CLOCK_TREE_INIT */
 662
 663 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
 664         STM32MP1_CLK_PLL(_PLL1, PLL_1600,
 665                          RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
 666                          RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
 667                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 668         STM32MP1_CLK_PLL(_PLL2, PLL_1600,
 669                          RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
 670                          RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
 671                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 672         STM32MP1_CLK_PLL(_PLL3, PLL_800,
 673                          RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
 674                          RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
 675                          _HSI, _HSE, _CSI, _UNKNOWN_ID),
 676         STM32MP1_CLK_PLL(_PLL4, PLL_800,
 677                          RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
 678                          RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
 679                          _HSI, _HSE, _CSI, _I2S_CKIN),
 680 };
 681
 682 /* Prescaler table lookups for clock computation */
 683 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
 684 static const u8 stm32mp1_mcu_div[16] = {
 685         0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
 686 };
 687
 688 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
 689 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
 690 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
 691 static const u8 stm32mp1_mpu_apbx_div[8] = {
 692         0, 1, 2, 3, 4, 4, 4, 4
 693 };
 694
 695 /* div = /1 /2 /3 /4 */
 696 static const u8 stm32mp1_axi_div[8] = {
 697         1, 2, 3, 4, 4, 4, 4, 4
 698 };
 699
 700 static const __maybe_unused
 701 char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
 702         [_HSI] = "HSI",
 703         [_HSE] = "HSE",
 704         [_CSI] = "CSI",
 705         [_LSI] = "LSI",
 706         [_LSE] = "LSE",
 707         [_I2S_CKIN] = "I2S_CKIN",
 708         [_HSI_KER] = "HSI_KER",
 709         [_HSE_KER] = "HSE_KER",
 710         [_HSE_KER_DIV2] = "HSE_KER_DIV2",
 711         [_CSI_KER] = "CSI_KER",
 712         [_PLL1_P] = "PLL1_P",
 713         [_PLL1_Q] = "PLL1_Q",
 714         [_PLL1_R] = "PLL1_R",
 715         [_PLL2_P] = "PLL2_P",
 716         [_PLL2_Q] = "PLL2_Q",
 717         [_PLL2_R] = "PLL2_R",
 718         [_PLL3_P] = "PLL3_P",
 719         [_PLL3_Q] = "PLL3_Q",
 720         [_PLL3_R] = "PLL3_R",
 721         [_PLL4_P] = "PLL4_P",
 722         [_PLL4_Q] = "PLL4_Q",
 723         [_PLL4_R] = "PLL4_R",
 724         [_ACLK] = "ACLK",
 725         [_PCLK1] = "PCLK1",
 726         [_PCLK2] = "PCLK2",
 727         [_PCLK3] = "PCLK3",
 728         [_PCLK4] = "PCLK4",
 729         [_PCLK5] = "PCLK5",
 730         [_HCLK6] = "KCLK6",
 731         [_HCLK2] = "HCLK2",
 732         [_CK_PER] = "CK_PER",
 733         [_CK_MPU] = "CK_MPU",
 734         [_CK_MCU] = "CK_MCU",
 735         [_USB_PHY_48] = "USB_PHY_48",
 736         [_DSI_PHY] = "DSI_PHY_PLL",
 737 };
 738
 739 static const __maybe_unused
 740 char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
 741         [_I2C12_SEL] = "I2C12",
 742         [_I2C35_SEL] = "I2C35",
 743         [_I2C46_SEL] = "I2C46",
 744         [_UART6_SEL] = "UART6",
 745         [_UART24_SEL] = "UART24",
 746         [_UART35_SEL] = "UART35",
 747         [_UART78_SEL] = "UART78",
 748         [_SDMMC12_SEL] = "SDMMC12",
 749         [_SDMMC3_SEL] = "SDMMC3",
 750         [_ETH_SEL] = "ETH",
 751         [_QSPI_SEL] = "QSPI",
 752         [_FMC_SEL] = "FMC",
 753         [_USBPHY_SEL] = "USBPHY",
 754         [_USBO_SEL] = "USBO",
 755         [_STGEN_SEL] = "STGEN",
 756         [_DSI_SEL] = "DSI",
 757         [_ADC12_SEL] = "ADC12",
 758         [_SPI1_SEL] = "SPI1",
 759         [_SPI45_SEL] = "SPI45",
 760         [_RTC_SEL] = "RTC",
 761 };
 762
 763 static const struct stm32mp1_clk_data stm32mp1_data = {
 764         .gate = stm32mp1_clk_gate,
 765         .sel = stm32mp1_clk_sel,
 766         .pll = stm32mp1_clk_pll,
 767         .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
 768 };
 769
 770 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
 771 {
 772         if (idx >= NB_OSC) {
 773                 debug("%s: clk id %d not found\n", __func__, idx);
 774                 return 0;
 775         }
 776
 777         return priv->osc[idx];
 778 }
 779
 780 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
 781 {
 782         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 783         int i, nb_clks = priv->data->nb_gate;
 784
 785         for (i = 0; i < nb_clks; i++) {
 786                 if (gate[i].index == id)
 787                         break;
 788         }
 789
 790         if (i == nb_clks) {
 791                 printf("%s: clk id %d not found\n", __func__, (u32)id);
 792                 return -EINVAL;
 793         }
 794
 795         return i;
 796 }
 797
 798 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
 799                                 int i)
 800 {
 801         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 802
 803         if (gate[i].sel > _PARENT_SEL_NB) {
 804                 printf("%s: parents for clk id %d not found\n",
 805                        __func__, i);
 806                 return -EINVAL;
 807         }
 808
 809         return gate[i].sel;
 810 }
 811
 812 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
 813                                          int i)
 814 {
 815         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 816
 817         if (gate[i].fixed == _UNKNOWN_ID)
 818                 return -ENOENT;
 819
 820         return gate[i].fixed;
 821 }
 822
 823 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
 824                                    unsigned long id)
 825 {
 826         const struct stm32mp1_clk_sel *sel = priv->data->sel;
 827         int i;
 828         int s, p;
 829         unsigned int idx;
 830
 831         for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++)
 832                 if (stm32mp1_clks[idx][0] == id)
 833                         return stm32mp1_clks[idx][1];
 834
 835         i = stm32mp1_clk_get_id(priv, id);
 836         if (i < 0)
 837                 return i;
 838
 839         p = stm32mp1_clk_get_fixed_parent(priv, i);
 840         if (p >= 0 && p < _PARENT_NB)
 841                 return p;
 842
 843         s = stm32mp1_clk_get_sel(priv, i);
 844         if (s < 0)
 845                 return s;
 846
 847         p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
 848
 849         if (p < sel[s].nb_parent) {
 850 #ifdef DEBUG
 851                 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
 852                       stm32mp1_clk_parent_name[sel[s].parent[p]],
 853                       stm32mp1_clk_parent_sel_name[s],
 854                       (u32)id);
 855 #endif
 856                 return sel[s].parent[p];
 857         }
 858
 859         pr_err("%s: no parents defined for clk id %d\n",
 860                __func__, (u32)id);
 861
 862         return -EINVAL;
 863 }
 864
 865 static ulong  pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
 866                               int pll_id)
 867 {
 868         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 869         u32 selr;
 870         int src;
 871         ulong refclk;
 872
 873         /* Get current refclk */
 874         selr = readl(priv->base + pll[pll_id].rckxselr);
 875         src = selr & RCC_SELR_SRC_MASK;
 876
 877         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
 878
 879         return refclk;
 880 }
 881
 882 /*
 883  * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
 884  * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
 885  * - PLL3 & PLL4 => return VCO     with Fpll_y_ck = FVCO / (DIVy + 1)
 886  * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
 887  */
 888 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
 889                           int pll_id)
 890 {
 891         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 892         int divm, divn;
 893         ulong refclk, fvco;
 894         u32 cfgr1, fracr;
 895
 896         cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
 897         fracr = readl(priv->base + pll[pll_id].pllxfracr);
 898
 899         divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
 900         divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
 901
 902         refclk = pll_get_fref_ck(priv, pll_id);
 903
 904         /* with FRACV :
 905          *   Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
 906          * without FRACV
 907          *   Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
 908          */
 909         if (fracr & RCC_PLLNFRACR_FRACLE) {
 910                 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
 911                             >> RCC_PLLNFRACR_FRACV_SHIFT;
 912                 fvco = (ulong)lldiv((unsigned long long)refclk *
 913                                      (((divn + 1) << 13) + fracv),
 914                                      ((unsigned long long)(divm + 1)) << 13);
 915         } else {
 916                 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
 917         }
 918
 919         return fvco;
 920 }
 921
 922 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
 923                                     int pll_id, int div_id)
 924 {
 925         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 926         int divy;
 927         ulong dfout;
 928         u32 cfgr2;
 929
 930         if (div_id >= _DIV_NB)
 931                 return 0;
 932
 933         cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
 934         divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
 935
 936         dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
 937
 938         return dfout;
 939 }
 940
 941 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
 942 {
 943         u32 reg;
 944         ulong clock = 0;
 945
 946         switch (p) {
 947         case _CK_MPU:
 948         /* MPU sub system */
 949                 reg = readl(priv->base + RCC_MPCKSELR);
 950                 switch (reg & RCC_SELR_SRC_MASK) {
 951                 case RCC_MPCKSELR_HSI:
 952                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 953                         break;
 954                 case RCC_MPCKSELR_HSE:
 955                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 956                         break;
 957                 case RCC_MPCKSELR_PLL:
 958                 case RCC_MPCKSELR_PLL_MPUDIV:
 959                         clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
 960                         if ((reg & RCC_SELR_SRC_MASK) ==
 961                             RCC_MPCKSELR_PLL_MPUDIV) {
 962                                 reg = readl(priv->base + RCC_MPCKDIVR);
 963                                 clock >>= stm32mp1_mpu_div[reg &
 964                                         RCC_MPUDIV_MASK];
 965                         }
 966                         break;
 967                 }
 968                 break;
 969         /* AXI sub system */
 970         case _ACLK:
 971         case _HCLK2:
 972         case _HCLK6:
 973         case _PCLK4:
 974         case _PCLK5:
 975                 reg = readl(priv->base + RCC_ASSCKSELR);
 976                 switch (reg & RCC_SELR_SRC_MASK) {
 977                 case RCC_ASSCKSELR_HSI:
 978                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 979                         break;
 980                 case RCC_ASSCKSELR_HSE:
 981                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 982                         break;
 983                 case RCC_ASSCKSELR_PLL:
 984                         clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
 985                         break;
 986                 }
 987
 988                 /* System clock divider */
 989                 reg = readl(priv->base + RCC_AXIDIVR);
 990                 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
 991
 992                 switch (p) {
 993                 case _PCLK4:
 994                         reg = readl(priv->base + RCC_APB4DIVR);
 995                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 996                         break;
 997                 case _PCLK5:
 998                         reg = readl(priv->base + RCC_APB5DIVR);
 999                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1000                         break;
1001                 default:
1002                         break;
1003                 }
1004                 break;
1005         /* MCU sub system */
1006         case _CK_MCU:
1007         case _PCLK1:
1008         case _PCLK2:
1009         case _PCLK3:
1010                 reg = readl(priv->base + RCC_MSSCKSELR);
1011                 switch (reg & RCC_SELR_SRC_MASK) {
1012                 case RCC_MSSCKSELR_HSI:
1013                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1014                         break;
1015                 case RCC_MSSCKSELR_HSE:
1016                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1017                         break;
1018                 case RCC_MSSCKSELR_CSI:
1019                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1020                         break;
1021                 case RCC_MSSCKSELR_PLL:
1022                         clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
1023                         break;
1024                 }
1025
1026                 /* MCU clock divider */
1027                 reg = readl(priv->base + RCC_MCUDIVR);
1028                 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1029
1030                 switch (p) {
1031                 case _PCLK1:
1032                         reg = readl(priv->base + RCC_APB1DIVR);
1033                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1034                         break;
1035                 case _PCLK2:
1036                         reg = readl(priv->base + RCC_APB2DIVR);
1037                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1038                         break;
1039                 case _PCLK3:
1040                         reg = readl(priv->base + RCC_APB3DIVR);
1041                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1042                         break;
1043                 case _CK_MCU:
1044                 default:
1045                         break;
1046                 }
1047                 break;
1048         case _CK_PER:
1049                 reg = readl(priv->base + RCC_CPERCKSELR);
1050                 switch (reg & RCC_SELR_SRC_MASK) {
1051                 case RCC_CPERCKSELR_HSI:
1052                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1053                         break;
1054                 case RCC_CPERCKSELR_HSE:
1055                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1056                         break;
1057                 case RCC_CPERCKSELR_CSI:
1058                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1059                         break;
1060                 }
1061                 break;
1062         case _HSI:
1063         case _HSI_KER:
1064                 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1065                 break;
1066         case _CSI:
1067         case _CSI_KER:
1068                 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1069                 break;
1070         case _HSE:
1071         case _HSE_KER:
1072         case _HSE_KER_DIV2:
1073                 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1074                 if (p == _HSE_KER_DIV2)
1075                         clock >>= 1;
1076                 break;
1077         case _LSI:
1078                 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1079                 break;
1080         case _LSE:
1081                 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1082                 break;
1083         /* PLL */
1084         case _PLL1_P:
1085         case _PLL1_Q:
1086         case _PLL1_R:
1087                 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1088                 break;
1089         case _PLL2_P:
1090         case _PLL2_Q:
1091         case _PLL2_R:
1092                 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1093                 break;
1094         case _PLL3_P:
1095         case _PLL3_Q:
1096         case _PLL3_R:
1097                 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1098                 break;
1099         case _PLL4_P:
1100         case _PLL4_Q:
1101         case _PLL4_R:
1102                 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1103                 break;
1104         /* other */
1105         case _USB_PHY_48:
1106                 clock = 48000000;
1107                 break;
1108         case _DSI_PHY:
1109         {
1110                 struct clk clk;
1111                 struct udevice *dev = NULL;
1112
1113                 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1114                                                &dev)) {
1115                         if (clk_request(dev, &clk)) {
1116                                 pr_err("ck_dsi_phy request");
1117                         } else {
1118                                 clk.id = 0;
1119                                 clock = clk_get_rate(&clk);
1120                         }
1121                 }
1122                 break;
1123         }
1124         default:
1125                 break;
1126         }
1127
1128         debug("%s(%d) clock = %lx : %ld kHz\n",
1129               __func__, p, clock, clock / 1000);
1130
1131         return clock;
1132 }
1133
1134 static int stm32mp1_clk_enable(struct clk *clk)
1135 {
1136         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1137         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1138         int i = stm32mp1_clk_get_id(priv, clk->id);
1139
1140         if (i < 0)
1141                 return i;
1142
1143         if (gate[i].set_clr)
1144                 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1145         else
1146                 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1147
1148         debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1149
1150         return 0;
1151 }
1152
1153 static int stm32mp1_clk_disable(struct clk *clk)
1154 {
1155         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1156         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1157         int i = stm32mp1_clk_get_id(priv, clk->id);
1158
1159         if (i < 0)
1160                 return i;
1161
1162         if (gate[i].set_clr)
1163                 writel(BIT(gate[i].bit),
1164                        priv->base + gate[i].offset
1165                        + RCC_MP_ENCLRR_OFFSET);
1166         else
1167                 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1168
1169         debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1170
1171         return 0;
1172 }
1173
1174 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1175 {
1176         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1177         int p = stm32mp1_clk_get_parent(priv, clk->id);
1178         ulong rate;
1179
1180         if (p < 0)
1181                 return 0;
1182
1183         rate = stm32mp1_clk_get(priv, p);
1184
1185 #ifdef DEBUG
1186         debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1187               __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1188 #endif
1189         return rate;
1190 }
1191
1192 #ifdef STM32MP1_CLOCK_TREE_INIT
1193 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1194                                 u32 mask_on)
1195 {
1196         u32 address = rcc + offset;
1197
1198         if (enable)
1199                 setbits_le32(address, mask_on);
1200         else
1201                 clrbits_le32(address, mask_on);
1202 }
1203
1204 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1205 {
1206         writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
1207 }
1208
1209 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1210                              u32 mask_rdy)
1211 {
1212         u32 mask_test = 0;
1213         u32 address = rcc + offset;
1214         u32 val;
1215         int ret;
1216
1217         if (enable)
1218                 mask_test = mask_rdy;
1219
1220         ret = readl_poll_timeout(address, val,
1221                                  (val & mask_rdy) == mask_test,
1222                                  TIMEOUT_1S);
1223
1224         if (ret)
1225                 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1226                        mask_rdy, address, enable, readl(address));
1227
1228         return ret;
1229 }
1230
1231 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
1232                                 u32 lsedrv)
1233 {
1234         u32 value;
1235
1236         if (digbyp)
1237                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
1238
1239         if (bypass || digbyp)
1240                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1241
1242         /*
1243          * warning: not recommended to switch directly from "high drive"
1244          * to "medium low drive", and vice-versa.
1245          */
1246         value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1247                 >> RCC_BDCR_LSEDRV_SHIFT;
1248
1249         while (value != lsedrv) {
1250                 if (value > lsedrv)
1251                         value--;
1252                 else
1253                         value++;
1254
1255                 clrsetbits_le32(rcc + RCC_BDCR,
1256                                 RCC_BDCR_LSEDRV_MASK,
1257                                 value << RCC_BDCR_LSEDRV_SHIFT);
1258         }
1259
1260         stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1261 }
1262
1263 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1264 {
1265         stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1266 }
1267
1268 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1269 {
1270         stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1271         stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1272 }
1273
1274 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
1275 {
1276         if (digbyp)
1277                 writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
1278         if (bypass || digbyp)
1279                 writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
1280
1281         stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1282         stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1283
1284         if (css)
1285                 writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
1286 }
1287
1288 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1289 {
1290         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
1291         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1292 }
1293
1294 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1295 {
1296         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1297         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1298 }
1299
1300 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1301 {
1302         u32 address = rcc + RCC_OCRDYR;
1303         u32 val;
1304         int ret;
1305
1306         clrsetbits_le32(rcc + RCC_HSICFGR,
1307                         RCC_HSICFGR_HSIDIV_MASK,
1308                         RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1309
1310         ret = readl_poll_timeout(address, val,
1311                                  val & RCC_OCRDYR_HSIDIVRDY,
1312                                  TIMEOUT_200MS);
1313         if (ret)
1314                 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1315                        address, readl(address));
1316
1317         return ret;
1318 }
1319
1320 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1321 {
1322         u8 hsidiv;
1323         u32 hsidivfreq = MAX_HSI_HZ;
1324
1325         for (hsidiv = 0; hsidiv < 4; hsidiv++,
1326              hsidivfreq = hsidivfreq / 2)
1327                 if (hsidivfreq == hsifreq)
1328                         break;
1329
1330         if (hsidiv == 4) {
1331                 pr_err("clk-hsi frequency invalid");
1332                 return -1;
1333         }
1334
1335         if (hsidiv > 0)
1336                 return stm32mp1_set_hsidiv(rcc, hsidiv);
1337
1338         return 0;
1339 }
1340
1341 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1342 {
1343         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1344
1345         clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
1346                         RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1347                         RCC_PLLNCR_DIVREN,
1348                         RCC_PLLNCR_PLLON);
1349 }
1350
1351 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1352 {
1353         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1354         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1355         u32 val;
1356         int ret;
1357
1358         ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1359                                  TIMEOUT_200MS);
1360
1361         if (ret) {
1362                 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1363                        pll_id, pllxcr, readl(pllxcr));
1364                 return ret;
1365         }
1366
1367         /* start the requested output */
1368         setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1369
1370         return 0;
1371 }
1372
1373 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1374 {
1375         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1376         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1377         u32 val;
1378
1379         /* stop all output */
1380         clrbits_le32(pllxcr,
1381                      RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1382
1383         /* stop PLL */
1384         clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1385
1386         /* wait PLL stopped */
1387         return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1388                                   TIMEOUT_200MS);
1389 }
1390
1391 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1392                               int pll_id, u32 *pllcfg)
1393 {
1394         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1395         fdt_addr_t rcc = priv->base;
1396         u32 value;
1397
1398         value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1399                 & RCC_PLLNCFGR2_DIVP_MASK;
1400         value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1401                  & RCC_PLLNCFGR2_DIVQ_MASK;
1402         value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1403                  & RCC_PLLNCFGR2_DIVR_MASK;
1404         writel(value, rcc + pll[pll_id].pllxcfgr2);
1405 }
1406
1407 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1408                       u32 *pllcfg, u32 fracv)
1409 {
1410         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1411         fdt_addr_t rcc = priv->base;
1412         enum stm32mp1_plltype type = pll[pll_id].plltype;
1413         int src;
1414         ulong refclk;
1415         u8 ifrge = 0;
1416         u32 value;
1417
1418         src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1419
1420         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1421                  (pllcfg[PLLCFG_M] + 1);
1422
1423         if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1424             refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1425                 debug("invalid refclk = %x\n", (u32)refclk);
1426                 return -EINVAL;
1427         }
1428         if (type == PLL_800 && refclk >= 8000000)
1429                 ifrge = 1;
1430
1431         value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1432                  & RCC_PLLNCFGR1_DIVN_MASK;
1433         value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1434                  & RCC_PLLNCFGR1_DIVM_MASK;
1435         value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1436                  & RCC_PLLNCFGR1_IFRGE_MASK;
1437         writel(value, rcc + pll[pll_id].pllxcfgr1);
1438
1439         /* fractional configuration: load sigma-delta modulator (SDM) */
1440
1441         /* Write into FRACV the new fractional value , and FRACLE to 0 */
1442         writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1443                rcc + pll[pll_id].pllxfracr);
1444
1445         /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1446         setbits_le32(rcc + pll[pll_id].pllxfracr,
1447                      RCC_PLLNFRACR_FRACLE);
1448
1449         pll_config_output(priv, pll_id, pllcfg);
1450
1451         return 0;
1452 }
1453
1454 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1455 {
1456         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1457         u32 pllxcsg;
1458
1459         pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1460                     RCC_PLLNCSGR_MOD_PER_MASK) |
1461                   ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1462                     RCC_PLLNCSGR_INC_STEP_MASK) |
1463                   ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1464                     RCC_PLLNCSGR_SSCG_MODE_MASK);
1465
1466         writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1467
1468         setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
1469 }
1470
1471 static  __maybe_unused int pll_set_rate(struct udevice *dev,
1472                                         int pll_id,
1473                                         int div_id,
1474                                         unsigned long clk_rate)
1475 {
1476         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1477         unsigned int pllcfg[PLLCFG_NB];
1478         ofnode plloff;
1479         char name[12];
1480         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1481         enum stm32mp1_plltype type = pll[pll_id].plltype;
1482         int divm, divn, divy;
1483         int ret;
1484         ulong fck_ref;
1485         u32 fracv;
1486         u64 value;
1487
1488         if (div_id > _DIV_NB)
1489                 return -EINVAL;
1490
1491         sprintf(name, "st,pll@%d", pll_id);
1492         plloff = dev_read_subnode(dev, name);
1493         if (!ofnode_valid(plloff))
1494                 return -FDT_ERR_NOTFOUND;
1495
1496         ret = ofnode_read_u32_array(plloff, "cfg",
1497                                     pllcfg, PLLCFG_NB);
1498         if (ret < 0)
1499                 return -FDT_ERR_NOTFOUND;
1500
1501         fck_ref = pll_get_fref_ck(priv, pll_id);
1502
1503         divm = pllcfg[PLLCFG_M];
1504         /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
1505         divy = pllcfg[PLLCFG_P + div_id];
1506
1507         /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
1508          * So same final result than PLL2 et 4
1509          * with FRACV
1510          * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
1511          *             / (DIVy + 1) * (DIVM + 1)
1512          * value = (DIVN + 1) * 2^13 + FRACV / 2^13
1513          *       = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
1514          */
1515         value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
1516         value = lldiv(value, fck_ref);
1517
1518         divn = (value >> 13) - 1;
1519         if (divn < DIVN_MIN ||
1520             divn > stm32mp1_pll[type].divn_max) {
1521                 pr_err("divn invalid = %d", divn);
1522                 return -EINVAL;
1523         }
1524         fracv = value - ((divn + 1) << 13);
1525         pllcfg[PLLCFG_N] = divn;
1526
1527         /* reconfigure PLL */
1528         pll_stop(priv, pll_id);
1529         pll_config(priv, pll_id, pllcfg, fracv);
1530         pll_start(priv, pll_id);
1531         pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
1532
1533         return 0;
1534 }
1535
1536 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1537 {
1538         u32 address = priv->base + (clksrc >> 4);
1539         u32 val;
1540         int ret;
1541
1542         clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1543         ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1544                                  TIMEOUT_200MS);
1545         if (ret)
1546                 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1547                        clksrc, address, readl(address));
1548
1549         return ret;
1550 }
1551
1552 static void stgen_config(struct stm32mp1_clk_priv *priv)
1553 {
1554         int p;
1555         u32 stgenc, cntfid0;
1556         ulong rate;
1557
1558         stgenc = STM32_STGEN_BASE;
1559         cntfid0 = readl(stgenc + STGENC_CNTFID0);
1560         p = stm32mp1_clk_get_parent(priv, STGEN_K);
1561         rate = stm32mp1_clk_get(priv, p);
1562
1563         if (cntfid0 != rate) {
1564                 u64 counter;
1565
1566                 pr_debug("System Generic Counter (STGEN) update\n");
1567                 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1568                 counter = (u64)readl(stgenc + STGENC_CNTCVL);
1569                 counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
1570                 counter = lldiv(counter * (u64)rate, cntfid0);
1571                 writel((u32)counter, stgenc + STGENC_CNTCVL);
1572                 writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
1573                 writel(rate, stgenc + STGENC_CNTFID0);
1574                 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1575
1576                 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1577
1578                 /* need to update gd->arch.timer_rate_hz with new frequency */
1579                 timer_init();
1580         }
1581 }
1582
1583 static int set_clkdiv(unsigned int clkdiv, u32 address)
1584 {
1585         u32 val;
1586         int ret;
1587
1588         clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1589         ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1590                                  TIMEOUT_200MS);
1591         if (ret)
1592                 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1593                        clkdiv, address, readl(address));
1594
1595         return ret;
1596 }
1597
1598 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1599                              u32 clksrc, u32 clkdiv)
1600 {
1601         u32 address = priv->base + (clksrc >> 4);
1602
1603         /*
1604          * binding clksrc : bit15-4 offset
1605          *                  bit3:   disable
1606          *                  bit2-0: MCOSEL[2:0]
1607          */
1608         if (clksrc & 0x8) {
1609                 clrbits_le32(address, RCC_MCOCFG_MCOON);
1610         } else {
1611                 clrsetbits_le32(address,
1612                                 RCC_MCOCFG_MCOSRC_MASK,
1613                                 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1614                 clrsetbits_le32(address,
1615                                 RCC_MCOCFG_MCODIV_MASK,
1616                                 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1617                 setbits_le32(address, RCC_MCOCFG_MCOON);
1618         }
1619 }
1620
1621 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1622                        unsigned int clksrc,
1623                        int lse_css)
1624 {
1625         u32 address = priv->base + RCC_BDCR;
1626
1627         if (readl(address) & RCC_BDCR_RTCCKEN)
1628                 goto skip_rtc;
1629
1630         if (clksrc == CLK_RTC_DISABLED)
1631                 goto skip_rtc;
1632
1633         clrsetbits_le32(address,
1634                         RCC_BDCR_RTCSRC_MASK,
1635                         clksrc << RCC_BDCR_RTCSRC_SHIFT);
1636
1637         setbits_le32(address, RCC_BDCR_RTCCKEN);
1638
1639 skip_rtc:
1640         if (lse_css)
1641                 setbits_le32(address, RCC_BDCR_LSECSSON);
1642 }
1643
1644 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1645 {
1646         u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1647         u32 value = pkcs & 0xF;
1648         u32 mask = 0xF;
1649
1650         if (pkcs & BIT(31)) {
1651                 mask <<= 4;
1652                 value <<= 4;
1653         }
1654         clrsetbits_le32(address, mask, value);
1655 }
1656
1657 static int stm32mp1_clktree(struct udevice *dev)
1658 {
1659         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1660         fdt_addr_t rcc = priv->base;
1661         unsigned int clksrc[CLKSRC_NB];
1662         unsigned int clkdiv[CLKDIV_NB];
1663         unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1664         ofnode plloff[_PLL_NB];
1665         int ret, len;
1666         uint i;
1667         int lse_css = 0;
1668         const u32 *pkcs_cell;
1669
1670         /* check mandatory field */
1671         ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1672         if (ret < 0) {
1673                 debug("field st,clksrc invalid: error %d\n", ret);
1674                 return -FDT_ERR_NOTFOUND;
1675         }
1676
1677         ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1678         if (ret < 0) {
1679                 debug("field st,clkdiv invalid: error %d\n", ret);
1680                 return -FDT_ERR_NOTFOUND;
1681         }
1682
1683         /* check mandatory field in each pll */
1684         for (i = 0; i < _PLL_NB; i++) {
1685                 char name[12];
1686
1687                 sprintf(name, "st,pll@%d", i);
1688                 plloff[i] = dev_read_subnode(dev, name);
1689                 if (!ofnode_valid(plloff[i]))
1690                         continue;
1691                 ret = ofnode_read_u32_array(plloff[i], "cfg",
1692                                             pllcfg[i], PLLCFG_NB);
1693                 if (ret < 0) {
1694                         debug("field cfg invalid: error %d\n", ret);
1695                         return -FDT_ERR_NOTFOUND;
1696                 }
1697         }
1698
1699         debug("configuration MCO\n");
1700         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1701         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1702
1703         debug("switch ON osillator\n");
1704         /*
1705          * switch ON oscillator found in device-tree,
1706          * HSI already ON after bootrom
1707          */
1708         if (priv->osc[_LSI])
1709                 stm32mp1_lsi_set(rcc, 1);
1710
1711         if (priv->osc[_LSE]) {
1712                 int bypass, digbyp;
1713                 u32 lsedrv;
1714                 struct udevice *dev = priv->osc_dev[_LSE];
1715
1716                 bypass = dev_read_bool(dev, "st,bypass");
1717                 digbyp = dev_read_bool(dev, "st,digbypass");
1718                 lse_css = dev_read_bool(dev, "st,css");
1719                 lsedrv = dev_read_u32_default(dev, "st,drive",
1720                                               LSEDRV_MEDIUM_HIGH);
1721
1722                 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
1723         }
1724
1725         if (priv->osc[_HSE]) {
1726                 int bypass, digbyp, css;
1727                 struct udevice *dev = priv->osc_dev[_HSE];
1728
1729                 bypass = dev_read_bool(dev, "st,bypass");
1730                 digbyp = dev_read_bool(dev, "st,digbypass");
1731                 css = dev_read_bool(dev, "st,css");
1732
1733                 stm32mp1_hse_enable(rcc, bypass, digbyp, css);
1734         }
1735         /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1736          * => switch on CSI even if node is not present in device tree
1737          */
1738         stm32mp1_csi_set(rcc, 1);
1739
1740         /* come back to HSI */
1741         debug("come back to HSI\n");
1742         set_clksrc(priv, CLK_MPU_HSI);
1743         set_clksrc(priv, CLK_AXI_HSI);
1744         set_clksrc(priv, CLK_MCU_HSI);
1745
1746         debug("pll stop\n");
1747         for (i = 0; i < _PLL_NB; i++)
1748                 pll_stop(priv, i);
1749
1750         /* configure HSIDIV */
1751         debug("configure HSIDIV\n");
1752         if (priv->osc[_HSI]) {
1753                 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
1754                 stgen_config(priv);
1755         }
1756
1757         /* select DIV */
1758         debug("select DIV\n");
1759         /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1760         writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1761         set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1762         set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1763         set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1764         set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1765         set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1766         set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1767         set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1768
1769         /* no ready bit for RTC */
1770         writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1771
1772         /* configure PLLs source */
1773         debug("configure PLLs source\n");
1774         set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1775         set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1776         set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1777
1778         /* configure and start PLLs */
1779         debug("configure PLLs\n");
1780         for (i = 0; i < _PLL_NB; i++) {
1781                 u32 fracv;
1782                 u32 csg[PLLCSG_NB];
1783
1784                 debug("configure PLL %d @ %d\n", i,
1785                       ofnode_to_offset(plloff[i]));
1786                 if (!ofnode_valid(plloff[i]))
1787                         continue;
1788
1789                 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1790                 pll_config(priv, i, pllcfg[i], fracv);
1791                 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1792                 if (!ret) {
1793                         pll_csg(priv, i, csg);
1794                 } else if (ret != -FDT_ERR_NOTFOUND) {
1795                         debug("invalid csg node for pll@%d res=%d\n", i, ret);
1796                         return ret;
1797                 }
1798                 pll_start(priv, i);
1799         }
1800
1801         /* wait and start PLLs ouptut when ready */
1802         for (i = 0; i < _PLL_NB; i++) {
1803                 if (!ofnode_valid(plloff[i]))
1804                         continue;
1805                 debug("output PLL %d\n", i);
1806                 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1807         }
1808
1809         /* wait LSE ready before to use it */
1810         if (priv->osc[_LSE])
1811                 stm32mp1_lse_wait(rcc);
1812
1813         /* configure with expected clock source */
1814         debug("CLKSRC\n");
1815         set_clksrc(priv, clksrc[CLKSRC_MPU]);
1816         set_clksrc(priv, clksrc[CLKSRC_AXI]);
1817         set_clksrc(priv, clksrc[CLKSRC_MCU]);
1818         set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1819
1820         /* configure PKCK */
1821         debug("PKCK\n");
1822         pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1823         if (pkcs_cell) {
1824                 bool ckper_disabled = false;
1825
1826                 for (i = 0; i < len / sizeof(u32); i++) {
1827                         u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1828
1829                         if (pkcs == CLK_CKPER_DISABLED) {
1830                                 ckper_disabled = true;
1831                                 continue;
1832                         }
1833                         pkcs_config(priv, pkcs);
1834                 }
1835                 /* CKPER is source for some peripheral clock
1836                  * (FMC-NAND / QPSI-NOR) and switching source is allowed
1837                  * only if previous clock is still ON
1838                  * => deactivated CKPER only after switching clock
1839                  */
1840                 if (ckper_disabled)
1841                         pkcs_config(priv, CLK_CKPER_DISABLED);
1842         }
1843
1844         /* STGEN clock source can change with CLK_STGEN_XXX */
1845         stgen_config(priv);
1846
1847         debug("oscillator off\n");
1848         /* switch OFF HSI if not found in device-tree */
1849         if (!priv->osc[_HSI])
1850                 stm32mp1_hsi_set(rcc, 0);
1851
1852         /* Software Self-Refresh mode (SSR) during DDR initilialization */
1853         clrsetbits_le32(priv->base + RCC_DDRITFCR,
1854                         RCC_DDRITFCR_DDRCKMOD_MASK,
1855                         RCC_DDRITFCR_DDRCKMOD_SSR <<
1856                         RCC_DDRITFCR_DDRCKMOD_SHIFT);
1857
1858         return 0;
1859 }
1860 #endif /* STM32MP1_CLOCK_TREE_INIT */
1861
1862 static int pll_set_output_rate(struct udevice *dev,
1863                                int pll_id,
1864                                int div_id,
1865                                unsigned long clk_rate)
1866 {
1867         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1868         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1869         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1870         int div;
1871         ulong fvco;
1872
1873         if (div_id > _DIV_NB)
1874                 return -EINVAL;
1875
1876         fvco = pll_get_fvco(priv, pll_id);
1877
1878         if (fvco <= clk_rate)
1879                 div = 1;
1880         else
1881                 div = DIV_ROUND_UP(fvco, clk_rate);
1882
1883         if (div > 128)
1884                 div = 128;
1885
1886         /* stop the requested output */
1887         clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1888         /* change divider */
1889         clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
1890                         RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
1891                         (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
1892         /* start the requested output */
1893         setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1894
1895         return 0;
1896 }
1897
1898 static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
1899 {
1900         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1901         int p;
1902
1903         switch (clk->id) {
1904 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
1905         defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
1906         case DDRPHYC:
1907                 break;
1908 #endif
1909         case LTDC_PX:
1910         case DSI_PX:
1911                 break;
1912         default:
1913                 pr_err("not supported");
1914                 return -EINVAL;
1915         }
1916
1917         p = stm32mp1_clk_get_parent(priv, clk->id);
1918 #ifdef DEBUG
1919         debug("%s: parent = %d:%s\n", __func__, p, stm32mp1_clk_parent_name[p]);
1920 #endif
1921         if (p < 0)
1922                 return -EINVAL;
1923
1924         switch (p) {
1925 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
1926         defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
1927         case _PLL2_R: /* DDRPHYC */
1928         {
1929                 /* only for change DDR clock in interactive mode */
1930                 ulong result;
1931
1932                 set_clksrc(priv, CLK_AXI_HSI);
1933                 result = pll_set_rate(clk->dev,  _PLL2, _DIV_R, clk_rate);
1934                 set_clksrc(priv, CLK_AXI_PLL2P);
1935                 return result;
1936         }
1937 #endif
1938
1939         case _PLL4_Q:
1940                 /* for LTDC_PX and DSI_PX case */
1941                 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
1942         }
1943
1944         return -EINVAL;
1945 }
1946
1947 static void stm32mp1_osc_clk_init(const char *name,
1948                                   struct stm32mp1_clk_priv *priv,
1949                                   int index)
1950 {
1951         struct clk clk;
1952         struct udevice *dev = NULL;
1953
1954         priv->osc[index] = 0;
1955         clk.id = 0;
1956         if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1957                 if (clk_request(dev, &clk))
1958                         pr_err("%s request", name);
1959                 else
1960                         priv->osc[index] = clk_get_rate(&clk);
1961         }
1962         priv->osc_dev[index] = dev;
1963 }
1964
1965 static void stm32mp1_osc_init(struct udevice *dev)
1966 {
1967         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1968         int i;
1969         const char *name[NB_OSC] = {
1970                 [_LSI] = "clk-lsi",
1971                 [_LSE] = "clk-lse",
1972                 [_HSI] = "clk-hsi",
1973                 [_HSE] = "clk-hse",
1974                 [_CSI] = "clk-csi",
1975                 [_I2S_CKIN] = "i2s_ckin",
1976         };
1977
1978         for (i = 0; i < NB_OSC; i++) {
1979                 stm32mp1_osc_clk_init(name[i], priv, i);
1980                 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1981         }
1982 }
1983
1984 static void  __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
1985 {
1986         char buf[32];
1987         int i, s, p;
1988
1989         printf("Clocks:\n");
1990         for (i = 0; i < _PARENT_NB; i++) {
1991                 printf("- %s : %s MHz\n",
1992                        stm32mp1_clk_parent_name[i],
1993                        strmhz(buf, stm32mp1_clk_get(priv, i)));
1994         }
1995         printf("Source Clocks:\n");
1996         for (i = 0; i < _PARENT_SEL_NB; i++) {
1997                 p = (readl(priv->base + priv->data->sel[i].offset) >>
1998                      priv->data->sel[i].src) & priv->data->sel[i].msk;
1999                 if (p < priv->data->sel[i].nb_parent) {
2000                         s = priv->data->sel[i].parent[p];
2001                         printf("- %s(%d) => parent %s(%d)\n",
2002                                stm32mp1_clk_parent_sel_name[i], i,
2003                                stm32mp1_clk_parent_name[s], s);
2004                 } else {
2005                         printf("- %s(%d) => parent index %d is invalid\n",
2006                                stm32mp1_clk_parent_sel_name[i], i, p);
2007                 }
2008         }
2009 }
2010
2011 #ifdef CONFIG_CMD_CLK
2012 int soc_clk_dump(void)
2013 {
2014         struct udevice *dev;
2015         struct stm32mp1_clk_priv *priv;
2016         int ret;
2017
2018         ret = uclass_get_device_by_driver(UCLASS_CLK,
2019                                           DM_GET_DRIVER(stm32mp1_clock),
2020                                           &dev);
2021         if (ret)
2022                 return ret;
2023
2024         priv = dev_get_priv(dev);
2025
2026         stm32mp1_clk_dump(priv);
2027
2028         return 0;
2029 }
2030 #endif
2031
2032 static int stm32mp1_clk_probe(struct udevice *dev)
2033 {
2034         int result = 0;
2035         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2036
2037         priv->base = dev_read_addr(dev->parent);
2038         if (priv->base == FDT_ADDR_T_NONE)
2039                 return -EINVAL;
2040
2041         priv->data = (void *)&stm32mp1_data;
2042
2043         if (!priv->data->gate || !priv->data->sel ||
2044             !priv->data->pll)
2045                 return -EINVAL;
2046
2047         stm32mp1_osc_init(dev);
2048
2049 #ifdef STM32MP1_CLOCK_TREE_INIT
2050         /* clock tree init is done only one time, before relocation */
2051         if (!(gd->flags & GD_FLG_RELOC))
2052                 result = stm32mp1_clktree(dev);
2053 #endif
2054
2055 #ifndef CONFIG_SPL_BUILD
2056 #if defined(DEBUG)
2057         /* display debug information for probe after relocation */
2058         if (gd->flags & GD_FLG_RELOC)
2059                 stm32mp1_clk_dump(priv);
2060 #endif
2061
2062         gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU);
2063         gd->bus_clk = stm32mp1_clk_get(priv, _ACLK);
2064         /* DDRPHYC father */
2065         gd->mem_clk = stm32mp1_clk_get(priv, _PLL2_R);
2066 #if defined(CONFIG_DISPLAY_CPUINFO)
2067         if (gd->flags & GD_FLG_RELOC) {
2068                 char buf[32];
2069
2070                 printf("Clocks:\n");
2071                 printf("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
2072                 printf("- MCU : %s MHz\n",
2073                        strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
2074                 printf("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
2075                 printf("- PER : %s MHz\n",
2076                        strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
2077                 printf("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
2078         }
2079 #endif /* CONFIG_DISPLAY_CPUINFO */
2080 #endif
2081
2082         return result;
2083 }
2084
2085 static const struct clk_ops stm32mp1_clk_ops = {
2086         .enable = stm32mp1_clk_enable,
2087         .disable = stm32mp1_clk_disable,
2088         .get_rate = stm32mp1_clk_get_rate,
2089         .set_rate = stm32mp1_clk_set_rate,
2090 };
2091
2092 U_BOOT_DRIVER(stm32mp1_clock) = {
2093         .name = "stm32mp1_clk",
2094         .id = UCLASS_CLK,
2095         .ops = &stm32mp1_clk_ops,
2096         .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
2097         .probe = stm32mp1_clk_probe,
2098 };