drivers/clk/clk_stm32mp1.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk-uclass.h>
   8 #include <div64.h>
   9 #include <dm.h>
  10 #include <regmap.h>
  11 #include <spl.h>
  12 #include <syscon.h>
  13 #include <linux/io.h>
  14 #include <linux/iopoll.h>
  15 #include <dt-bindings/clock/stm32mp1-clks.h>
  16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  17
  18 #ifndef CONFIG_STM32MP1_TRUSTED
  19 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  20 /* activate clock tree initialization in the driver */
  21 #define STM32MP1_CLOCK_TREE_INIT
  22 #endif
  23 #endif
  24
  25 #define MAX_HSI_HZ              64000000
  26
  27 /* TIMEOUT */
  28 #define TIMEOUT_200MS           200000
  29 #define TIMEOUT_1S              1000000
  30
  31 /* STGEN registers */
  32 #define STGENC_CNTCR            0x00
  33 #define STGENC_CNTSR            0x04
  34 #define STGENC_CNTCVL           0x08
  35 #define STGENC_CNTCVU           0x0C
  36 #define STGENC_CNTFID0          0x20
  37
  38 #define STGENC_CNTCR_EN         BIT(0)
  39
  40 /* RCC registers */
  41 #define RCC_OCENSETR            0x0C
  42 #define RCC_OCENCLRR            0x10
  43 #define RCC_HSICFGR             0x18
  44 #define RCC_MPCKSELR            0x20
  45 #define RCC_ASSCKSELR           0x24
  46 #define RCC_RCK12SELR           0x28
  47 #define RCC_MPCKDIVR            0x2C
  48 #define RCC_AXIDIVR             0x30
  49 #define RCC_APB4DIVR            0x3C
  50 #define RCC_APB5DIVR            0x40
  51 #define RCC_RTCDIVR             0x44
  52 #define RCC_MSSCKSELR           0x48
  53 #define RCC_PLL1CR              0x80
  54 #define RCC_PLL1CFGR1           0x84
  55 #define RCC_PLL1CFGR2           0x88
  56 #define RCC_PLL1FRACR           0x8C
  57 #define RCC_PLL1CSGR            0x90
  58 #define RCC_PLL2CR              0x94
  59 #define RCC_PLL2CFGR1           0x98
  60 #define RCC_PLL2CFGR2           0x9C
  61 #define RCC_PLL2FRACR           0xA0
  62 #define RCC_PLL2CSGR            0xA4
  63 #define RCC_I2C46CKSELR         0xC0
  64 #define RCC_CPERCKSELR          0xD0
  65 #define RCC_STGENCKSELR         0xD4
  66 #define RCC_DDRITFCR            0xD8
  67 #define RCC_BDCR                0x140
  68 #define RCC_RDLSICR             0x144
  69 #define RCC_MP_APB4ENSETR       0x200
  70 #define RCC_MP_APB5ENSETR       0x208
  71 #define RCC_MP_AHB5ENSETR       0x210
  72 #define RCC_MP_AHB6ENSETR       0x218
  73 #define RCC_OCRDYR              0x808
  74 #define RCC_DBGCFGR             0x80C
  75 #define RCC_RCK3SELR            0x820
  76 #define RCC_RCK4SELR            0x824
  77 #define RCC_MCUDIVR             0x830
  78 #define RCC_APB1DIVR            0x834
  79 #define RCC_APB2DIVR            0x838
  80 #define RCC_APB3DIVR            0x83C
  81 #define RCC_PLL3CR              0x880
  82 #define RCC_PLL3CFGR1           0x884
  83 #define RCC_PLL3CFGR2           0x888
  84 #define RCC_PLL3FRACR           0x88C
  85 #define RCC_PLL3CSGR            0x890
  86 #define RCC_PLL4CR              0x894
  87 #define RCC_PLL4CFGR1           0x898
  88 #define RCC_PLL4CFGR2           0x89C
  89 #define RCC_PLL4FRACR           0x8A0
  90 #define RCC_PLL4CSGR            0x8A4
  91 #define RCC_I2C12CKSELR         0x8C0
  92 #define RCC_I2C35CKSELR         0x8C4
  93 #define RCC_UART6CKSELR         0x8E4
  94 #define RCC_UART24CKSELR        0x8E8
  95 #define RCC_UART35CKSELR        0x8EC
  96 #define RCC_UART78CKSELR        0x8F0
  97 #define RCC_SDMMC12CKSELR       0x8F4
  98 #define RCC_SDMMC3CKSELR        0x8F8
  99 #define RCC_ETHCKSELR           0x8FC
 100 #define RCC_QSPICKSELR          0x900
 101 #define RCC_FMCCKSELR           0x904
 102 #define RCC_USBCKSELR           0x91C
 103 #define RCC_DSICKSELR           0x924
 104 #define RCC_ADCCKSELR           0x928
 105 #define RCC_MP_APB1ENSETR       0xA00
 106 #define RCC_MP_APB2ENSETR       0XA08
 107 #define RCC_MP_APB3ENSETR       0xA10
 108 #define RCC_MP_AHB2ENSETR       0xA18
 109 #define RCC_MP_AHB3ENSETR       0xA20
 110 #define RCC_MP_AHB4ENSETR       0xA28
 111
 112 /* used for most of SELR register */
 113 #define RCC_SELR_SRC_MASK       GENMASK(2, 0)
 114 #define RCC_SELR_SRCRDY         BIT(31)
 115
 116 /* Values of RCC_MPCKSELR register */
 117 #define RCC_MPCKSELR_HSI        0
 118 #define RCC_MPCKSELR_HSE        1
 119 #define RCC_MPCKSELR_PLL        2
 120 #define RCC_MPCKSELR_PLL_MPUDIV 3
 121
 122 /* Values of RCC_ASSCKSELR register */
 123 #define RCC_ASSCKSELR_HSI       0
 124 #define RCC_ASSCKSELR_HSE       1
 125 #define RCC_ASSCKSELR_PLL       2
 126
 127 /* Values of RCC_MSSCKSELR register */
 128 #define RCC_MSSCKSELR_HSI       0
 129 #define RCC_MSSCKSELR_HSE       1
 130 #define RCC_MSSCKSELR_CSI       2
 131 #define RCC_MSSCKSELR_PLL       3
 132
 133 /* Values of RCC_CPERCKSELR register */
 134 #define RCC_CPERCKSELR_HSI      0
 135 #define RCC_CPERCKSELR_CSI      1
 136 #define RCC_CPERCKSELR_HSE      2
 137
 138 /* used for most of DIVR register : max div for RTC */
 139 #define RCC_DIVR_DIV_MASK       GENMASK(5, 0)
 140 #define RCC_DIVR_DIVRDY         BIT(31)
 141
 142 /* Masks for specific DIVR registers */
 143 #define RCC_APBXDIV_MASK        GENMASK(2, 0)
 144 #define RCC_MPUDIV_MASK         GENMASK(2, 0)
 145 #define RCC_AXIDIV_MASK         GENMASK(2, 0)
 146 #define RCC_MCUDIV_MASK         GENMASK(3, 0)
 147
 148 /*  offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
 149 #define RCC_MP_ENCLRR_OFFSET    4
 150
 151 /* Fields of RCC_BDCR register */
 152 #define RCC_BDCR_LSEON          BIT(0)
 153 #define RCC_BDCR_LSEBYP         BIT(1)
 154 #define RCC_BDCR_LSERDY         BIT(2)
 155 #define RCC_BDCR_DIGBYP         BIT(3)
 156 #define RCC_BDCR_LSEDRV_MASK    GENMASK(5, 4)
 157 #define RCC_BDCR_LSEDRV_SHIFT   4
 158 #define RCC_BDCR_LSECSSON       BIT(8)
 159 #define RCC_BDCR_RTCCKEN        BIT(20)
 160 #define RCC_BDCR_RTCSRC_MASK    GENMASK(17, 16)
 161 #define RCC_BDCR_RTCSRC_SHIFT   16
 162
 163 /* Fields of RCC_RDLSICR register */
 164 #define RCC_RDLSICR_LSION       BIT(0)
 165 #define RCC_RDLSICR_LSIRDY      BIT(1)
 166
 167 /* used for ALL PLLNCR registers */
 168 #define RCC_PLLNCR_PLLON        BIT(0)
 169 #define RCC_PLLNCR_PLLRDY       BIT(1)
 170 #define RCC_PLLNCR_SSCG_CTRL    BIT(2)
 171 #define RCC_PLLNCR_DIVPEN       BIT(4)
 172 #define RCC_PLLNCR_DIVQEN       BIT(5)
 173 #define RCC_PLLNCR_DIVREN       BIT(6)
 174 #define RCC_PLLNCR_DIVEN_SHIFT  4
 175
 176 /* used for ALL PLLNCFGR1 registers */
 177 #define RCC_PLLNCFGR1_DIVM_SHIFT        16
 178 #define RCC_PLLNCFGR1_DIVM_MASK         GENMASK(21, 16)
 179 #define RCC_PLLNCFGR1_DIVN_SHIFT        0
 180 #define RCC_PLLNCFGR1_DIVN_MASK         GENMASK(8, 0)
 181 /* only for PLL3 and PLL4 */
 182 #define RCC_PLLNCFGR1_IFRGE_SHIFT       24
 183 #define RCC_PLLNCFGR1_IFRGE_MASK        GENMASK(25, 24)
 184
 185 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
 186 #define RCC_PLLNCFGR2_SHIFT(div_id)     ((div_id) * 8)
 187 #define RCC_PLLNCFGR2_DIVX_MASK         GENMASK(6, 0)
 188 #define RCC_PLLNCFGR2_DIVP_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_P)
 189 #define RCC_PLLNCFGR2_DIVP_MASK         GENMASK(6, 0)
 190 #define RCC_PLLNCFGR2_DIVQ_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_Q)
 191 #define RCC_PLLNCFGR2_DIVQ_MASK         GENMASK(14, 8)
 192 #define RCC_PLLNCFGR2_DIVR_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_R)
 193 #define RCC_PLLNCFGR2_DIVR_MASK         GENMASK(22, 16)
 194
 195 /* used for ALL PLLNFRACR registers */
 196 #define RCC_PLLNFRACR_FRACV_SHIFT       3
 197 #define RCC_PLLNFRACR_FRACV_MASK        GENMASK(15, 3)
 198 #define RCC_PLLNFRACR_FRACLE            BIT(16)
 199
 200 /* used for ALL PLLNCSGR registers */
 201 #define RCC_PLLNCSGR_INC_STEP_SHIFT     16
 202 #define RCC_PLLNCSGR_INC_STEP_MASK      GENMASK(30, 16)
 203 #define RCC_PLLNCSGR_MOD_PER_SHIFT      0
 204 #define RCC_PLLNCSGR_MOD_PER_MASK       GENMASK(12, 0)
 205 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT    15
 206 #define RCC_PLLNCSGR_SSCG_MODE_MASK     BIT(15)
 207
 208 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
 209 #define RCC_OCENR_HSION                 BIT(0)
 210 #define RCC_OCENR_CSION                 BIT(4)
 211 #define RCC_OCENR_DIGBYP                BIT(7)
 212 #define RCC_OCENR_HSEON                 BIT(8)
 213 #define RCC_OCENR_HSEBYP                BIT(10)
 214 #define RCC_OCENR_HSECSSON              BIT(11)
 215
 216 /* Fields of RCC_OCRDYR register */
 217 #define RCC_OCRDYR_HSIRDY               BIT(0)
 218 #define RCC_OCRDYR_HSIDIVRDY            BIT(2)
 219 #define RCC_OCRDYR_CSIRDY               BIT(4)
 220 #define RCC_OCRDYR_HSERDY               BIT(8)
 221
 222 /* Fields of DDRITFCR register */
 223 #define RCC_DDRITFCR_DDRCKMOD_MASK      GENMASK(22, 20)
 224 #define RCC_DDRITFCR_DDRCKMOD_SHIFT     20
 225 #define RCC_DDRITFCR_DDRCKMOD_SSR       0
 226
 227 /* Fields of RCC_HSICFGR register */
 228 #define RCC_HSICFGR_HSIDIV_MASK         GENMASK(1, 0)
 229
 230 /* used for MCO related operations */
 231 #define RCC_MCOCFG_MCOON                BIT(12)
 232 #define RCC_MCOCFG_MCODIV_MASK          GENMASK(7, 4)
 233 #define RCC_MCOCFG_MCODIV_SHIFT         4
 234 #define RCC_MCOCFG_MCOSRC_MASK          GENMASK(2, 0)
 235
 236 enum stm32mp1_parent_id {
 237 /*
 238  * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
 239  * they are used as index in osc[] as entry point
 240  */
 241         _HSI,
 242         _HSE,
 243         _CSI,
 244         _LSI,
 245         _LSE,
 246         _I2S_CKIN,
 247         NB_OSC,
 248
 249 /* other parent source */
 250         _HSI_KER = NB_OSC,
 251         _HSE_KER,
 252         _HSE_KER_DIV2,
 253         _CSI_KER,
 254         _PLL1_P,
 255         _PLL1_Q,
 256         _PLL1_R,
 257         _PLL2_P,
 258         _PLL2_Q,
 259         _PLL2_R,
 260         _PLL3_P,
 261         _PLL3_Q,
 262         _PLL3_R,
 263         _PLL4_P,
 264         _PLL4_Q,
 265         _PLL4_R,
 266         _ACLK,
 267         _PCLK1,
 268         _PCLK2,
 269         _PCLK3,
 270         _PCLK4,
 271         _PCLK5,
 272         _HCLK6,
 273         _HCLK2,
 274         _CK_PER,
 275         _CK_MPU,
 276         _CK_MCU,
 277         _DSI_PHY,
 278         _USB_PHY_48,
 279         _PARENT_NB,
 280         _UNKNOWN_ID = 0xff,
 281 };
 282
 283 enum stm32mp1_parent_sel {
 284         _I2C12_SEL,
 285         _I2C35_SEL,
 286         _I2C46_SEL,
 287         _UART6_SEL,
 288         _UART24_SEL,
 289         _UART35_SEL,
 290         _UART78_SEL,
 291         _SDMMC12_SEL,
 292         _SDMMC3_SEL,
 293         _ETH_SEL,
 294         _QSPI_SEL,
 295         _FMC_SEL,
 296         _USBPHY_SEL,
 297         _USBO_SEL,
 298         _STGEN_SEL,
 299         _DSI_SEL,
 300         _ADC12_SEL,
 301         _PARENT_SEL_NB,
 302         _UNKNOWN_SEL = 0xff,
 303 };
 304
 305 enum stm32mp1_pll_id {
 306         _PLL1,
 307         _PLL2,
 308         _PLL3,
 309         _PLL4,
 310         _PLL_NB
 311 };
 312
 313 enum stm32mp1_div_id {
 314         _DIV_P,
 315         _DIV_Q,
 316         _DIV_R,
 317         _DIV_NB,
 318 };
 319
 320 enum stm32mp1_clksrc_id {
 321         CLKSRC_MPU,
 322         CLKSRC_AXI,
 323         CLKSRC_MCU,
 324         CLKSRC_PLL12,
 325         CLKSRC_PLL3,
 326         CLKSRC_PLL4,
 327         CLKSRC_RTC,
 328         CLKSRC_MCO1,
 329         CLKSRC_MCO2,
 330         CLKSRC_NB
 331 };
 332
 333 enum stm32mp1_clkdiv_id {
 334         CLKDIV_MPU,
 335         CLKDIV_AXI,
 336         CLKDIV_MCU,
 337         CLKDIV_APB1,
 338         CLKDIV_APB2,
 339         CLKDIV_APB3,
 340         CLKDIV_APB4,
 341         CLKDIV_APB5,
 342         CLKDIV_RTC,
 343         CLKDIV_MCO1,
 344         CLKDIV_MCO2,
 345         CLKDIV_NB
 346 };
 347
 348 enum stm32mp1_pllcfg {
 349         PLLCFG_M,
 350         PLLCFG_N,
 351         PLLCFG_P,
 352         PLLCFG_Q,
 353         PLLCFG_R,
 354         PLLCFG_O,
 355         PLLCFG_NB
 356 };
 357
 358 enum stm32mp1_pllcsg {
 359         PLLCSG_MOD_PER,
 360         PLLCSG_INC_STEP,
 361         PLLCSG_SSCG_MODE,
 362         PLLCSG_NB
 363 };
 364
 365 enum stm32mp1_plltype {
 366         PLL_800,
 367         PLL_1600,
 368         PLL_TYPE_NB
 369 };
 370
 371 struct stm32mp1_pll {
 372         u8 refclk_min;
 373         u8 refclk_max;
 374         u8 divn_max;
 375 };
 376
 377 struct stm32mp1_clk_gate {
 378         u16 offset;
 379         u8 bit;
 380         u8 index;
 381         u8 set_clr;
 382         u8 sel;
 383         u8 fixed;
 384 };
 385
 386 struct stm32mp1_clk_sel {
 387         u16 offset;
 388         u8 src;
 389         u8 msk;
 390         u8 nb_parent;
 391         const u8 *parent;
 392 };
 393
 394 #define REFCLK_SIZE 4
 395 struct stm32mp1_clk_pll {
 396         enum stm32mp1_plltype plltype;
 397         u16 rckxselr;
 398         u16 pllxcfgr1;
 399         u16 pllxcfgr2;
 400         u16 pllxfracr;
 401         u16 pllxcr;
 402         u16 pllxcsgr;
 403         u8 refclk[REFCLK_SIZE];
 404 };
 405
 406 struct stm32mp1_clk_data {
 407         const struct stm32mp1_clk_gate *gate;
 408         const struct stm32mp1_clk_sel *sel;
 409         const struct stm32mp1_clk_pll *pll;
 410         const int nb_gate;
 411 };
 412
 413 struct stm32mp1_clk_priv {
 414         fdt_addr_t base;
 415         const struct stm32mp1_clk_data *data;
 416         ulong osc[NB_OSC];
 417         struct udevice *osc_dev[NB_OSC];
 418 };
 419
 420 #define STM32MP1_CLK(off, b, idx, s)            \
 421         {                                       \
 422                 .offset = (off),                \
 423                 .bit = (b),                     \
 424                 .index = (idx),                 \
 425                 .set_clr = 0,                   \
 426                 .sel = (s),                     \
 427                 .fixed = _UNKNOWN_ID,           \
 428         }
 429
 430 #define STM32MP1_CLK_F(off, b, idx, f)          \
 431         {                                       \
 432                 .offset = (off),                \
 433                 .bit = (b),                     \
 434                 .index = (idx),                 \
 435                 .set_clr = 0,                   \
 436                 .sel = _UNKNOWN_SEL,            \
 437                 .fixed = (f),                   \
 438         }
 439
 440 #define STM32MP1_CLK_SET_CLR(off, b, idx, s)    \
 441         {                                       \
 442                 .offset = (off),                \
 443                 .bit = (b),                     \
 444                 .index = (idx),                 \
 445                 .set_clr = 1,                   \
 446                 .sel = (s),                     \
 447                 .fixed = _UNKNOWN_ID,           \
 448         }
 449
 450 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f)  \
 451         {                                       \
 452                 .offset = (off),                \
 453                 .bit = (b),                     \
 454                 .index = (idx),                 \
 455                 .set_clr = 1,                   \
 456                 .sel = _UNKNOWN_SEL,            \
 457                 .fixed = (f),                   \
 458         }
 459
 460 #define STM32MP1_CLK_PARENT(idx, off, s, m, p)   \
 461         [(idx)] = {                             \
 462                 .offset = (off),                \
 463                 .src = (s),                     \
 464                 .msk = (m),                     \
 465                 .parent = (p),                  \
 466                 .nb_parent = ARRAY_SIZE((p))    \
 467         }
 468
 469 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
 470                         p1, p2, p3, p4) \
 471         [(idx)] = {                             \
 472                 .plltype = (type),                      \
 473                 .rckxselr = (off1),             \
 474                 .pllxcfgr1 = (off2),            \
 475                 .pllxcfgr2 = (off3),            \
 476                 .pllxfracr = (off4),            \
 477                 .pllxcr = (off5),               \
 478                 .pllxcsgr = (off6),             \
 479                 .refclk[0] = (p1),              \
 480                 .refclk[1] = (p2),              \
 481                 .refclk[2] = (p3),              \
 482                 .refclk[3] = (p4),              \
 483         }
 484
 485 static const u8 stm32mp1_clks[][2] = {
 486         {CK_PER, _CK_PER},
 487         {CK_MPU, _CK_MPU},
 488         {CK_AXI, _ACLK},
 489         {CK_MCU, _CK_MCU},
 490         {CK_HSE, _HSE},
 491         {CK_CSI, _CSI},
 492         {CK_LSI, _LSI},
 493         {CK_LSE, _LSE},
 494         {CK_HSI, _HSI},
 495         {CK_HSE_DIV2, _HSE_KER_DIV2},
 496 };
 497
 498 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 499         STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
 500         STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
 501         STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
 502         STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
 503         STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
 504         STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
 505         STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
 506         STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
 507         STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
 508         STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
 509         STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
 510
 511         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
 512         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
 513         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
 514         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
 515         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
 516         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
 517         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
 518         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
 519         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
 520         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
 521
 522         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 523
 524         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
 525
 526         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
 527         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
 528         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
 529         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
 530         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
 531         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
 532
 533         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
 534         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
 535
 536         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
 537         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
 538         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
 539         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
 540
 541         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
 542         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
 543
 544         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
 545         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
 546         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
 547         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
 548         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
 549         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
 550         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
 551         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
 552         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
 553         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
 554         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 555
 556         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
 557
 558         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _ETH_SEL),
 559         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
 560         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
 561         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
 562         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
 563         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
 564         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
 565         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
 566         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
 567
 568         STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
 569 };
 570
 571 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 572 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 573 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
 574 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
 575                                         _HSE_KER};
 576 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 577                                          _HSE_KER};
 578 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 579                                          _HSE_KER};
 580 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 581                                          _HSE_KER};
 582 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
 583 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
 584 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
 585 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 586 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 587 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
 588 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
 589 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
 590 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
 591 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
 592
 593 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
 594         STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
 595         STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
 596         STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
 597         STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
 598         STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
 599                             uart24_parents),
 600         STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
 601                             uart35_parents),
 602         STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
 603                             uart78_parents),
 604         STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
 605                             sdmmc12_parents),
 606         STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
 607                             sdmmc3_parents),
 608         STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
 609         STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
 610         STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
 611         STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
 612         STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
 613         STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
 614         STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
 615         STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
 616 };
 617
 618 #ifdef STM32MP1_CLOCK_TREE_INIT
 619 /* define characteristic of PLL according type */
 620 #define DIVN_MIN        24
 621 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
 622         [PLL_800] = {
 623                 .refclk_min = 4,
 624                 .refclk_max = 16,
 625                 .divn_max = 99,
 626                 },
 627         [PLL_1600] = {
 628                 .refclk_min = 8,
 629                 .refclk_max = 16,
 630                 .divn_max = 199,
 631                 },
 632 };
 633 #endif /* STM32MP1_CLOCK_TREE_INIT */
 634
 635 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
 636         STM32MP1_CLK_PLL(_PLL1, PLL_1600,
 637                          RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
 638                          RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
 639                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 640         STM32MP1_CLK_PLL(_PLL2, PLL_1600,
 641                          RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
 642                          RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
 643                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 644         STM32MP1_CLK_PLL(_PLL3, PLL_800,
 645                          RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
 646                          RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
 647                          _HSI, _HSE, _CSI, _UNKNOWN_ID),
 648         STM32MP1_CLK_PLL(_PLL4, PLL_800,
 649                          RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
 650                          RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
 651                          _HSI, _HSE, _CSI, _I2S_CKIN),
 652 };
 653
 654 /* Prescaler table lookups for clock computation */
 655 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
 656 static const u8 stm32mp1_mcu_div[16] = {
 657         0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
 658 };
 659
 660 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
 661 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
 662 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
 663 static const u8 stm32mp1_mpu_apbx_div[8] = {
 664         0, 1, 2, 3, 4, 4, 4, 4
 665 };
 666
 667 /* div = /1 /2 /3 /4 */
 668 static const u8 stm32mp1_axi_div[8] = {
 669         1, 2, 3, 4, 4, 4, 4, 4
 670 };
 671
 672 static const __maybe_unused
 673 char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
 674         [_HSI] = "HSI",
 675         [_HSE] = "HSE",
 676         [_CSI] = "CSI",
 677         [_LSI] = "LSI",
 678         [_LSE] = "LSE",
 679         [_I2S_CKIN] = "I2S_CKIN",
 680         [_HSI_KER] = "HSI_KER",
 681         [_HSE_KER] = "HSE_KER",
 682         [_HSE_KER_DIV2] = "HSE_KER_DIV2",
 683         [_CSI_KER] = "CSI_KER",
 684         [_PLL1_P] = "PLL1_P",
 685         [_PLL1_Q] = "PLL1_Q",
 686         [_PLL1_R] = "PLL1_R",
 687         [_PLL2_P] = "PLL2_P",
 688         [_PLL2_Q] = "PLL2_Q",
 689         [_PLL2_R] = "PLL2_R",
 690         [_PLL3_P] = "PLL3_P",
 691         [_PLL3_Q] = "PLL3_Q",
 692         [_PLL3_R] = "PLL3_R",
 693         [_PLL4_P] = "PLL4_P",
 694         [_PLL4_Q] = "PLL4_Q",
 695         [_PLL4_R] = "PLL4_R",
 696         [_ACLK] = "ACLK",
 697         [_PCLK1] = "PCLK1",
 698         [_PCLK2] = "PCLK2",
 699         [_PCLK3] = "PCLK3",
 700         [_PCLK4] = "PCLK4",
 701         [_PCLK5] = "PCLK5",
 702         [_HCLK6] = "KCLK6",
 703         [_HCLK2] = "HCLK2",
 704         [_CK_PER] = "CK_PER",
 705         [_CK_MPU] = "CK_MPU",
 706         [_CK_MCU] = "CK_MCU",
 707         [_USB_PHY_48] = "USB_PHY_48",
 708         [_DSI_PHY] = "DSI_PHY_PLL",
 709 };
 710
 711 static const __maybe_unused
 712 char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
 713         [_I2C12_SEL] = "I2C12",
 714         [_I2C35_SEL] = "I2C35",
 715         [_I2C46_SEL] = "I2C46",
 716         [_UART6_SEL] = "UART6",
 717         [_UART24_SEL] = "UART24",
 718         [_UART35_SEL] = "UART35",
 719         [_UART78_SEL] = "UART78",
 720         [_SDMMC12_SEL] = "SDMMC12",
 721         [_SDMMC3_SEL] = "SDMMC3",
 722         [_ETH_SEL] = "ETH",
 723         [_QSPI_SEL] = "QSPI",
 724         [_FMC_SEL] = "FMC",
 725         [_USBPHY_SEL] = "USBPHY",
 726         [_USBO_SEL] = "USBO",
 727         [_STGEN_SEL] = "STGEN",
 728         [_DSI_SEL] = "DSI",
 729         [_ADC12_SEL] = "ADC12",
 730 };
 731
 732 static const struct stm32mp1_clk_data stm32mp1_data = {
 733         .gate = stm32mp1_clk_gate,
 734         .sel = stm32mp1_clk_sel,
 735         .pll = stm32mp1_clk_pll,
 736         .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
 737 };
 738
 739 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
 740 {
 741         if (idx >= NB_OSC) {
 742                 debug("%s: clk id %d not found\n", __func__, idx);
 743                 return 0;
 744         }
 745
 746         debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
 747               (u32)priv->osc[idx], priv->osc[idx] / 1000);
 748
 749         return priv->osc[idx];
 750 }
 751
 752 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
 753 {
 754         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 755         int i, nb_clks = priv->data->nb_gate;
 756
 757         for (i = 0; i < nb_clks; i++) {
 758                 if (gate[i].index == id)
 759                         break;
 760         }
 761
 762         if (i == nb_clks) {
 763                 printf("%s: clk id %d not found\n", __func__, (u32)id);
 764                 return -EINVAL;
 765         }
 766
 767         return i;
 768 }
 769
 770 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
 771                                 int i)
 772 {
 773         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 774
 775         if (gate[i].sel > _PARENT_SEL_NB) {
 776                 printf("%s: parents for clk id %d not found\n",
 777                        __func__, i);
 778                 return -EINVAL;
 779         }
 780
 781         return gate[i].sel;
 782 }
 783
 784 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
 785                                          int i)
 786 {
 787         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 788
 789         if (gate[i].fixed == _UNKNOWN_ID)
 790                 return -ENOENT;
 791
 792         return gate[i].fixed;
 793 }
 794
 795 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
 796                                    unsigned long id)
 797 {
 798         const struct stm32mp1_clk_sel *sel = priv->data->sel;
 799         int i;
 800         int s, p;
 801
 802         for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
 803                 if (stm32mp1_clks[i][0] == id)
 804                         return stm32mp1_clks[i][1];
 805
 806         i = stm32mp1_clk_get_id(priv, id);
 807         if (i < 0)
 808                 return i;
 809
 810         p = stm32mp1_clk_get_fixed_parent(priv, i);
 811         if (p >= 0 && p < _PARENT_NB)
 812                 return p;
 813
 814         s = stm32mp1_clk_get_sel(priv, i);
 815         if (s < 0)
 816                 return s;
 817
 818         p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
 819
 820         if (p < sel[s].nb_parent) {
 821 #ifdef DEBUG
 822                 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
 823                       stm32mp1_clk_parent_name[sel[s].parent[p]],
 824                       stm32mp1_clk_parent_sel_name[s],
 825                       (u32)id);
 826 #endif
 827                 return sel[s].parent[p];
 828         }
 829
 830         pr_err("%s: no parents defined for clk id %d\n",
 831                __func__, (u32)id);
 832
 833         return -EINVAL;
 834 }
 835
 836 static ulong  pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
 837                               int pll_id)
 838 {
 839         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 840         u32 selr;
 841         int src;
 842         ulong refclk;
 843
 844         /* Get current refclk */
 845         selr = readl(priv->base + pll[pll_id].rckxselr);
 846         src = selr & RCC_SELR_SRC_MASK;
 847
 848         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
 849         debug("PLL%d : selr=%x refclk = %d kHz\n",
 850               pll_id, selr, (u32)(refclk / 1000));
 851
 852         return refclk;
 853 }
 854
 855 /*
 856  * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
 857  * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
 858  * - PLL3 & PLL4 => return VCO     with Fpll_y_ck = FVCO / (DIVy + 1)
 859  * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
 860  */
 861 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
 862                           int pll_id)
 863 {
 864         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 865         int divm, divn;
 866         ulong refclk, fvco;
 867         u32 cfgr1, fracr;
 868
 869         cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
 870         fracr = readl(priv->base + pll[pll_id].pllxfracr);
 871
 872         divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
 873         divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
 874
 875         debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n",
 876               pll_id, cfgr1, fracr, divn, divm);
 877
 878         refclk = pll_get_fref_ck(priv, pll_id);
 879
 880         /* with FRACV :
 881          *   Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
 882          * without FRACV
 883          *   Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
 884          */
 885         if (fracr & RCC_PLLNFRACR_FRACLE) {
 886                 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
 887                             >> RCC_PLLNFRACR_FRACV_SHIFT;
 888                 fvco = (ulong)lldiv((unsigned long long)refclk *
 889                                      (((divn + 1) << 13) + fracv),
 890                                      ((unsigned long long)(divm + 1)) << 13);
 891         } else {
 892                 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
 893         }
 894         debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco);
 895
 896         return fvco;
 897 }
 898
 899 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
 900                                     int pll_id, int div_id)
 901 {
 902         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 903         int divy;
 904         ulong dfout;
 905         u32 cfgr2;
 906
 907         debug("%s(%d, %d)\n", __func__, pll_id, div_id);
 908         if (div_id >= _DIV_NB)
 909                 return 0;
 910
 911         cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
 912         divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
 913
 914         debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy);
 915
 916         dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
 917         debug("        => dfout = %d kHz\n", (u32)(dfout / 1000));
 918
 919         return dfout;
 920 }
 921
 922 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
 923 {
 924         u32 reg;
 925         ulong clock = 0;
 926
 927         switch (p) {
 928         case _CK_MPU:
 929         /* MPU sub system */
 930                 reg = readl(priv->base + RCC_MPCKSELR);
 931                 switch (reg & RCC_SELR_SRC_MASK) {
 932                 case RCC_MPCKSELR_HSI:
 933                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 934                         break;
 935                 case RCC_MPCKSELR_HSE:
 936                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 937                         break;
 938                 case RCC_MPCKSELR_PLL:
 939                 case RCC_MPCKSELR_PLL_MPUDIV:
 940                         clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
 941                         if (p == RCC_MPCKSELR_PLL_MPUDIV) {
 942                                 reg = readl(priv->base + RCC_MPCKDIVR);
 943                                 clock /= stm32mp1_mpu_div[reg &
 944                                                           RCC_MPUDIV_MASK];
 945                         }
 946                         break;
 947                 }
 948                 break;
 949         /* AXI sub system */
 950         case _ACLK:
 951         case _HCLK2:
 952         case _HCLK6:
 953         case _PCLK4:
 954         case _PCLK5:
 955                 reg = readl(priv->base + RCC_ASSCKSELR);
 956                 switch (reg & RCC_SELR_SRC_MASK) {
 957                 case RCC_ASSCKSELR_HSI:
 958                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 959                         break;
 960                 case RCC_ASSCKSELR_HSE:
 961                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 962                         break;
 963                 case RCC_ASSCKSELR_PLL:
 964                         clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
 965                         break;
 966                 }
 967
 968                 /* System clock divider */
 969                 reg = readl(priv->base + RCC_AXIDIVR);
 970                 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
 971
 972                 switch (p) {
 973                 case _PCLK4:
 974                         reg = readl(priv->base + RCC_APB4DIVR);
 975                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 976                         break;
 977                 case _PCLK5:
 978                         reg = readl(priv->base + RCC_APB5DIVR);
 979                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 980                         break;
 981                 default:
 982                         break;
 983                 }
 984                 break;
 985         /* MCU sub system */
 986         case _CK_MCU:
 987         case _PCLK1:
 988         case _PCLK2:
 989         case _PCLK3:
 990                 reg = readl(priv->base + RCC_MSSCKSELR);
 991                 switch (reg & RCC_SELR_SRC_MASK) {
 992                 case RCC_MSSCKSELR_HSI:
 993                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 994                         break;
 995                 case RCC_MSSCKSELR_HSE:
 996                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 997                         break;
 998                 case RCC_MSSCKSELR_CSI:
 999                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1000                         break;
1001                 case RCC_MSSCKSELR_PLL:
1002                         clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
1003                         break;
1004                 }
1005
1006                 /* MCU clock divider */
1007                 reg = readl(priv->base + RCC_MCUDIVR);
1008                 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1009
1010                 switch (p) {
1011                 case _PCLK1:
1012                         reg = readl(priv->base + RCC_APB1DIVR);
1013                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1014                         break;
1015                 case _PCLK2:
1016                         reg = readl(priv->base + RCC_APB2DIVR);
1017                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1018                         break;
1019                 case _PCLK3:
1020                         reg = readl(priv->base + RCC_APB3DIVR);
1021                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1022                         break;
1023                 case _CK_MCU:
1024                 default:
1025                         break;
1026                 }
1027                 break;
1028         case _CK_PER:
1029                 reg = readl(priv->base + RCC_CPERCKSELR);
1030                 switch (reg & RCC_SELR_SRC_MASK) {
1031                 case RCC_CPERCKSELR_HSI:
1032                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1033                         break;
1034                 case RCC_CPERCKSELR_HSE:
1035                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1036                         break;
1037                 case RCC_CPERCKSELR_CSI:
1038                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1039                         break;
1040                 }
1041                 break;
1042         case _HSI:
1043         case _HSI_KER:
1044                 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1045                 break;
1046         case _CSI:
1047         case _CSI_KER:
1048                 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1049                 break;
1050         case _HSE:
1051         case _HSE_KER:
1052         case _HSE_KER_DIV2:
1053                 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1054                 if (p == _HSE_KER_DIV2)
1055                         clock >>= 1;
1056                 break;
1057         case _LSI:
1058                 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1059                 break;
1060         case _LSE:
1061                 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1062                 break;
1063         /* PLL */
1064         case _PLL1_P:
1065         case _PLL1_Q:
1066         case _PLL1_R:
1067                 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1068                 break;
1069         case _PLL2_P:
1070         case _PLL2_Q:
1071         case _PLL2_R:
1072                 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1073                 break;
1074         case _PLL3_P:
1075         case _PLL3_Q:
1076         case _PLL3_R:
1077                 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1078                 break;
1079         case _PLL4_P:
1080         case _PLL4_Q:
1081         case _PLL4_R:
1082                 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1083                 break;
1084         /* other */
1085         case _USB_PHY_48:
1086                 clock = 48000000;
1087                 break;
1088         case _DSI_PHY:
1089         {
1090                 struct clk clk;
1091                 struct udevice *dev = NULL;
1092
1093                 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1094                                                &dev)) {
1095                         if (clk_request(dev, &clk)) {
1096                                 pr_err("ck_dsi_phy request");
1097                         } else {
1098                                 clk.id = 0;
1099                                 clock = clk_get_rate(&clk);
1100                         }
1101                 }
1102                 break;
1103         }
1104         default:
1105                 break;
1106         }
1107
1108         debug("%s(%d) clock = %lx : %ld kHz\n",
1109               __func__, p, clock, clock / 1000);
1110
1111         return clock;
1112 }
1113
1114 static int stm32mp1_clk_enable(struct clk *clk)
1115 {
1116         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1117         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1118         int i = stm32mp1_clk_get_id(priv, clk->id);
1119
1120         if (i < 0)
1121                 return i;
1122
1123         if (gate[i].set_clr)
1124                 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1125         else
1126                 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1127
1128         debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1129
1130         return 0;
1131 }
1132
1133 static int stm32mp1_clk_disable(struct clk *clk)
1134 {
1135         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1136         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1137         int i = stm32mp1_clk_get_id(priv, clk->id);
1138
1139         if (i < 0)
1140                 return i;
1141
1142         if (gate[i].set_clr)
1143                 writel(BIT(gate[i].bit),
1144                        priv->base + gate[i].offset
1145                        + RCC_MP_ENCLRR_OFFSET);
1146         else
1147                 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1148
1149         debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1150
1151         return 0;
1152 }
1153
1154 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1155 {
1156         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1157         int p = stm32mp1_clk_get_parent(priv, clk->id);
1158         ulong rate;
1159
1160         if (p < 0)
1161                 return 0;
1162
1163         rate = stm32mp1_clk_get(priv, p);
1164
1165 #ifdef DEBUG
1166         debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1167               __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1168 #endif
1169         return rate;
1170 }
1171
1172 #ifdef STM32MP1_CLOCK_TREE_INIT
1173 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1174                                 u32 mask_on)
1175 {
1176         u32 address = rcc + offset;
1177
1178         if (enable)
1179                 setbits_le32(address, mask_on);
1180         else
1181                 clrbits_le32(address, mask_on);
1182 }
1183
1184 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1185 {
1186         writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
1187 }
1188
1189 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1190                              u32 mask_rdy)
1191 {
1192         u32 mask_test = 0;
1193         u32 address = rcc + offset;
1194         u32 val;
1195         int ret;
1196
1197         if (enable)
1198                 mask_test = mask_rdy;
1199
1200         ret = readl_poll_timeout(address, val,
1201                                  (val & mask_rdy) == mask_test,
1202                                  TIMEOUT_1S);
1203
1204         if (ret)
1205                 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1206                        mask_rdy, address, enable, readl(address));
1207
1208         return ret;
1209 }
1210
1211 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
1212                                 int lsedrv)
1213 {
1214         u32 value;
1215
1216         if (digbyp)
1217                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
1218
1219         if (bypass || digbyp)
1220                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1221
1222         /*
1223          * warning: not recommended to switch directly from "high drive"
1224          * to "medium low drive", and vice-versa.
1225          */
1226         value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1227                 >> RCC_BDCR_LSEDRV_SHIFT;
1228
1229         while (value != lsedrv) {
1230                 if (value > lsedrv)
1231                         value--;
1232                 else
1233                         value++;
1234
1235                 clrsetbits_le32(rcc + RCC_BDCR,
1236                                 RCC_BDCR_LSEDRV_MASK,
1237                                 value << RCC_BDCR_LSEDRV_SHIFT);
1238         }
1239
1240         stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1241 }
1242
1243 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1244 {
1245         stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1246 }
1247
1248 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1249 {
1250         stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1251         stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1252 }
1253
1254 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
1255 {
1256         if (digbyp)
1257                 writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
1258         if (bypass || digbyp)
1259                 writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
1260
1261         stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1262         stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1263
1264         if (css)
1265                 writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
1266 }
1267
1268 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1269 {
1270         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
1271         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1272 }
1273
1274 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1275 {
1276         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1277         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1278 }
1279
1280 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1281 {
1282         u32 address = rcc + RCC_OCRDYR;
1283         u32 val;
1284         int ret;
1285
1286         clrsetbits_le32(rcc + RCC_HSICFGR,
1287                         RCC_HSICFGR_HSIDIV_MASK,
1288                         RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1289
1290         ret = readl_poll_timeout(address, val,
1291                                  val & RCC_OCRDYR_HSIDIVRDY,
1292                                  TIMEOUT_200MS);
1293         if (ret)
1294                 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1295                        address, readl(address));
1296
1297         return ret;
1298 }
1299
1300 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1301 {
1302         u8 hsidiv;
1303         u32 hsidivfreq = MAX_HSI_HZ;
1304
1305         for (hsidiv = 0; hsidiv < 4; hsidiv++,
1306              hsidivfreq = hsidivfreq / 2)
1307                 if (hsidivfreq == hsifreq)
1308                         break;
1309
1310         if (hsidiv == 4) {
1311                 pr_err("clk-hsi frequency invalid");
1312                 return -1;
1313         }
1314
1315         if (hsidiv > 0)
1316                 return stm32mp1_set_hsidiv(rcc, hsidiv);
1317
1318         return 0;
1319 }
1320
1321 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1322 {
1323         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1324
1325         clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
1326                         RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1327                         RCC_PLLNCR_DIVREN,
1328                         RCC_PLLNCR_PLLON);
1329 }
1330
1331 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1332 {
1333         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1334         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1335         u32 val;
1336         int ret;
1337
1338         ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1339                                  TIMEOUT_200MS);
1340
1341         if (ret) {
1342                 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1343                        pll_id, pllxcr, readl(pllxcr));
1344                 return ret;
1345         }
1346
1347         /* start the requested output */
1348         setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1349
1350         return 0;
1351 }
1352
1353 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1354 {
1355         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1356         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1357         u32 val;
1358
1359         /* stop all output */
1360         clrbits_le32(pllxcr,
1361                      RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1362
1363         /* stop PLL */
1364         clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1365
1366         /* wait PLL stopped */
1367         return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1368                                   TIMEOUT_200MS);
1369 }
1370
1371 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1372                               int pll_id, u32 *pllcfg)
1373 {
1374         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1375         fdt_addr_t rcc = priv->base;
1376         u32 value;
1377
1378         value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1379                 & RCC_PLLNCFGR2_DIVP_MASK;
1380         value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1381                  & RCC_PLLNCFGR2_DIVQ_MASK;
1382         value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1383                  & RCC_PLLNCFGR2_DIVR_MASK;
1384         writel(value, rcc + pll[pll_id].pllxcfgr2);
1385 }
1386
1387 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1388                       u32 *pllcfg, u32 fracv)
1389 {
1390         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1391         fdt_addr_t rcc = priv->base;
1392         enum stm32mp1_plltype type = pll[pll_id].plltype;
1393         int src;
1394         ulong refclk;
1395         u8 ifrge = 0;
1396         u32 value;
1397
1398         src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1399
1400         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1401                  (pllcfg[PLLCFG_M] + 1);
1402
1403         if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1404             refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1405                 debug("invalid refclk = %x\n", (u32)refclk);
1406                 return -EINVAL;
1407         }
1408         if (type == PLL_800 && refclk >= 8000000)
1409                 ifrge = 1;
1410
1411         value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1412                  & RCC_PLLNCFGR1_DIVN_MASK;
1413         value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1414                  & RCC_PLLNCFGR1_DIVM_MASK;
1415         value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1416                  & RCC_PLLNCFGR1_IFRGE_MASK;
1417         writel(value, rcc + pll[pll_id].pllxcfgr1);
1418
1419         /* fractional configuration: load sigma-delta modulator (SDM) */
1420
1421         /* Write into FRACV the new fractional value , and FRACLE to 0 */
1422         writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1423                rcc + pll[pll_id].pllxfracr);
1424
1425         /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1426         setbits_le32(rcc + pll[pll_id].pllxfracr,
1427                      RCC_PLLNFRACR_FRACLE);
1428
1429         pll_config_output(priv, pll_id, pllcfg);
1430
1431         return 0;
1432 }
1433
1434 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1435 {
1436         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1437         u32 pllxcsg;
1438
1439         pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1440                     RCC_PLLNCSGR_MOD_PER_MASK) |
1441                   ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1442                     RCC_PLLNCSGR_INC_STEP_MASK) |
1443                   ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1444                     RCC_PLLNCSGR_SSCG_MODE_MASK);
1445
1446         writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1447
1448         setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
1449 }
1450
1451 static  __maybe_unused int pll_set_rate(struct udevice *dev,
1452                                         int pll_id,
1453                                         int div_id,
1454                                         unsigned long clk_rate)
1455 {
1456         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1457         unsigned int pllcfg[PLLCFG_NB];
1458         ofnode plloff;
1459         char name[12];
1460         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1461         enum stm32mp1_plltype type = pll[pll_id].plltype;
1462         int divm, divn, divy;
1463         int ret;
1464         ulong fck_ref;
1465         u32 fracv;
1466         u64 value;
1467
1468         if (div_id > _DIV_NB)
1469                 return -EINVAL;
1470
1471         sprintf(name, "st,pll@%d", pll_id);
1472         plloff = dev_read_subnode(dev, name);
1473         if (!ofnode_valid(plloff))
1474                 return -FDT_ERR_NOTFOUND;
1475
1476         ret = ofnode_read_u32_array(plloff, "cfg",
1477                                     pllcfg, PLLCFG_NB);
1478         if (ret < 0)
1479                 return -FDT_ERR_NOTFOUND;
1480
1481         fck_ref = pll_get_fref_ck(priv, pll_id);
1482
1483         divm = pllcfg[PLLCFG_M];
1484         /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
1485         divy = pllcfg[PLLCFG_P + div_id];
1486
1487         /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
1488          * So same final result than PLL2 et 4
1489          * with FRACV
1490          * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
1491          *             / (DIVy + 1) * (DIVM + 1)
1492          * value = (DIVN + 1) * 2^13 + FRACV / 2^13
1493          *       = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
1494          */
1495         value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
1496         value = lldiv(value, fck_ref);
1497
1498         divn = (value >> 13) - 1;
1499         if (divn < DIVN_MIN ||
1500             divn > stm32mp1_pll[type].divn_max) {
1501                 pr_err("divn invalid = %d", divn);
1502                 return -EINVAL;
1503         }
1504         fracv = value - ((divn + 1) << 13);
1505         pllcfg[PLLCFG_N] = divn;
1506
1507         /* reconfigure PLL */
1508         pll_stop(priv, pll_id);
1509         pll_config(priv, pll_id, pllcfg, fracv);
1510         pll_start(priv, pll_id);
1511         pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
1512
1513         return 0;
1514 }
1515
1516 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1517 {
1518         u32 address = priv->base + (clksrc >> 4);
1519         u32 val;
1520         int ret;
1521
1522         clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1523         ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1524                                  TIMEOUT_200MS);
1525         if (ret)
1526                 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1527                        clksrc, address, readl(address));
1528
1529         return ret;
1530 }
1531
1532 static void stgen_config(struct stm32mp1_clk_priv *priv)
1533 {
1534         int p;
1535         u32 stgenc, cntfid0;
1536         ulong rate;
1537
1538         stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
1539
1540         cntfid0 = readl(stgenc + STGENC_CNTFID0);
1541         p = stm32mp1_clk_get_parent(priv, STGEN_K);
1542         rate = stm32mp1_clk_get(priv, p);
1543
1544         if (cntfid0 != rate) {
1545                 u64 counter;
1546
1547                 pr_debug("System Generic Counter (STGEN) update\n");
1548                 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1549                 counter = (u64)readl(stgenc + STGENC_CNTCVL);
1550                 counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
1551                 counter = lldiv(counter * (u64)rate, cntfid0);
1552                 writel((u32)counter, stgenc + STGENC_CNTCVL);
1553                 writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
1554                 writel(rate, stgenc + STGENC_CNTFID0);
1555                 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1556
1557                 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1558
1559                 /* need to update gd->arch.timer_rate_hz with new frequency */
1560                 timer_init();
1561                 pr_debug("gd->arch.timer_rate_hz = %x\n",
1562                          (u32)gd->arch.timer_rate_hz);
1563                 pr_debug("Tick = %x\n", (u32)(get_ticks()));
1564         }
1565 }
1566
1567 static int set_clkdiv(unsigned int clkdiv, u32 address)
1568 {
1569         u32 val;
1570         int ret;
1571
1572         clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1573         ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1574                                  TIMEOUT_200MS);
1575         if (ret)
1576                 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1577                        clkdiv, address, readl(address));
1578
1579         return ret;
1580 }
1581
1582 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1583                              u32 clksrc, u32 clkdiv)
1584 {
1585         u32 address = priv->base + (clksrc >> 4);
1586
1587         /*
1588          * binding clksrc : bit15-4 offset
1589          *                  bit3:   disable
1590          *                  bit2-0: MCOSEL[2:0]
1591          */
1592         if (clksrc & 0x8) {
1593                 clrbits_le32(address, RCC_MCOCFG_MCOON);
1594         } else {
1595                 clrsetbits_le32(address,
1596                                 RCC_MCOCFG_MCOSRC_MASK,
1597                                 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1598                 clrsetbits_le32(address,
1599                                 RCC_MCOCFG_MCODIV_MASK,
1600                                 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1601                 setbits_le32(address, RCC_MCOCFG_MCOON);
1602         }
1603 }
1604
1605 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1606                        unsigned int clksrc,
1607                        int lse_css)
1608 {
1609         u32 address = priv->base + RCC_BDCR;
1610
1611         if (readl(address) & RCC_BDCR_RTCCKEN)
1612                 goto skip_rtc;
1613
1614         if (clksrc == CLK_RTC_DISABLED)
1615                 goto skip_rtc;
1616
1617         clrsetbits_le32(address,
1618                         RCC_BDCR_RTCSRC_MASK,
1619                         clksrc << RCC_BDCR_RTCSRC_SHIFT);
1620
1621         setbits_le32(address, RCC_BDCR_RTCCKEN);
1622
1623 skip_rtc:
1624         if (lse_css)
1625                 setbits_le32(address, RCC_BDCR_LSECSSON);
1626 }
1627
1628 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1629 {
1630         u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1631         u32 value = pkcs & 0xF;
1632         u32 mask = 0xF;
1633
1634         if (pkcs & BIT(31)) {
1635                 mask <<= 4;
1636                 value <<= 4;
1637         }
1638         clrsetbits_le32(address, mask, value);
1639 }
1640
1641 static int stm32mp1_clktree(struct udevice *dev)
1642 {
1643         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1644         fdt_addr_t rcc = priv->base;
1645         unsigned int clksrc[CLKSRC_NB];
1646         unsigned int clkdiv[CLKDIV_NB];
1647         unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1648         ofnode plloff[_PLL_NB];
1649         int ret;
1650         int i, len;
1651         int lse_css = 0;
1652         const u32 *pkcs_cell;
1653
1654         /* check mandatory field */
1655         ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1656         if (ret < 0) {
1657                 debug("field st,clksrc invalid: error %d\n", ret);
1658                 return -FDT_ERR_NOTFOUND;
1659         }
1660
1661         ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1662         if (ret < 0) {
1663                 debug("field st,clkdiv invalid: error %d\n", ret);
1664                 return -FDT_ERR_NOTFOUND;
1665         }
1666
1667         /* check mandatory field in each pll */
1668         for (i = 0; i < _PLL_NB; i++) {
1669                 char name[12];
1670
1671                 sprintf(name, "st,pll@%d", i);
1672                 plloff[i] = dev_read_subnode(dev, name);
1673                 if (!ofnode_valid(plloff[i]))
1674                         continue;
1675                 ret = ofnode_read_u32_array(plloff[i], "cfg",
1676                                             pllcfg[i], PLLCFG_NB);
1677                 if (ret < 0) {
1678                         debug("field cfg invalid: error %d\n", ret);
1679                         return -FDT_ERR_NOTFOUND;
1680                 }
1681         }
1682
1683         debug("configuration MCO\n");
1684         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1685         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1686
1687         debug("switch ON osillator\n");
1688         /*
1689          * switch ON oscillator found in device-tree,
1690          * HSI already ON after bootrom
1691          */
1692         if (priv->osc[_LSI])
1693                 stm32mp1_lsi_set(rcc, 1);
1694
1695         if (priv->osc[_LSE]) {
1696                 int bypass, digbyp, lsedrv;
1697                 struct udevice *dev = priv->osc_dev[_LSE];
1698
1699                 bypass = dev_read_bool(dev, "st,bypass");
1700                 digbyp = dev_read_bool(dev, "st,digbypass");
1701                 lse_css = dev_read_bool(dev, "st,css");
1702                 lsedrv = dev_read_u32_default(dev, "st,drive",
1703                                               LSEDRV_MEDIUM_HIGH);
1704
1705                 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
1706         }
1707
1708         if (priv->osc[_HSE]) {
1709                 int bypass, digbyp, css;
1710                 struct udevice *dev = priv->osc_dev[_HSE];
1711
1712                 bypass = dev_read_bool(dev, "st,bypass");
1713                 digbyp = dev_read_bool(dev, "st,digbypass");
1714                 css = dev_read_bool(dev, "st,css");
1715
1716                 stm32mp1_hse_enable(rcc, bypass, digbyp, css);
1717         }
1718         /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1719          * => switch on CSI even if node is not present in device tree
1720          */
1721         stm32mp1_csi_set(rcc, 1);
1722
1723         /* come back to HSI */
1724         debug("come back to HSI\n");
1725         set_clksrc(priv, CLK_MPU_HSI);
1726         set_clksrc(priv, CLK_AXI_HSI);
1727         set_clksrc(priv, CLK_MCU_HSI);
1728
1729         debug("pll stop\n");
1730         for (i = 0; i < _PLL_NB; i++)
1731                 pll_stop(priv, i);
1732
1733         /* configure HSIDIV */
1734         debug("configure HSIDIV\n");
1735         if (priv->osc[_HSI]) {
1736                 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
1737                 stgen_config(priv);
1738         }
1739
1740         /* select DIV */
1741         debug("select DIV\n");
1742         /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1743         writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1744         set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1745         set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1746         set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1747         set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1748         set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1749         set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1750         set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1751
1752         /* no ready bit for RTC */
1753         writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1754
1755         /* configure PLLs source */
1756         debug("configure PLLs source\n");
1757         set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1758         set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1759         set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1760
1761         /* configure and start PLLs */
1762         debug("configure PLLs\n");
1763         for (i = 0; i < _PLL_NB; i++) {
1764                 u32 fracv;
1765                 u32 csg[PLLCSG_NB];
1766
1767                 debug("configure PLL %d @ %d\n", i,
1768                       ofnode_to_offset(plloff[i]));
1769                 if (!ofnode_valid(plloff[i]))
1770                         continue;
1771
1772                 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1773                 pll_config(priv, i, pllcfg[i], fracv);
1774                 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1775                 if (!ret) {
1776                         pll_csg(priv, i, csg);
1777                 } else if (ret != -FDT_ERR_NOTFOUND) {
1778                         debug("invalid csg node for pll@%d res=%d\n", i, ret);
1779                         return ret;
1780                 }
1781                 pll_start(priv, i);
1782         }
1783
1784         /* wait and start PLLs ouptut when ready */
1785         for (i = 0; i < _PLL_NB; i++) {
1786                 if (!ofnode_valid(plloff[i]))
1787                         continue;
1788                 debug("output PLL %d\n", i);
1789                 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1790         }
1791
1792         /* wait LSE ready before to use it */
1793         if (priv->osc[_LSE])
1794                 stm32mp1_lse_wait(rcc);
1795
1796         /* configure with expected clock source */
1797         debug("CLKSRC\n");
1798         set_clksrc(priv, clksrc[CLKSRC_MPU]);
1799         set_clksrc(priv, clksrc[CLKSRC_AXI]);
1800         set_clksrc(priv, clksrc[CLKSRC_MCU]);
1801         set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1802
1803         /* configure PKCK */
1804         debug("PKCK\n");
1805         pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1806         if (pkcs_cell) {
1807                 bool ckper_disabled = false;
1808
1809                 for (i = 0; i < len / sizeof(u32); i++) {
1810                         u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1811
1812                         if (pkcs == CLK_CKPER_DISABLED) {
1813                                 ckper_disabled = true;
1814                                 continue;
1815                         }
1816                         pkcs_config(priv, pkcs);
1817                 }
1818                 /* CKPER is source for some peripheral clock
1819                  * (FMC-NAND / QPSI-NOR) and switching source is allowed
1820                  * only if previous clock is still ON
1821                  * => deactivated CKPER only after switching clock
1822                  */
1823                 if (ckper_disabled)
1824                         pkcs_config(priv, CLK_CKPER_DISABLED);
1825         }
1826
1827         /* STGEN clock source can change with CLK_STGEN_XXX */
1828         stgen_config(priv);
1829
1830         debug("oscillator off\n");
1831         /* switch OFF HSI if not found in device-tree */
1832         if (!priv->osc[_HSI])
1833                 stm32mp1_hsi_set(rcc, 0);
1834
1835         /* Software Self-Refresh mode (SSR) during DDR initilialization */
1836         clrsetbits_le32(priv->base + RCC_DDRITFCR,
1837                         RCC_DDRITFCR_DDRCKMOD_MASK,
1838                         RCC_DDRITFCR_DDRCKMOD_SSR <<
1839                         RCC_DDRITFCR_DDRCKMOD_SHIFT);
1840
1841         return 0;
1842 }
1843 #endif /* STM32MP1_CLOCK_TREE_INIT */
1844
1845 static int pll_set_output_rate(struct udevice *dev,
1846                                int pll_id,
1847                                int div_id,
1848                                unsigned long clk_rate)
1849 {
1850         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1851         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1852         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1853         int div;
1854         ulong fvco;
1855
1856         if (div_id > _DIV_NB)
1857                 return -EINVAL;
1858
1859         fvco = pll_get_fvco(priv, pll_id);
1860
1861         if (fvco <= clk_rate)
1862                 div = 1;
1863         else
1864                 div = DIV_ROUND_UP(fvco, clk_rate);
1865
1866         if (div > 128)
1867                 div = 128;
1868
1869         debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div);
1870         /* stop the requested output */
1871         clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1872         /* change divider */
1873         clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
1874                         RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
1875                         (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
1876         /* start the requested output */
1877         setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1878
1879         return 0;
1880 }
1881
1882 static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
1883 {
1884         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1885         int p;
1886
1887         switch (clk->id) {
1888 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
1889         defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
1890         case DDRPHYC:
1891                 break;
1892 #endif
1893         case LTDC_PX:
1894         case DSI_PX:
1895                 break;
1896         default:
1897                 pr_err("not supported");
1898                 return -EINVAL;
1899         }
1900
1901         p = stm32mp1_clk_get_parent(priv, clk->id);
1902         if (p < 0)
1903                 return -EINVAL;
1904
1905         switch (p) {
1906 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
1907         defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
1908         case _PLL2_R: /* DDRPHYC */
1909         {
1910                 /* only for change DDR clock in interactive mode */
1911                 ulong result;
1912
1913                 set_clksrc(priv, CLK_AXI_HSI);
1914                 result = pll_set_rate(clk->dev,  _PLL2, _DIV_R, clk_rate);
1915                 set_clksrc(priv, CLK_AXI_PLL2P);
1916                 return result;
1917         }
1918 #endif
1919         case _PLL4_Q:
1920                 /* for LTDC_PX and DSI_PX case */
1921                 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
1922         }
1923
1924         return -EINVAL;
1925 }
1926
1927 static void stm32mp1_osc_clk_init(const char *name,
1928                                   struct stm32mp1_clk_priv *priv,
1929                                   int index)
1930 {
1931         struct clk clk;
1932         struct udevice *dev = NULL;
1933
1934         priv->osc[index] = 0;
1935         clk.id = 0;
1936         if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1937                 if (clk_request(dev, &clk))
1938                         pr_err("%s request", name);
1939                 else
1940                         priv->osc[index] = clk_get_rate(&clk);
1941         }
1942         priv->osc_dev[index] = dev;
1943 }
1944
1945 static void stm32mp1_osc_init(struct udevice *dev)
1946 {
1947         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1948         int i;
1949         const char *name[NB_OSC] = {
1950                 [_LSI] = "clk-lsi",
1951                 [_LSE] = "clk-lse",
1952                 [_HSI] = "clk-hsi",
1953                 [_HSE] = "clk-hse",
1954                 [_CSI] = "clk-csi",
1955                 [_I2S_CKIN] = "i2s_ckin",
1956         };
1957
1958         for (i = 0; i < NB_OSC; i++) {
1959                 stm32mp1_osc_clk_init(name[i], priv, i);
1960                 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1961         }
1962 }
1963
1964 static void  __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
1965 {
1966         char buf[32];
1967         int i, s, p;
1968
1969         printf("Clocks:\n");
1970         for (i = 0; i < _PARENT_NB; i++) {
1971                 printf("- %s : %s MHz\n",
1972                        stm32mp1_clk_parent_name[i],
1973                        strmhz(buf, stm32mp1_clk_get(priv, i)));
1974         }
1975         printf("Source Clocks:\n");
1976         for (i = 0; i < _PARENT_SEL_NB; i++) {
1977                 p = (readl(priv->base + priv->data->sel[i].offset) >>
1978                      priv->data->sel[i].src) & priv->data->sel[i].msk;
1979                 if (p < priv->data->sel[i].nb_parent) {
1980                         s = priv->data->sel[i].parent[p];
1981                         printf("- %s(%d) => parent %s(%d)\n",
1982                                stm32mp1_clk_parent_sel_name[i], i,
1983                                stm32mp1_clk_parent_name[s], s);
1984                 } else {
1985                         printf("- %s(%d) => parent index %d is invalid\n",
1986                                stm32mp1_clk_parent_sel_name[i], i, p);
1987                 }
1988         }
1989 }
1990
1991 #ifdef CONFIG_CMD_CLK
1992 int soc_clk_dump(void)
1993 {
1994         struct udevice *dev;
1995         struct stm32mp1_clk_priv *priv;
1996         int ret;
1997
1998         ret = uclass_get_device_by_driver(UCLASS_CLK,
1999                                           DM_GET_DRIVER(stm32mp1_clock),
2000                                           &dev);
2001         if (ret)
2002                 return ret;
2003
2004         priv = dev_get_priv(dev);
2005
2006         stm32mp1_clk_dump(priv);
2007
2008         return 0;
2009 }
2010 #endif
2011
2012 static int stm32mp1_clk_probe(struct udevice *dev)
2013 {
2014         int result = 0;
2015         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2016
2017         priv->base = dev_read_addr(dev->parent);
2018         if (priv->base == FDT_ADDR_T_NONE)
2019                 return -EINVAL;
2020
2021         priv->data = (void *)&stm32mp1_data;
2022
2023         if (!priv->data->gate || !priv->data->sel ||
2024             !priv->data->pll)
2025                 return -EINVAL;
2026
2027         stm32mp1_osc_init(dev);
2028
2029 #ifdef STM32MP1_CLOCK_TREE_INIT
2030         /* clock tree init is done only one time, before relocation */
2031         if (!(gd->flags & GD_FLG_RELOC))
2032                 result = stm32mp1_clktree(dev);
2033 #endif
2034
2035 #ifndef CONFIG_SPL_BUILD
2036 #if defined(DEBUG)
2037         /* display debug information for probe after relocation */
2038         if (gd->flags & GD_FLG_RELOC)
2039                 stm32mp1_clk_dump(priv);
2040 #endif
2041
2042 #if defined(CONFIG_DISPLAY_CPUINFO)
2043         if (gd->flags & GD_FLG_RELOC) {
2044                 char buf[32];
2045
2046                 printf("Clocks:\n");
2047                 printf("- MPU : %s MHz\n",
2048                        strmhz(buf, stm32mp1_clk_get(priv, _CK_MPU)));
2049                 printf("- MCU : %s MHz\n",
2050                        strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
2051                 printf("- AXI : %s MHz\n",
2052                        strmhz(buf, stm32mp1_clk_get(priv, _ACLK)));
2053                 printf("- PER : %s MHz\n",
2054                        strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
2055                 /* DDRPHYC father */
2056                 printf("- DDR : %s MHz\n",
2057                        strmhz(buf, stm32mp1_clk_get(priv, _PLL2_R)));
2058         }
2059 #endif /* CONFIG_DISPLAY_CPUINFO */
2060 #endif
2061
2062         return result;
2063 }
2064
2065 static const struct clk_ops stm32mp1_clk_ops = {
2066         .enable = stm32mp1_clk_enable,
2067         .disable = stm32mp1_clk_disable,
2068         .get_rate = stm32mp1_clk_get_rate,
2069         .set_rate = stm32mp1_clk_set_rate,
2070 };
2071
2072 U_BOOT_DRIVER(stm32mp1_clock) = {
2073         .name = "stm32mp1_clk",
2074         .id = UCLASS_CLK,
2075         .ops = &stm32mp1_clk_ops,
2076         .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
2077         .probe = stm32mp1_clk_probe,
2078 };