drivers/clk/clk_stm32mp1.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #define LOG_CATEGORY UCLASS_CLK
   7
   8 #include <common.h>
   9 #include <clk-uclass.h>
  10 #include <div64.h>
  11 #include <dm.h>
  12 #include <init.h>
  13 #include <log.h>
  14 #include <regmap.h>
  15 #include <spl.h>
  16 #include <syscon.h>
  17 #include <time.h>
  18 #include <vsprintf.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/global_data.h>
  21 #include <dm/device_compat.h>
  22 #include <dt-bindings/clock/stm32mp1-clks.h>
  23 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  24 #include <linux/bitops.h>
  25 #include <linux/io.h>
  26 #include <linux/iopoll.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #if defined(CONFIG_SPL_BUILD)
  31 /* activate clock tree initialization in the driver */
  32 #define STM32MP1_CLOCK_TREE_INIT
  33 #endif
  34
  35 #define MAX_HSI_HZ              64000000
  36
  37 /* TIMEOUT */
  38 #define TIMEOUT_200MS           200000
  39 #define TIMEOUT_1S              1000000
  40
  41 /* STGEN registers */
  42 #define STGENC_CNTCR            0x00
  43 #define STGENC_CNTSR            0x04
  44 #define STGENC_CNTCVL           0x08
  45 #define STGENC_CNTCVU           0x0C
  46 #define STGENC_CNTFID0          0x20
  47
  48 #define STGENC_CNTCR_EN         BIT(0)
  49
  50 /* RCC registers */
  51 #define RCC_OCENSETR            0x0C
  52 #define RCC_OCENCLRR            0x10
  53 #define RCC_HSICFGR             0x18
  54 #define RCC_MPCKSELR            0x20
  55 #define RCC_ASSCKSELR           0x24
  56 #define RCC_RCK12SELR           0x28
  57 #define RCC_MPCKDIVR            0x2C
  58 #define RCC_AXIDIVR             0x30
  59 #define RCC_APB4DIVR            0x3C
  60 #define RCC_APB5DIVR            0x40
  61 #define RCC_RTCDIVR             0x44
  62 #define RCC_MSSCKSELR           0x48
  63 #define RCC_PLL1CR              0x80
  64 #define RCC_PLL1CFGR1           0x84
  65 #define RCC_PLL1CFGR2           0x88
  66 #define RCC_PLL1FRACR           0x8C
  67 #define RCC_PLL1CSGR            0x90
  68 #define RCC_PLL2CR              0x94
  69 #define RCC_PLL2CFGR1           0x98
  70 #define RCC_PLL2CFGR2           0x9C
  71 #define RCC_PLL2FRACR           0xA0
  72 #define RCC_PLL2CSGR            0xA4
  73 #define RCC_I2C46CKSELR         0xC0
  74 #define RCC_SPI6CKSELR          0xC4
  75 #define RCC_CPERCKSELR          0xD0
  76 #define RCC_STGENCKSELR         0xD4
  77 #define RCC_DDRITFCR            0xD8
  78 #define RCC_BDCR                0x140
  79 #define RCC_RDLSICR             0x144
  80 #define RCC_MP_APB4ENSETR       0x200
  81 #define RCC_MP_APB5ENSETR       0x208
  82 #define RCC_MP_AHB5ENSETR       0x210
  83 #define RCC_MP_AHB6ENSETR       0x218
  84 #define RCC_OCRDYR              0x808
  85 #define RCC_DBGCFGR             0x80C
  86 #define RCC_RCK3SELR            0x820
  87 #define RCC_RCK4SELR            0x824
  88 #define RCC_MCUDIVR             0x830
  89 #define RCC_APB1DIVR            0x834
  90 #define RCC_APB2DIVR            0x838
  91 #define RCC_APB3DIVR            0x83C
  92 #define RCC_PLL3CR              0x880
  93 #define RCC_PLL3CFGR1           0x884
  94 #define RCC_PLL3CFGR2           0x888
  95 #define RCC_PLL3FRACR           0x88C
  96 #define RCC_PLL3CSGR            0x890
  97 #define RCC_PLL4CR              0x894
  98 #define RCC_PLL4CFGR1           0x898
  99 #define RCC_PLL4CFGR2           0x89C
 100 #define RCC_PLL4FRACR           0x8A0
 101 #define RCC_PLL4CSGR            0x8A4
 102 #define RCC_I2C12CKSELR         0x8C0
 103 #define RCC_I2C35CKSELR         0x8C4
 104 #define RCC_SPI2S1CKSELR        0x8D8
 105 #define RCC_SPI2S23CKSELR       0x8DC
 106 #define RCC_SPI45CKSELR         0x8E0
 107 #define RCC_UART6CKSELR         0x8E4
 108 #define RCC_UART24CKSELR        0x8E8
 109 #define RCC_UART35CKSELR        0x8EC
 110 #define RCC_UART78CKSELR        0x8F0
 111 #define RCC_SDMMC12CKSELR       0x8F4
 112 #define RCC_SDMMC3CKSELR        0x8F8
 113 #define RCC_ETHCKSELR           0x8FC
 114 #define RCC_QSPICKSELR          0x900
 115 #define RCC_FMCCKSELR           0x904
 116 #define RCC_USBCKSELR           0x91C
 117 #define RCC_DSICKSELR           0x924
 118 #define RCC_ADCCKSELR           0x928
 119 #define RCC_MP_APB1ENSETR       0xA00
 120 #define RCC_MP_APB2ENSETR       0XA08
 121 #define RCC_MP_APB3ENSETR       0xA10
 122 #define RCC_MP_AHB2ENSETR       0xA18
 123 #define RCC_MP_AHB3ENSETR       0xA20
 124 #define RCC_MP_AHB4ENSETR       0xA28
 125
 126 /* used for most of SELR register */
 127 #define RCC_SELR_SRC_MASK       GENMASK(2, 0)
 128 #define RCC_SELR_SRCRDY         BIT(31)
 129
 130 /* Values of RCC_MPCKSELR register */
 131 #define RCC_MPCKSELR_HSI        0
 132 #define RCC_MPCKSELR_HSE        1
 133 #define RCC_MPCKSELR_PLL        2
 134 #define RCC_MPCKSELR_PLL_MPUDIV 3
 135
 136 /* Values of RCC_ASSCKSELR register */
 137 #define RCC_ASSCKSELR_HSI       0
 138 #define RCC_ASSCKSELR_HSE       1
 139 #define RCC_ASSCKSELR_PLL       2
 140
 141 /* Values of RCC_MSSCKSELR register */
 142 #define RCC_MSSCKSELR_HSI       0
 143 #define RCC_MSSCKSELR_HSE       1
 144 #define RCC_MSSCKSELR_CSI       2
 145 #define RCC_MSSCKSELR_PLL       3
 146
 147 /* Values of RCC_CPERCKSELR register */
 148 #define RCC_CPERCKSELR_HSI      0
 149 #define RCC_CPERCKSELR_CSI      1
 150 #define RCC_CPERCKSELR_HSE      2
 151
 152 /* used for most of DIVR register : max div for RTC */
 153 #define RCC_DIVR_DIV_MASK       GENMASK(5, 0)
 154 #define RCC_DIVR_DIVRDY         BIT(31)
 155
 156 /* Masks for specific DIVR registers */
 157 #define RCC_APBXDIV_MASK        GENMASK(2, 0)
 158 #define RCC_MPUDIV_MASK         GENMASK(2, 0)
 159 #define RCC_AXIDIV_MASK         GENMASK(2, 0)
 160 #define RCC_MCUDIV_MASK         GENMASK(3, 0)
 161
 162 /*  offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
 163 #define RCC_MP_ENCLRR_OFFSET    4
 164
 165 /* Fields of RCC_BDCR register */
 166 #define RCC_BDCR_LSEON          BIT(0)
 167 #define RCC_BDCR_LSEBYP         BIT(1)
 168 #define RCC_BDCR_LSERDY         BIT(2)
 169 #define RCC_BDCR_DIGBYP         BIT(3)
 170 #define RCC_BDCR_LSEDRV_MASK    GENMASK(5, 4)
 171 #define RCC_BDCR_LSEDRV_SHIFT   4
 172 #define RCC_BDCR_LSECSSON       BIT(8)
 173 #define RCC_BDCR_RTCCKEN        BIT(20)
 174 #define RCC_BDCR_RTCSRC_MASK    GENMASK(17, 16)
 175 #define RCC_BDCR_RTCSRC_SHIFT   16
 176
 177 /* Fields of RCC_RDLSICR register */
 178 #define RCC_RDLSICR_LSION       BIT(0)
 179 #define RCC_RDLSICR_LSIRDY      BIT(1)
 180
 181 /* used for ALL PLLNCR registers */
 182 #define RCC_PLLNCR_PLLON        BIT(0)
 183 #define RCC_PLLNCR_PLLRDY       BIT(1)
 184 #define RCC_PLLNCR_SSCG_CTRL    BIT(2)
 185 #define RCC_PLLNCR_DIVPEN       BIT(4)
 186 #define RCC_PLLNCR_DIVQEN       BIT(5)
 187 #define RCC_PLLNCR_DIVREN       BIT(6)
 188 #define RCC_PLLNCR_DIVEN_SHIFT  4
 189
 190 /* used for ALL PLLNCFGR1 registers */
 191 #define RCC_PLLNCFGR1_DIVM_SHIFT        16
 192 #define RCC_PLLNCFGR1_DIVM_MASK         GENMASK(21, 16)
 193 #define RCC_PLLNCFGR1_DIVN_SHIFT        0
 194 #define RCC_PLLNCFGR1_DIVN_MASK         GENMASK(8, 0)
 195 /* only for PLL3 and PLL4 */
 196 #define RCC_PLLNCFGR1_IFRGE_SHIFT       24
 197 #define RCC_PLLNCFGR1_IFRGE_MASK        GENMASK(25, 24)
 198
 199 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
 200 #define RCC_PLLNCFGR2_SHIFT(div_id)     ((div_id) * 8)
 201 #define RCC_PLLNCFGR2_DIVX_MASK         GENMASK(6, 0)
 202 #define RCC_PLLNCFGR2_DIVP_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_P)
 203 #define RCC_PLLNCFGR2_DIVP_MASK         GENMASK(6, 0)
 204 #define RCC_PLLNCFGR2_DIVQ_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_Q)
 205 #define RCC_PLLNCFGR2_DIVQ_MASK         GENMASK(14, 8)
 206 #define RCC_PLLNCFGR2_DIVR_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_R)
 207 #define RCC_PLLNCFGR2_DIVR_MASK         GENMASK(22, 16)
 208
 209 /* used for ALL PLLNFRACR registers */
 210 #define RCC_PLLNFRACR_FRACV_SHIFT       3
 211 #define RCC_PLLNFRACR_FRACV_MASK        GENMASK(15, 3)
 212 #define RCC_PLLNFRACR_FRACLE            BIT(16)
 213
 214 /* used for ALL PLLNCSGR registers */
 215 #define RCC_PLLNCSGR_INC_STEP_SHIFT     16
 216 #define RCC_PLLNCSGR_INC_STEP_MASK      GENMASK(30, 16)
 217 #define RCC_PLLNCSGR_MOD_PER_SHIFT      0
 218 #define RCC_PLLNCSGR_MOD_PER_MASK       GENMASK(12, 0)
 219 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT    15
 220 #define RCC_PLLNCSGR_SSCG_MODE_MASK     BIT(15)
 221
 222 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
 223 #define RCC_OCENR_HSION                 BIT(0)
 224 #define RCC_OCENR_CSION                 BIT(4)
 225 #define RCC_OCENR_DIGBYP                BIT(7)
 226 #define RCC_OCENR_HSEON                 BIT(8)
 227 #define RCC_OCENR_HSEBYP                BIT(10)
 228 #define RCC_OCENR_HSECSSON              BIT(11)
 229
 230 /* Fields of RCC_OCRDYR register */
 231 #define RCC_OCRDYR_HSIRDY               BIT(0)
 232 #define RCC_OCRDYR_HSIDIVRDY            BIT(2)
 233 #define RCC_OCRDYR_CSIRDY               BIT(4)
 234 #define RCC_OCRDYR_HSERDY               BIT(8)
 235
 236 /* Fields of DDRITFCR register */
 237 #define RCC_DDRITFCR_DDRCKMOD_MASK      GENMASK(22, 20)
 238 #define RCC_DDRITFCR_DDRCKMOD_SHIFT     20
 239 #define RCC_DDRITFCR_DDRCKMOD_SSR       0
 240
 241 /* Fields of RCC_HSICFGR register */
 242 #define RCC_HSICFGR_HSIDIV_MASK         GENMASK(1, 0)
 243
 244 /* used for MCO related operations */
 245 #define RCC_MCOCFG_MCOON                BIT(12)
 246 #define RCC_MCOCFG_MCODIV_MASK          GENMASK(7, 4)
 247 #define RCC_MCOCFG_MCODIV_SHIFT         4
 248 #define RCC_MCOCFG_MCOSRC_MASK          GENMASK(2, 0)
 249
 250 enum stm32mp1_parent_id {
 251 /*
 252  * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
 253  * they are used as index in osc_clk[] as clock reference
 254  */
 255         _HSI,
 256         _HSE,
 257         _CSI,
 258         _LSI,
 259         _LSE,
 260         _I2S_CKIN,
 261         NB_OSC,
 262
 263 /* other parent source */
 264         _HSI_KER = NB_OSC,
 265         _HSE_KER,
 266         _HSE_KER_DIV2,
 267         _CSI_KER,
 268         _PLL1_P,
 269         _PLL1_Q,
 270         _PLL1_R,
 271         _PLL2_P,
 272         _PLL2_Q,
 273         _PLL2_R,
 274         _PLL3_P,
 275         _PLL3_Q,
 276         _PLL3_R,
 277         _PLL4_P,
 278         _PLL4_Q,
 279         _PLL4_R,
 280         _ACLK,
 281         _PCLK1,
 282         _PCLK2,
 283         _PCLK3,
 284         _PCLK4,
 285         _PCLK5,
 286         _HCLK6,
 287         _HCLK2,
 288         _CK_PER,
 289         _CK_MPU,
 290         _CK_MCU,
 291         _DSI_PHY,
 292         _USB_PHY_48,
 293         _PARENT_NB,
 294         _UNKNOWN_ID = 0xff,
 295 };
 296
 297 enum stm32mp1_parent_sel {
 298         _I2C12_SEL,
 299         _I2C35_SEL,
 300         _I2C46_SEL,
 301         _UART6_SEL,
 302         _UART24_SEL,
 303         _UART35_SEL,
 304         _UART78_SEL,
 305         _SDMMC12_SEL,
 306         _SDMMC3_SEL,
 307         _ETH_SEL,
 308         _QSPI_SEL,
 309         _FMC_SEL,
 310         _USBPHY_SEL,
 311         _USBO_SEL,
 312         _STGEN_SEL,
 313         _DSI_SEL,
 314         _ADC12_SEL,
 315         _SPI1_SEL,
 316         _SPI23_SEL,
 317         _SPI45_SEL,
 318         _SPI6_SEL,
 319         _RTC_SEL,
 320         _PARENT_SEL_NB,
 321         _UNKNOWN_SEL = 0xff,
 322 };
 323
 324 enum stm32mp1_pll_id {
 325         _PLL1,
 326         _PLL2,
 327         _PLL3,
 328         _PLL4,
 329         _PLL_NB
 330 };
 331
 332 enum stm32mp1_div_id {
 333         _DIV_P,
 334         _DIV_Q,
 335         _DIV_R,
 336         _DIV_NB,
 337 };
 338
 339 enum stm32mp1_clksrc_id {
 340         CLKSRC_MPU,
 341         CLKSRC_AXI,
 342         CLKSRC_MCU,
 343         CLKSRC_PLL12,
 344         CLKSRC_PLL3,
 345         CLKSRC_PLL4,
 346         CLKSRC_RTC,
 347         CLKSRC_MCO1,
 348         CLKSRC_MCO2,
 349         CLKSRC_NB
 350 };
 351
 352 enum stm32mp1_clkdiv_id {
 353         CLKDIV_MPU,
 354         CLKDIV_AXI,
 355         CLKDIV_MCU,
 356         CLKDIV_APB1,
 357         CLKDIV_APB2,
 358         CLKDIV_APB3,
 359         CLKDIV_APB4,
 360         CLKDIV_APB5,
 361         CLKDIV_RTC,
 362         CLKDIV_MCO1,
 363         CLKDIV_MCO2,
 364         CLKDIV_NB
 365 };
 366
 367 enum stm32mp1_pllcfg {
 368         PLLCFG_M,
 369         PLLCFG_N,
 370         PLLCFG_P,
 371         PLLCFG_Q,
 372         PLLCFG_R,
 373         PLLCFG_O,
 374         PLLCFG_NB
 375 };
 376
 377 enum stm32mp1_pllcsg {
 378         PLLCSG_MOD_PER,
 379         PLLCSG_INC_STEP,
 380         PLLCSG_SSCG_MODE,
 381         PLLCSG_NB
 382 };
 383
 384 enum stm32mp1_plltype {
 385         PLL_800,
 386         PLL_1600,
 387         PLL_TYPE_NB
 388 };
 389
 390 struct stm32mp1_pll {
 391         u8 refclk_min;
 392         u8 refclk_max;
 393         u8 divn_max;
 394 };
 395
 396 struct stm32mp1_clk_gate {
 397         u16 offset;
 398         u8 bit;
 399         u8 index;
 400         u8 set_clr;
 401         u8 sel;
 402         u8 fixed;
 403 };
 404
 405 struct stm32mp1_clk_sel {
 406         u16 offset;
 407         u8 src;
 408         u8 msk;
 409         u8 nb_parent;
 410         const u8 *parent;
 411 };
 412
 413 #define REFCLK_SIZE 4
 414 struct stm32mp1_clk_pll {
 415         enum stm32mp1_plltype plltype;
 416         u16 rckxselr;
 417         u16 pllxcfgr1;
 418         u16 pllxcfgr2;
 419         u16 pllxfracr;
 420         u16 pllxcr;
 421         u16 pllxcsgr;
 422         u8 refclk[REFCLK_SIZE];
 423 };
 424
 425 struct stm32mp1_clk_data {
 426         const struct stm32mp1_clk_gate *gate;
 427         const struct stm32mp1_clk_sel *sel;
 428         const struct stm32mp1_clk_pll *pll;
 429         const int nb_gate;
 430 };
 431
 432 struct stm32mp1_clk_priv {
 433         fdt_addr_t base;
 434         const struct stm32mp1_clk_data *data;
 435         struct clk osc_clk[NB_OSC];
 436 };
 437
 438 #define STM32MP1_CLK(off, b, idx, s)            \
 439         {                                       \
 440                 .offset = (off),                \
 441                 .bit = (b),                     \
 442                 .index = (idx),                 \
 443                 .set_clr = 0,                   \
 444                 .sel = (s),                     \
 445                 .fixed = _UNKNOWN_ID,           \
 446         }
 447
 448 #define STM32MP1_CLK_F(off, b, idx, f)          \
 449         {                                       \
 450                 .offset = (off),                \
 451                 .bit = (b),                     \
 452                 .index = (idx),                 \
 453                 .set_clr = 0,                   \
 454                 .sel = _UNKNOWN_SEL,            \
 455                 .fixed = (f),                   \
 456         }
 457
 458 #define STM32MP1_CLK_SET_CLR(off, b, idx, s)    \
 459         {                                       \
 460                 .offset = (off),                \
 461                 .bit = (b),                     \
 462                 .index = (idx),                 \
 463                 .set_clr = 1,                   \
 464                 .sel = (s),                     \
 465                 .fixed = _UNKNOWN_ID,           \
 466         }
 467
 468 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f)  \
 469         {                                       \
 470                 .offset = (off),                \
 471                 .bit = (b),                     \
 472                 .index = (idx),                 \
 473                 .set_clr = 1,                   \
 474                 .sel = _UNKNOWN_SEL,            \
 475                 .fixed = (f),                   \
 476         }
 477
 478 #define STM32MP1_CLK_PARENT(idx, off, s, m, p)   \
 479         [(idx)] = {                             \
 480                 .offset = (off),                \
 481                 .src = (s),                     \
 482                 .msk = (m),                     \
 483                 .parent = (p),                  \
 484                 .nb_parent = ARRAY_SIZE((p))    \
 485         }
 486
 487 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
 488                         p1, p2, p3, p4) \
 489         [(idx)] = {                             \
 490                 .plltype = (type),                      \
 491                 .rckxselr = (off1),             \
 492                 .pllxcfgr1 = (off2),            \
 493                 .pllxcfgr2 = (off3),            \
 494                 .pllxfracr = (off4),            \
 495                 .pllxcr = (off5),               \
 496                 .pllxcsgr = (off6),             \
 497                 .refclk[0] = (p1),              \
 498                 .refclk[1] = (p2),              \
 499                 .refclk[2] = (p3),              \
 500                 .refclk[3] = (p4),              \
 501         }
 502
 503 static const u8 stm32mp1_clks[][2] = {
 504         {CK_PER, _CK_PER},
 505         {CK_MPU, _CK_MPU},
 506         {CK_AXI, _ACLK},
 507         {CK_MCU, _CK_MCU},
 508         {CK_HSE, _HSE},
 509         {CK_CSI, _CSI},
 510         {CK_LSI, _LSI},
 511         {CK_LSE, _LSE},
 512         {CK_HSI, _HSI},
 513         {CK_HSE_DIV2, _HSE_KER_DIV2},
 514 };
 515
 516 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 517         STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
 518         STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
 519         STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
 520         STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
 521         STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
 522         STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
 523         STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
 524         STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
 525         STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
 526         STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
 527         STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
 528
 529         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 11, SPI2_K, _SPI23_SEL),
 530         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 12, SPI3_K, _SPI23_SEL),
 531         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
 532         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
 533         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
 534         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
 535         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
 536         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
 537         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
 538         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
 539         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
 540         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
 541
 542         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
 543         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 9, SPI4_K, _SPI45_SEL),
 544         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL),
 545         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 546
 547         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
 548         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_SEL),
 549
 550         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
 551         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
 552         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
 553         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
 554         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
 555         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
 556
 557         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL),
 558         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
 559         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
 560         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
 561         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 16, BSEC, _UNKNOWN_SEL),
 562         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
 563
 564         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
 565         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
 566         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
 567         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
 568
 569         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
 570         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
 571
 572         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
 573         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
 574         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
 575         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
 576         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
 577         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
 578         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
 579         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
 580         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
 581         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
 582         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 583
 584         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
 585         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _UNKNOWN_SEL),
 586
 587         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
 588         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
 589         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
 590         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
 591         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
 592         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
 593         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
 594         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
 595         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
 596
 597         STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
 598
 599         STM32MP1_CLK(RCC_BDCR, 20, RTC, _RTC_SEL),
 600 };
 601
 602 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 603 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 604 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
 605 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
 606                                         _HSE_KER};
 607 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 608                                          _HSE_KER};
 609 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 610                                          _HSE_KER};
 611 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 612                                          _HSE_KER};
 613 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
 614 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
 615 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
 616 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 617 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 618 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
 619 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
 620 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
 621 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
 622 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
 623 /* same parents for SPI1=RCC_SPI2S1CKSELR and SPI2&3 = RCC_SPI2S23CKSELR */
 624 static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
 625                                  _PLL3_R};
 626 static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
 627                                    _HSE_KER};
 628 static const u8 spi6_parents[] = {_PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER,
 629                                   _HSE_KER, _PLL3_Q};
 630 static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
 631
 632 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
 633         STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
 634         STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
 635         STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
 636         STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
 637         STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
 638                             uart24_parents),
 639         STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
 640                             uart35_parents),
 641         STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
 642                             uart78_parents),
 643         STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
 644                             sdmmc12_parents),
 645         STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
 646                             sdmmc3_parents),
 647         STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
 648         STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0x3, qspi_parents),
 649         STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0x3, fmc_parents),
 650         STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
 651         STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
 652         STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
 653         STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
 654         STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents),
 655         STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
 656         STM32MP1_CLK_PARENT(_SPI23_SEL, RCC_SPI2S23CKSELR, 0, 0x7, spi_parents),
 657         STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents),
 658         STM32MP1_CLK_PARENT(_SPI6_SEL, RCC_SPI6CKSELR, 0, 0x7, spi6_parents),
 659         STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
 660                             (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
 661                             rtc_parents),
 662 };
 663
 664 #ifdef STM32MP1_CLOCK_TREE_INIT
 665
 666 /* define characteristic of PLL according type */
 667 #define DIVM_MIN        0
 668 #define DIVM_MAX        63
 669 #define DIVN_MIN        24
 670 #define DIVP_MIN        0
 671 #define DIVP_MAX        127
 672 #define FRAC_MAX        8192
 673
 674 #define PLL1600_VCO_MIN 800000000
 675 #define PLL1600_VCO_MAX 1600000000
 676
 677 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
 678         [PLL_800] = {
 679                 .refclk_min = 4,
 680                 .refclk_max = 16,
 681                 .divn_max = 99,
 682                 },
 683         [PLL_1600] = {
 684                 .refclk_min = 8,
 685                 .refclk_max = 16,
 686                 .divn_max = 199,
 687                 },
 688 };
 689 #endif /* STM32MP1_CLOCK_TREE_INIT */
 690
 691 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
 692         STM32MP1_CLK_PLL(_PLL1, PLL_1600,
 693                          RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
 694                          RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
 695                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 696         STM32MP1_CLK_PLL(_PLL2, PLL_1600,
 697                          RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
 698                          RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
 699                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 700         STM32MP1_CLK_PLL(_PLL3, PLL_800,
 701                          RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
 702                          RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
 703                          _HSI, _HSE, _CSI, _UNKNOWN_ID),
 704         STM32MP1_CLK_PLL(_PLL4, PLL_800,
 705                          RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
 706                          RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
 707                          _HSI, _HSE, _CSI, _I2S_CKIN),
 708 };
 709
 710 /* Prescaler table lookups for clock computation */
 711 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
 712 static const u8 stm32mp1_mcu_div[16] = {
 713         0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
 714 };
 715
 716 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
 717 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
 718 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
 719 static const u8 stm32mp1_mpu_apbx_div[8] = {
 720         0, 1, 2, 3, 4, 4, 4, 4
 721 };
 722
 723 /* div = /1 /2 /3 /4 */
 724 static const u8 stm32mp1_axi_div[8] = {
 725         1, 2, 3, 4, 4, 4, 4, 4
 726 };
 727
 728 static const __maybe_unused
 729 char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
 730         [_HSI] = "HSI",
 731         [_HSE] = "HSE",
 732         [_CSI] = "CSI",
 733         [_LSI] = "LSI",
 734         [_LSE] = "LSE",
 735         [_I2S_CKIN] = "I2S_CKIN",
 736         [_HSI_KER] = "HSI_KER",
 737         [_HSE_KER] = "HSE_KER",
 738         [_HSE_KER_DIV2] = "HSE_KER_DIV2",
 739         [_CSI_KER] = "CSI_KER",
 740         [_PLL1_P] = "PLL1_P",
 741         [_PLL1_Q] = "PLL1_Q",
 742         [_PLL1_R] = "PLL1_R",
 743         [_PLL2_P] = "PLL2_P",
 744         [_PLL2_Q] = "PLL2_Q",
 745         [_PLL2_R] = "PLL2_R",
 746         [_PLL3_P] = "PLL3_P",
 747         [_PLL3_Q] = "PLL3_Q",
 748         [_PLL3_R] = "PLL3_R",
 749         [_PLL4_P] = "PLL4_P",
 750         [_PLL4_Q] = "PLL4_Q",
 751         [_PLL4_R] = "PLL4_R",
 752         [_ACLK] = "ACLK",
 753         [_PCLK1] = "PCLK1",
 754         [_PCLK2] = "PCLK2",
 755         [_PCLK3] = "PCLK3",
 756         [_PCLK4] = "PCLK4",
 757         [_PCLK5] = "PCLK5",
 758         [_HCLK6] = "KCLK6",
 759         [_HCLK2] = "HCLK2",
 760         [_CK_PER] = "CK_PER",
 761         [_CK_MPU] = "CK_MPU",
 762         [_CK_MCU] = "CK_MCU",
 763         [_USB_PHY_48] = "USB_PHY_48",
 764         [_DSI_PHY] = "DSI_PHY_PLL",
 765 };
 766
 767 static const __maybe_unused
 768 char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
 769         [_I2C12_SEL] = "I2C12",
 770         [_I2C35_SEL] = "I2C35",
 771         [_I2C46_SEL] = "I2C46",
 772         [_UART6_SEL] = "UART6",
 773         [_UART24_SEL] = "UART24",
 774         [_UART35_SEL] = "UART35",
 775         [_UART78_SEL] = "UART78",
 776         [_SDMMC12_SEL] = "SDMMC12",
 777         [_SDMMC3_SEL] = "SDMMC3",
 778         [_ETH_SEL] = "ETH",
 779         [_QSPI_SEL] = "QSPI",
 780         [_FMC_SEL] = "FMC",
 781         [_USBPHY_SEL] = "USBPHY",
 782         [_USBO_SEL] = "USBO",
 783         [_STGEN_SEL] = "STGEN",
 784         [_DSI_SEL] = "DSI",
 785         [_ADC12_SEL] = "ADC12",
 786         [_SPI1_SEL] = "SPI1",
 787         [_SPI45_SEL] = "SPI45",
 788         [_RTC_SEL] = "RTC",
 789 };
 790
 791 static const struct stm32mp1_clk_data stm32mp1_data = {
 792         .gate = stm32mp1_clk_gate,
 793         .sel = stm32mp1_clk_sel,
 794         .pll = stm32mp1_clk_pll,
 795         .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
 796 };
 797
 798 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
 799 {
 800         if (idx >= NB_OSC) {
 801                 log_debug("clk id %d not found\n", idx);
 802                 return 0;
 803         }
 804
 805         return clk_get_rate(&priv->osc_clk[idx]);
 806 }
 807
 808 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
 809 {
 810         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 811         int i, nb_clks = priv->data->nb_gate;
 812
 813         for (i = 0; i < nb_clks; i++) {
 814                 if (gate[i].index == id)
 815                         break;
 816         }
 817
 818         if (i == nb_clks) {
 819                 log_err("clk id %d not found\n", (u32)id);
 820                 return -EINVAL;
 821         }
 822
 823         return i;
 824 }
 825
 826 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
 827                                 int i)
 828 {
 829         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 830
 831         if (gate[i].sel > _PARENT_SEL_NB) {
 832                 log_err("parents for clk id %d not found\n", i);
 833                 return -EINVAL;
 834         }
 835
 836         return gate[i].sel;
 837 }
 838
 839 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
 840                                          int i)
 841 {
 842         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 843
 844         if (gate[i].fixed == _UNKNOWN_ID)
 845                 return -ENOENT;
 846
 847         return gate[i].fixed;
 848 }
 849
 850 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
 851                                    unsigned long id)
 852 {
 853         const struct stm32mp1_clk_sel *sel = priv->data->sel;
 854         int i;
 855         int s, p;
 856         unsigned int idx;
 857
 858         for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++)
 859                 if (stm32mp1_clks[idx][0] == id)
 860                         return stm32mp1_clks[idx][1];
 861
 862         i = stm32mp1_clk_get_id(priv, id);
 863         if (i < 0)
 864                 return i;
 865
 866         p = stm32mp1_clk_get_fixed_parent(priv, i);
 867         if (p >= 0 && p < _PARENT_NB)
 868                 return p;
 869
 870         s = stm32mp1_clk_get_sel(priv, i);
 871         if (s < 0)
 872                 return s;
 873
 874         p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
 875
 876         if (p < sel[s].nb_parent) {
 877                 log_content("%s clock is the parent %s of clk id %d\n",
 878                             stm32mp1_clk_parent_name[sel[s].parent[p]],
 879                             stm32mp1_clk_parent_sel_name[s],
 880                             (u32)id);
 881                 return sel[s].parent[p];
 882         }
 883
 884         log_err("no parents defined for clk id %d\n", (u32)id);
 885
 886         return -EINVAL;
 887 }
 888
 889 static ulong  pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
 890                               int pll_id)
 891 {
 892         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 893         u32 selr;
 894         int src;
 895         ulong refclk;
 896
 897         /* Get current refclk */
 898         selr = readl(priv->base + pll[pll_id].rckxselr);
 899         src = selr & RCC_SELR_SRC_MASK;
 900
 901         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
 902
 903         return refclk;
 904 }
 905
 906 /*
 907  * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
 908  * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
 909  * - PLL3 & PLL4 => return VCO     with Fpll_y_ck = FVCO / (DIVy + 1)
 910  * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
 911  */
 912 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
 913                           int pll_id)
 914 {
 915         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 916         int divm, divn;
 917         ulong refclk, fvco;
 918         u32 cfgr1, fracr;
 919
 920         cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
 921         fracr = readl(priv->base + pll[pll_id].pllxfracr);
 922
 923         divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
 924         divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
 925
 926         refclk = pll_get_fref_ck(priv, pll_id);
 927
 928         /* with FRACV :
 929          *   Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
 930          * without FRACV
 931          *   Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
 932          */
 933         if (fracr & RCC_PLLNFRACR_FRACLE) {
 934                 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
 935                             >> RCC_PLLNFRACR_FRACV_SHIFT;
 936                 fvco = (ulong)lldiv((unsigned long long)refclk *
 937                                      (((divn + 1) << 13) + fracv),
 938                                      ((unsigned long long)(divm + 1)) << 13);
 939         } else {
 940                 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
 941         }
 942
 943         return fvco;
 944 }
 945
 946 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
 947                                     int pll_id, int div_id)
 948 {
 949         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 950         int divy;
 951         ulong dfout;
 952         u32 cfgr2;
 953
 954         if (div_id >= _DIV_NB)
 955                 return 0;
 956
 957         cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
 958         divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
 959
 960         dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
 961
 962         return dfout;
 963 }
 964
 965 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
 966 {
 967         u32 reg;
 968         ulong clock = 0;
 969
 970         switch (p) {
 971         case _CK_MPU:
 972         /* MPU sub system */
 973                 reg = readl(priv->base + RCC_MPCKSELR);
 974                 switch (reg & RCC_SELR_SRC_MASK) {
 975                 case RCC_MPCKSELR_HSI:
 976                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 977                         break;
 978                 case RCC_MPCKSELR_HSE:
 979                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 980                         break;
 981                 case RCC_MPCKSELR_PLL:
 982                 case RCC_MPCKSELR_PLL_MPUDIV:
 983                         clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
 984                         if ((reg & RCC_SELR_SRC_MASK) ==
 985                             RCC_MPCKSELR_PLL_MPUDIV) {
 986                                 reg = readl(priv->base + RCC_MPCKDIVR);
 987                                 clock >>= stm32mp1_mpu_div[reg &
 988                                         RCC_MPUDIV_MASK];
 989                         }
 990                         break;
 991                 }
 992                 break;
 993         /* AXI sub system */
 994         case _ACLK:
 995         case _HCLK2:
 996         case _HCLK6:
 997         case _PCLK4:
 998         case _PCLK5:
 999                 reg = readl(priv->base + RCC_ASSCKSELR);
1000                 switch (reg & RCC_SELR_SRC_MASK) {
1001                 case RCC_ASSCKSELR_HSI:
1002                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1003                         break;
1004                 case RCC_ASSCKSELR_HSE:
1005                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1006                         break;
1007                 case RCC_ASSCKSELR_PLL:
1008                         clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
1009                         break;
1010                 }
1011
1012                 /* System clock divider */
1013                 reg = readl(priv->base + RCC_AXIDIVR);
1014                 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
1015
1016                 switch (p) {
1017                 case _PCLK4:
1018                         reg = readl(priv->base + RCC_APB4DIVR);
1019                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1020                         break;
1021                 case _PCLK5:
1022                         reg = readl(priv->base + RCC_APB5DIVR);
1023                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1024                         break;
1025                 default:
1026                         break;
1027                 }
1028                 break;
1029         /* MCU sub system */
1030         case _CK_MCU:
1031         case _PCLK1:
1032         case _PCLK2:
1033         case _PCLK3:
1034                 reg = readl(priv->base + RCC_MSSCKSELR);
1035                 switch (reg & RCC_SELR_SRC_MASK) {
1036                 case RCC_MSSCKSELR_HSI:
1037                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1038                         break;
1039                 case RCC_MSSCKSELR_HSE:
1040                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1041                         break;
1042                 case RCC_MSSCKSELR_CSI:
1043                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1044                         break;
1045                 case RCC_MSSCKSELR_PLL:
1046                         clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
1047                         break;
1048                 }
1049
1050                 /* MCU clock divider */
1051                 reg = readl(priv->base + RCC_MCUDIVR);
1052                 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1053
1054                 switch (p) {
1055                 case _PCLK1:
1056                         reg = readl(priv->base + RCC_APB1DIVR);
1057                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1058                         break;
1059                 case _PCLK2:
1060                         reg = readl(priv->base + RCC_APB2DIVR);
1061                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1062                         break;
1063                 case _PCLK3:
1064                         reg = readl(priv->base + RCC_APB3DIVR);
1065                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1066                         break;
1067                 case _CK_MCU:
1068                 default:
1069                         break;
1070                 }
1071                 break;
1072         case _CK_PER:
1073                 reg = readl(priv->base + RCC_CPERCKSELR);
1074                 switch (reg & RCC_SELR_SRC_MASK) {
1075                 case RCC_CPERCKSELR_HSI:
1076                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1077                         break;
1078                 case RCC_CPERCKSELR_HSE:
1079                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1080                         break;
1081                 case RCC_CPERCKSELR_CSI:
1082                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1083                         break;
1084                 }
1085                 break;
1086         case _HSI:
1087         case _HSI_KER:
1088                 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1089                 break;
1090         case _CSI:
1091         case _CSI_KER:
1092                 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1093                 break;
1094         case _HSE:
1095         case _HSE_KER:
1096         case _HSE_KER_DIV2:
1097                 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1098                 if (p == _HSE_KER_DIV2)
1099                         clock >>= 1;
1100                 break;
1101         case _LSI:
1102                 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1103                 break;
1104         case _LSE:
1105                 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1106                 break;
1107         /* PLL */
1108         case _PLL1_P:
1109         case _PLL1_Q:
1110         case _PLL1_R:
1111                 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1112                 break;
1113         case _PLL2_P:
1114         case _PLL2_Q:
1115         case _PLL2_R:
1116                 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1117                 break;
1118         case _PLL3_P:
1119         case _PLL3_Q:
1120         case _PLL3_R:
1121                 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1122                 break;
1123         case _PLL4_P:
1124         case _PLL4_Q:
1125         case _PLL4_R:
1126                 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1127                 break;
1128         /* other */
1129         case _USB_PHY_48:
1130                 clock = 48000000;
1131                 break;
1132         case _DSI_PHY:
1133         {
1134                 struct clk clk;
1135                 struct udevice *dev = NULL;
1136
1137                 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1138                                                &dev)) {
1139                         if (clk_request(dev, &clk)) {
1140                                 log_err("ck_dsi_phy request");
1141                         } else {
1142                                 clk.id = 0;
1143                                 clock = clk_get_rate(&clk);
1144                         }
1145                 }
1146                 break;
1147         }
1148         default:
1149                 break;
1150         }
1151
1152         log_debug("id=%d clock = %lx : %ld kHz\n", p, clock, clock / 1000);
1153
1154         return clock;
1155 }
1156
1157 static int stm32mp1_clk_enable(struct clk *clk)
1158 {
1159         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1160         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1161         int i = stm32mp1_clk_get_id(priv, clk->id);
1162
1163         if (i < 0)
1164                 return i;
1165
1166         if (gate[i].set_clr)
1167                 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1168         else
1169                 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1170
1171         dev_dbg(clk->dev, "%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1172
1173         return 0;
1174 }
1175
1176 static int stm32mp1_clk_disable(struct clk *clk)
1177 {
1178         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1179         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1180         int i = stm32mp1_clk_get_id(priv, clk->id);
1181
1182         if (i < 0)
1183                 return i;
1184
1185         if (gate[i].set_clr)
1186                 writel(BIT(gate[i].bit),
1187                        priv->base + gate[i].offset
1188                        + RCC_MP_ENCLRR_OFFSET);
1189         else
1190                 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1191
1192         dev_dbg(clk->dev, "%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1193
1194         return 0;
1195 }
1196
1197 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1198 {
1199         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1200         int p = stm32mp1_clk_get_parent(priv, clk->id);
1201         ulong rate;
1202
1203         if (p < 0)
1204                 return 0;
1205
1206         rate = stm32mp1_clk_get(priv, p);
1207
1208         dev_vdbg(clk->dev, "computed rate for id clock %d is %d (parent is %s)\n",
1209                  (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1210
1211         return rate;
1212 }
1213
1214 #ifdef STM32MP1_CLOCK_TREE_INIT
1215
1216 bool stm32mp1_supports_opp(u32 opp_id, u32 cpu_type)
1217 {
1218         unsigned int id;
1219
1220         switch (opp_id) {
1221         case 1:
1222         case 2:
1223                 id = opp_id;
1224                 break;
1225         default:
1226                 id = 1; /* default value */
1227                 break;
1228         }
1229
1230         switch (cpu_type) {
1231         case CPU_STM32MP157Fxx:
1232         case CPU_STM32MP157Dxx:
1233         case CPU_STM32MP153Fxx:
1234         case CPU_STM32MP153Dxx:
1235         case CPU_STM32MP151Fxx:
1236         case CPU_STM32MP151Dxx:
1237                 return true;
1238         default:
1239                 return id == 1;
1240         }
1241 }
1242
1243 __weak void board_vddcore_init(u32 voltage_mv)
1244 {
1245 }
1246
1247 /*
1248  * gets OPP parameters (frequency in KHz and voltage in mV) from
1249  * an OPP table subnode. Platform HW support capabilities are also checked.
1250  * Returns 0 on success and a negative FDT error code on failure.
1251  */
1252 static int stm32mp1_get_opp(u32 cpu_type, ofnode subnode,
1253                             u32 *freq_khz, u32 *voltage_mv)
1254 {
1255         u32 opp_hw;
1256         u64 read_freq_64;
1257         u32 read_voltage_32;
1258
1259         *freq_khz = 0;
1260         *voltage_mv = 0;
1261
1262         opp_hw = ofnode_read_u32_default(subnode, "opp-supported-hw", 0);
1263         if (opp_hw)
1264                 if (!stm32mp1_supports_opp(opp_hw, cpu_type))
1265                         return -FDT_ERR_BADVALUE;
1266
1267         read_freq_64 = ofnode_read_u64_default(subnode, "opp-hz", 0) /
1268                        1000ULL;
1269         read_voltage_32 = ofnode_read_u32_default(subnode, "opp-microvolt", 0) /
1270                           1000U;
1271
1272         if (!read_voltage_32 || !read_freq_64)
1273                 return -FDT_ERR_NOTFOUND;
1274
1275         /* Frequency value expressed in KHz must fit on 32 bits */
1276         if (read_freq_64 > U32_MAX)
1277                 return -FDT_ERR_BADVALUE;
1278
1279         /* Millivolt value must fit on 16 bits */
1280         if (read_voltage_32 > U16_MAX)
1281                 return -FDT_ERR_BADVALUE;
1282
1283         *freq_khz = (u32)read_freq_64;
1284         *voltage_mv = read_voltage_32;
1285
1286         return 0;
1287 }
1288
1289 /*
1290  * parses OPP table in DT and finds the parameters for the
1291  * highest frequency supported by the HW platform.
1292  * Returns 0 on success and a negative FDT error code on failure.
1293  */
1294 int stm32mp1_get_max_opp_freq(struct stm32mp1_clk_priv *priv, u64 *freq_hz)
1295 {
1296         ofnode node, subnode;
1297         int ret;
1298         u32 freq = 0U, voltage = 0U;
1299         u32 cpu_type = get_cpu_type();
1300
1301         node = ofnode_by_compatible(ofnode_null(), "operating-points-v2");
1302         if (!ofnode_valid(node))
1303                 return -FDT_ERR_NOTFOUND;
1304
1305         ofnode_for_each_subnode(subnode, node) {
1306                 unsigned int read_freq;
1307                 unsigned int read_voltage;
1308
1309                 ret = stm32mp1_get_opp(cpu_type, subnode,
1310                                        &read_freq, &read_voltage);
1311                 if (ret)
1312                         continue;
1313
1314                 if (read_freq > freq) {
1315                         freq = read_freq;
1316                         voltage = read_voltage;
1317                 }
1318         }
1319
1320         if (!freq || !voltage)
1321                 return -FDT_ERR_NOTFOUND;
1322
1323         *freq_hz = (u64)1000U * freq;
1324         board_vddcore_init(voltage);
1325
1326         return 0;
1327 }
1328
1329 static int stm32mp1_pll1_opp(struct stm32mp1_clk_priv *priv, int clksrc,
1330                              u32 *pllcfg, u32 *fracv)
1331 {
1332         u32 post_divm;
1333         u32 input_freq;
1334         u64 output_freq;
1335         u64 freq;
1336         u64 vco;
1337         u32 divm, divn, divp, frac;
1338         int i, ret;
1339         u32 diff;
1340         u32 best_diff = U32_MAX;
1341
1342         /* PLL1 is 1600 */
1343         const u32 DIVN_MAX = stm32mp1_pll[PLL_1600].divn_max;
1344         const u32 POST_DIVM_MIN = stm32mp1_pll[PLL_1600].refclk_min * 1000000U;
1345         const u32 POST_DIVM_MAX = stm32mp1_pll[PLL_1600].refclk_max * 1000000U;
1346
1347         ret = stm32mp1_get_max_opp_freq(priv, &output_freq);
1348         if (ret) {
1349                 log_debug("PLL1 OPP configuration not found (%d).\n", ret);
1350                 return ret;
1351         }
1352
1353         switch (clksrc) {
1354         case CLK_PLL12_HSI:
1355                 input_freq = stm32mp1_clk_get_fixed(priv, _HSI);
1356                 break;
1357         case CLK_PLL12_HSE:
1358                 input_freq = stm32mp1_clk_get_fixed(priv, _HSE);
1359                 break;
1360         default:
1361                 return -EINTR;
1362         }
1363
1364         /* Following parameters have always the same value */
1365         pllcfg[PLLCFG_Q] = 0;
1366         pllcfg[PLLCFG_R] = 0;
1367         pllcfg[PLLCFG_O] = PQR(1, 0, 0);
1368
1369         for (divm = DIVM_MAX; divm >= DIVM_MIN; divm--) {
1370                 post_divm = (u32)(input_freq / (divm + 1));
1371                 if (post_divm < POST_DIVM_MIN || post_divm > POST_DIVM_MAX)
1372                         continue;
1373
1374                 for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) {
1375                         freq = output_freq * (divm + 1) * (divp + 1);
1376                         divn = (u32)((freq / input_freq) - 1);
1377                         if (divn < DIVN_MIN || divn > DIVN_MAX)
1378                                 continue;
1379
1380                         frac = (u32)(((freq * FRAC_MAX) / input_freq) -
1381                                      ((divn + 1) * FRAC_MAX));
1382                         /* 2 loops to refine the fractional part */
1383                         for (i = 2; i != 0; i--) {
1384                                 if (frac > FRAC_MAX)
1385                                         break;
1386
1387                                 vco = (post_divm * (divn + 1)) +
1388                                       ((post_divm * (u64)frac) /
1389                                        FRAC_MAX);
1390                                 if (vco < (PLL1600_VCO_MIN / 2) ||
1391                                     vco > (PLL1600_VCO_MAX / 2)) {
1392                                         frac++;
1393                                         continue;
1394                                 }
1395                                 freq = vco / (divp + 1);
1396                                 if (output_freq < freq)
1397                                         diff = (u32)(freq - output_freq);
1398                                 else
1399                                         diff = (u32)(output_freq - freq);
1400                                 if (diff < best_diff)  {
1401                                         pllcfg[PLLCFG_M] = divm;
1402                                         pllcfg[PLLCFG_N] = divn;
1403                                         pllcfg[PLLCFG_P] = divp;
1404                                         *fracv = frac;
1405
1406                                         if (diff == 0)
1407                                                 return 0;
1408
1409                                         best_diff = diff;
1410                                 }
1411                                 frac++;
1412                         }
1413                 }
1414         }
1415
1416         if (best_diff == U32_MAX)
1417                 return -1;
1418
1419         return 0;
1420 }
1421
1422 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1423                                 u32 mask_on)
1424 {
1425         u32 address = rcc + offset;
1426
1427         if (enable)
1428                 setbits_le32(address, mask_on);
1429         else
1430                 clrbits_le32(address, mask_on);
1431 }
1432
1433 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1434 {
1435         writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
1436 }
1437
1438 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1439                              u32 mask_rdy)
1440 {
1441         u32 mask_test = 0;
1442         u32 address = rcc + offset;
1443         u32 val;
1444         int ret;
1445
1446         if (enable)
1447                 mask_test = mask_rdy;
1448
1449         ret = readl_poll_timeout(address, val,
1450                                  (val & mask_rdy) == mask_test,
1451                                  TIMEOUT_1S);
1452
1453         if (ret)
1454                 log_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1455                         mask_rdy, address, enable, readl(address));
1456
1457         return ret;
1458 }
1459
1460 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
1461                                 u32 lsedrv)
1462 {
1463         u32 value;
1464
1465         if (digbyp)
1466                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
1467
1468         if (bypass || digbyp)
1469                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1470
1471         /*
1472          * warning: not recommended to switch directly from "high drive"
1473          * to "medium low drive", and vice-versa.
1474          */
1475         value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1476                 >> RCC_BDCR_LSEDRV_SHIFT;
1477
1478         while (value != lsedrv) {
1479                 if (value > lsedrv)
1480                         value--;
1481                 else
1482                         value++;
1483
1484                 clrsetbits_le32(rcc + RCC_BDCR,
1485                                 RCC_BDCR_LSEDRV_MASK,
1486                                 value << RCC_BDCR_LSEDRV_SHIFT);
1487         }
1488
1489         stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1490 }
1491
1492 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1493 {
1494         stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1495 }
1496
1497 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1498 {
1499         stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1500         stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1501 }
1502
1503 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
1504 {
1505         if (digbyp)
1506                 writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
1507         if (bypass || digbyp)
1508                 writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
1509
1510         stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1511         stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1512
1513         if (css)
1514                 writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
1515 }
1516
1517 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1518 {
1519         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
1520         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1521 }
1522
1523 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1524 {
1525         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1526         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1527 }
1528
1529 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1530 {
1531         u32 address = rcc + RCC_OCRDYR;
1532         u32 val;
1533         int ret;
1534
1535         clrsetbits_le32(rcc + RCC_HSICFGR,
1536                         RCC_HSICFGR_HSIDIV_MASK,
1537                         RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1538
1539         ret = readl_poll_timeout(address, val,
1540                                  val & RCC_OCRDYR_HSIDIVRDY,
1541                                  TIMEOUT_200MS);
1542         if (ret)
1543                 log_err("HSIDIV failed @ 0x%x: 0x%x\n",
1544                         address, readl(address));
1545
1546         return ret;
1547 }
1548
1549 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1550 {
1551         u8 hsidiv;
1552         u32 hsidivfreq = MAX_HSI_HZ;
1553
1554         for (hsidiv = 0; hsidiv < 4; hsidiv++,
1555              hsidivfreq = hsidivfreq / 2)
1556                 if (hsidivfreq == hsifreq)
1557                         break;
1558
1559         if (hsidiv == 4) {
1560                 log_err("hsi frequency invalid");
1561                 return -1;
1562         }
1563
1564         if (hsidiv > 0)
1565                 return stm32mp1_set_hsidiv(rcc, hsidiv);
1566
1567         return 0;
1568 }
1569
1570 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1571 {
1572         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1573
1574         clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
1575                         RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1576                         RCC_PLLNCR_DIVREN,
1577                         RCC_PLLNCR_PLLON);
1578 }
1579
1580 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1581 {
1582         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1583         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1584         u32 val;
1585         int ret;
1586
1587         ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1588                                  TIMEOUT_200MS);
1589
1590         if (ret) {
1591                 log_err("PLL%d start failed @ 0x%x: 0x%x\n",
1592                         pll_id, pllxcr, readl(pllxcr));
1593                 return ret;
1594         }
1595
1596         /* start the requested output */
1597         setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1598
1599         return 0;
1600 }
1601
1602 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1603 {
1604         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1605         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1606         u32 val;
1607
1608         /* stop all output */
1609         clrbits_le32(pllxcr,
1610                      RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1611
1612         /* stop PLL */
1613         clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1614
1615         /* wait PLL stopped */
1616         return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1617                                   TIMEOUT_200MS);
1618 }
1619
1620 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1621                               int pll_id, u32 *pllcfg)
1622 {
1623         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1624         fdt_addr_t rcc = priv->base;
1625         u32 value;
1626
1627         value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1628                 & RCC_PLLNCFGR2_DIVP_MASK;
1629         value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1630                  & RCC_PLLNCFGR2_DIVQ_MASK;
1631         value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1632                  & RCC_PLLNCFGR2_DIVR_MASK;
1633         writel(value, rcc + pll[pll_id].pllxcfgr2);
1634 }
1635
1636 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1637                       u32 *pllcfg, u32 fracv)
1638 {
1639         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1640         fdt_addr_t rcc = priv->base;
1641         enum stm32mp1_plltype type = pll[pll_id].plltype;
1642         int src;
1643         ulong refclk;
1644         u8 ifrge = 0;
1645         u32 value;
1646
1647         src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1648
1649         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1650                  (pllcfg[PLLCFG_M] + 1);
1651
1652         if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1653             refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1654                 log_err("invalid refclk = %x\n", (u32)refclk);
1655                 return -EINVAL;
1656         }
1657         if (type == PLL_800 && refclk >= 8000000)
1658                 ifrge = 1;
1659
1660         value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1661                  & RCC_PLLNCFGR1_DIVN_MASK;
1662         value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1663                  & RCC_PLLNCFGR1_DIVM_MASK;
1664         value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1665                  & RCC_PLLNCFGR1_IFRGE_MASK;
1666         writel(value, rcc + pll[pll_id].pllxcfgr1);
1667
1668         /* fractional configuration: load sigma-delta modulator (SDM) */
1669
1670         /* Write into FRACV the new fractional value , and FRACLE to 0 */
1671         writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1672                rcc + pll[pll_id].pllxfracr);
1673
1674         /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1675         setbits_le32(rcc + pll[pll_id].pllxfracr,
1676                      RCC_PLLNFRACR_FRACLE);
1677
1678         pll_config_output(priv, pll_id, pllcfg);
1679
1680         return 0;
1681 }
1682
1683 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1684 {
1685         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1686         u32 pllxcsg;
1687
1688         pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1689                     RCC_PLLNCSGR_MOD_PER_MASK) |
1690                   ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1691                     RCC_PLLNCSGR_INC_STEP_MASK) |
1692                   ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1693                     RCC_PLLNCSGR_SSCG_MODE_MASK);
1694
1695         writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1696
1697         setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
1698 }
1699
1700 static  __maybe_unused int pll_set_rate(struct udevice *dev,
1701                                         int pll_id,
1702                                         int div_id,
1703                                         unsigned long clk_rate)
1704 {
1705         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1706         unsigned int pllcfg[PLLCFG_NB];
1707         ofnode plloff;
1708         char name[12];
1709         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1710         enum stm32mp1_plltype type = pll[pll_id].plltype;
1711         int divm, divn, divy;
1712         int ret;
1713         ulong fck_ref;
1714         u32 fracv;
1715         u64 value;
1716
1717         if (div_id > _DIV_NB)
1718                 return -EINVAL;
1719
1720         sprintf(name, "st,pll@%d", pll_id);
1721         plloff = dev_read_subnode(dev, name);
1722         if (!ofnode_valid(plloff))
1723                 return -FDT_ERR_NOTFOUND;
1724
1725         ret = ofnode_read_u32_array(plloff, "cfg",
1726                                     pllcfg, PLLCFG_NB);
1727         if (ret < 0)
1728                 return -FDT_ERR_NOTFOUND;
1729
1730         fck_ref = pll_get_fref_ck(priv, pll_id);
1731
1732         divm = pllcfg[PLLCFG_M];
1733         /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
1734         divy = pllcfg[PLLCFG_P + div_id];
1735
1736         /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
1737          * So same final result than PLL2 et 4
1738          * with FRACV
1739          * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
1740          *             / (DIVy + 1) * (DIVM + 1)
1741          * value = (DIVN + 1) * 2^13 + FRACV / 2^13
1742          *       = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
1743          */
1744         value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
1745         value = lldiv(value, fck_ref);
1746
1747         divn = (value >> 13) - 1;
1748         if (divn < DIVN_MIN ||
1749             divn > stm32mp1_pll[type].divn_max) {
1750                 dev_err(dev, "divn invalid = %d", divn);
1751                 return -EINVAL;
1752         }
1753         fracv = value - ((divn + 1) << 13);
1754         pllcfg[PLLCFG_N] = divn;
1755
1756         /* reconfigure PLL */
1757         pll_stop(priv, pll_id);
1758         pll_config(priv, pll_id, pllcfg, fracv);
1759         pll_start(priv, pll_id);
1760         pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
1761
1762         return 0;
1763 }
1764
1765 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1766 {
1767         u32 address = priv->base + (clksrc >> 4);
1768         u32 val;
1769         int ret;
1770
1771         clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1772         ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1773                                  TIMEOUT_200MS);
1774         if (ret)
1775                 log_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1776                         clksrc, address, readl(address));
1777
1778         return ret;
1779 }
1780
1781 static void stgen_config(struct stm32mp1_clk_priv *priv)
1782 {
1783         int p;
1784         u32 stgenc, cntfid0;
1785         ulong rate;
1786
1787         stgenc = STM32_STGEN_BASE;
1788         cntfid0 = readl(stgenc + STGENC_CNTFID0);
1789         p = stm32mp1_clk_get_parent(priv, STGEN_K);
1790         rate = stm32mp1_clk_get(priv, p);
1791
1792         if (cntfid0 != rate) {
1793                 u64 counter;
1794
1795                 log_debug("System Generic Counter (STGEN) update\n");
1796                 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1797                 counter = (u64)readl(stgenc + STGENC_CNTCVL);
1798                 counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
1799                 counter = lldiv(counter * (u64)rate, cntfid0);
1800                 writel((u32)counter, stgenc + STGENC_CNTCVL);
1801                 writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
1802                 writel(rate, stgenc + STGENC_CNTFID0);
1803                 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1804
1805                 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1806
1807                 /* need to update gd->arch.timer_rate_hz with new frequency */
1808                 timer_init();
1809         }
1810 }
1811
1812 static int set_clkdiv(unsigned int clkdiv, u32 address)
1813 {
1814         u32 val;
1815         int ret;
1816
1817         clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1818         ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1819                                  TIMEOUT_200MS);
1820         if (ret)
1821                 log_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1822                         clkdiv, address, readl(address));
1823
1824         return ret;
1825 }
1826
1827 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1828                              u32 clksrc, u32 clkdiv)
1829 {
1830         u32 address = priv->base + (clksrc >> 4);
1831
1832         /*
1833          * binding clksrc : bit15-4 offset
1834          *                  bit3:   disable
1835          *                  bit2-0: MCOSEL[2:0]
1836          */
1837         if (clksrc & 0x8) {
1838                 clrbits_le32(address, RCC_MCOCFG_MCOON);
1839         } else {
1840                 clrsetbits_le32(address,
1841                                 RCC_MCOCFG_MCOSRC_MASK,
1842                                 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1843                 clrsetbits_le32(address,
1844                                 RCC_MCOCFG_MCODIV_MASK,
1845                                 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1846                 setbits_le32(address, RCC_MCOCFG_MCOON);
1847         }
1848 }
1849
1850 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1851                        unsigned int clksrc,
1852                        int lse_css)
1853 {
1854         u32 address = priv->base + RCC_BDCR;
1855
1856         if (readl(address) & RCC_BDCR_RTCCKEN)
1857                 goto skip_rtc;
1858
1859         if (clksrc == CLK_RTC_DISABLED)
1860                 goto skip_rtc;
1861
1862         clrsetbits_le32(address,
1863                         RCC_BDCR_RTCSRC_MASK,
1864                         clksrc << RCC_BDCR_RTCSRC_SHIFT);
1865
1866         setbits_le32(address, RCC_BDCR_RTCCKEN);
1867
1868 skip_rtc:
1869         if (lse_css)
1870                 setbits_le32(address, RCC_BDCR_LSECSSON);
1871 }
1872
1873 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1874 {
1875         u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1876         u32 value = pkcs & 0xF;
1877         u32 mask = 0xF;
1878
1879         if (pkcs & BIT(31)) {
1880                 mask <<= 4;
1881                 value <<= 4;
1882         }
1883         clrsetbits_le32(address, mask, value);
1884 }
1885
1886 static int stm32mp1_clktree(struct udevice *dev)
1887 {
1888         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1889         fdt_addr_t rcc = priv->base;
1890         unsigned int clksrc[CLKSRC_NB];
1891         unsigned int clkdiv[CLKDIV_NB];
1892         unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1893         unsigned int pllfracv[_PLL_NB];
1894         unsigned int pllcsg[_PLL_NB][PLLCSG_NB];
1895         bool pllcfg_valid[_PLL_NB];
1896         bool pllcsg_set[_PLL_NB];
1897         int ret;
1898         int i, len;
1899         int lse_css = 0;
1900         const u32 *pkcs_cell;
1901
1902         /* check mandatory field */
1903         ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1904         if (ret < 0) {
1905                 dev_dbg(dev, "field st,clksrc invalid: error %d\n", ret);
1906                 return -FDT_ERR_NOTFOUND;
1907         }
1908
1909         ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1910         if (ret < 0) {
1911                 dev_dbg(dev, "field st,clkdiv invalid: error %d\n", ret);
1912                 return -FDT_ERR_NOTFOUND;
1913         }
1914
1915         /* check mandatory field in each pll */
1916         for (i = 0; i < _PLL_NB; i++) {
1917                 char name[12];
1918                 ofnode node;
1919
1920                 sprintf(name, "st,pll@%d", i);
1921                 node = dev_read_subnode(dev, name);
1922                 pllcfg_valid[i] = ofnode_valid(node);
1923                 pllcsg_set[i] = false;
1924                 if (pllcfg_valid[i]) {
1925                         dev_dbg(dev, "DT for PLL %d @ %s\n", i, name);
1926                         ret = ofnode_read_u32_array(node, "cfg",
1927                                                     pllcfg[i], PLLCFG_NB);
1928                         if (ret < 0) {
1929                                 dev_dbg(dev, "field cfg invalid: error %d\n", ret);
1930                                 return -FDT_ERR_NOTFOUND;
1931                         }
1932                         pllfracv[i] = ofnode_read_u32_default(node, "frac", 0);
1933
1934                         ret = ofnode_read_u32_array(node, "csg", pllcsg[i],
1935                                                     PLLCSG_NB);
1936                         if (!ret) {
1937                                 pllcsg_set[i] = true;
1938                         } else if (ret != -FDT_ERR_NOTFOUND) {
1939                                 dev_dbg(dev, "invalid csg node for pll@%d res=%d\n",
1940                                         i, ret);
1941                                 return ret;
1942                         }
1943                 } else if (i == _PLL1)  {
1944                         /* use OPP for PLL1 for A7 CPU */
1945                         dev_dbg(dev, "DT for PLL %d with OPP\n", i);
1946                         ret = stm32mp1_pll1_opp(priv,
1947                                                 clksrc[CLKSRC_PLL12],
1948                                                 pllcfg[i],
1949                                                 &pllfracv[i]);
1950                         if (ret) {
1951                                 dev_dbg(dev, "PLL %d with OPP error = %d\n", i, ret);
1952                                 return ret;
1953                         }
1954                         pllcfg_valid[i] = true;
1955                 }
1956         }
1957
1958         dev_dbg(dev, "configuration MCO\n");
1959         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1960         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1961
1962         dev_dbg(dev, "switch ON osillator\n");
1963         /*
1964          * switch ON oscillator found in device-tree,
1965          * HSI already ON after bootrom
1966          */
1967         if (clk_valid(&priv->osc_clk[_LSI]))
1968                 stm32mp1_lsi_set(rcc, 1);
1969
1970         if (clk_valid(&priv->osc_clk[_LSE])) {
1971                 int bypass, digbyp;
1972                 u32 lsedrv;
1973                 struct udevice *dev = priv->osc_clk[_LSE].dev;
1974
1975                 bypass = dev_read_bool(dev, "st,bypass");
1976                 digbyp = dev_read_bool(dev, "st,digbypass");
1977                 lse_css = dev_read_bool(dev, "st,css");
1978                 lsedrv = dev_read_u32_default(dev, "st,drive",
1979                                               LSEDRV_MEDIUM_HIGH);
1980
1981                 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
1982         }
1983
1984         if (clk_valid(&priv->osc_clk[_HSE])) {
1985                 int bypass, digbyp, css;
1986                 struct udevice *dev = priv->osc_clk[_HSE].dev;
1987
1988                 bypass = dev_read_bool(dev, "st,bypass");
1989                 digbyp = dev_read_bool(dev, "st,digbypass");
1990                 css = dev_read_bool(dev, "st,css");
1991
1992                 stm32mp1_hse_enable(rcc, bypass, digbyp, css);
1993         }
1994         /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1995          * => switch on CSI even if node is not present in device tree
1996          */
1997         stm32mp1_csi_set(rcc, 1);
1998
1999         /* come back to HSI */
2000         dev_dbg(dev, "come back to HSI\n");
2001         set_clksrc(priv, CLK_MPU_HSI);
2002         set_clksrc(priv, CLK_AXI_HSI);
2003         set_clksrc(priv, CLK_MCU_HSI);
2004
2005         dev_dbg(dev, "pll stop\n");
2006         for (i = 0; i < _PLL_NB; i++)
2007                 pll_stop(priv, i);
2008
2009         /* configure HSIDIV */
2010         dev_dbg(dev, "configure HSIDIV\n");
2011         if (clk_valid(&priv->osc_clk[_HSI])) {
2012                 stm32mp1_hsidiv(rcc, clk_get_rate(&priv->osc_clk[_HSI]));
2013                 stgen_config(priv);
2014         }
2015
2016         /* select DIV */
2017         dev_dbg(dev, "select DIV\n");
2018         /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
2019         writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
2020         set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
2021         set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
2022         set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
2023         set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
2024         set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
2025         set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
2026         set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
2027
2028         /* no ready bit for RTC */
2029         writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
2030
2031         /* configure PLLs source */
2032         dev_dbg(dev, "configure PLLs source\n");
2033         set_clksrc(priv, clksrc[CLKSRC_PLL12]);
2034         set_clksrc(priv, clksrc[CLKSRC_PLL3]);
2035         set_clksrc(priv, clksrc[CLKSRC_PLL4]);
2036
2037         /* configure and start PLLs */
2038         dev_dbg(dev, "configure PLLs\n");
2039         for (i = 0; i < _PLL_NB; i++) {
2040                 if (!pllcfg_valid[i])
2041                         continue;
2042                 dev_dbg(dev, "configure PLL %d\n", i);
2043                 pll_config(priv, i, pllcfg[i], pllfracv[i]);
2044                 if (pllcsg_set[i])
2045                         pll_csg(priv, i, pllcsg[i]);
2046                 pll_start(priv, i);
2047         }
2048
2049         /* wait and start PLLs ouptut when ready */
2050         for (i = 0; i < _PLL_NB; i++) {
2051                 if (!pllcfg_valid[i])
2052                         continue;
2053                 dev_dbg(dev, "output PLL %d\n", i);
2054                 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
2055         }
2056
2057         /* wait LSE ready before to use it */
2058         if (clk_valid(&priv->osc_clk[_LSE]))
2059                 stm32mp1_lse_wait(rcc);
2060
2061         /* configure with expected clock source */
2062         dev_dbg(dev, "CLKSRC\n");
2063         set_clksrc(priv, clksrc[CLKSRC_MPU]);
2064         set_clksrc(priv, clksrc[CLKSRC_AXI]);
2065         set_clksrc(priv, clksrc[CLKSRC_MCU]);
2066         set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
2067
2068         /* configure PKCK */
2069         dev_dbg(dev, "PKCK\n");
2070         pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
2071         if (pkcs_cell) {
2072                 bool ckper_disabled = false;
2073
2074                 for (i = 0; i < len / sizeof(u32); i++) {
2075                         u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
2076
2077                         if (pkcs == CLK_CKPER_DISABLED) {
2078                                 ckper_disabled = true;
2079                                 continue;
2080                         }
2081                         pkcs_config(priv, pkcs);
2082                 }
2083                 /* CKPER is source for some peripheral clock
2084                  * (FMC-NAND / QPSI-NOR) and switching source is allowed
2085                  * only if previous clock is still ON
2086                  * => deactivated CKPER only after switching clock
2087                  */
2088                 if (ckper_disabled)
2089                         pkcs_config(priv, CLK_CKPER_DISABLED);
2090         }
2091
2092         /* STGEN clock source can change with CLK_STGEN_XXX */
2093         stgen_config(priv);
2094
2095         dev_dbg(dev, "oscillator off\n");
2096         /* switch OFF HSI if not found in device-tree */
2097         if (!clk_valid(&priv->osc_clk[_HSI]))
2098                 stm32mp1_hsi_set(rcc, 0);
2099
2100         /* Software Self-Refresh mode (SSR) during DDR initilialization */
2101         clrsetbits_le32(priv->base + RCC_DDRITFCR,
2102                         RCC_DDRITFCR_DDRCKMOD_MASK,
2103                         RCC_DDRITFCR_DDRCKMOD_SSR <<
2104                         RCC_DDRITFCR_DDRCKMOD_SHIFT);
2105
2106         return 0;
2107 }
2108 #endif /* STM32MP1_CLOCK_TREE_INIT */
2109
2110 static int pll_set_output_rate(struct udevice *dev,
2111                                int pll_id,
2112                                int div_id,
2113                                unsigned long clk_rate)
2114 {
2115         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2116         const struct stm32mp1_clk_pll *pll = priv->data->pll;
2117         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
2118         int div;
2119         ulong fvco;
2120
2121         if (div_id > _DIV_NB)
2122                 return -EINVAL;
2123
2124         fvco = pll_get_fvco(priv, pll_id);
2125
2126         if (fvco <= clk_rate)
2127                 div = 1;
2128         else
2129                 div = DIV_ROUND_UP(fvco, clk_rate);
2130
2131         if (div > 128)
2132                 div = 128;
2133
2134         /* stop the requested output */
2135         clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
2136         /* change divider */
2137         clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
2138                         RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
2139                         (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
2140         /* start the requested output */
2141         setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
2142
2143         return 0;
2144 }
2145
2146 static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
2147 {
2148         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
2149         int p;
2150
2151         switch (clk->id) {
2152 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
2153         defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
2154         case DDRPHYC:
2155                 break;
2156 #endif
2157         case LTDC_PX:
2158         case DSI_PX:
2159                 break;
2160         default:
2161                 dev_err(clk->dev, "Set of clk %ld not supported", clk->id);
2162                 return -EINVAL;
2163         }
2164
2165         p = stm32mp1_clk_get_parent(priv, clk->id);
2166         dev_vdbg(clk->dev, "parent = %d:%s\n", p, stm32mp1_clk_parent_name[p]);
2167         if (p < 0)
2168                 return -EINVAL;
2169
2170         switch (p) {
2171 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
2172         defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
2173         case _PLL2_R: /* DDRPHYC */
2174         {
2175                 /* only for change DDR clock in interactive mode */
2176                 ulong result;
2177
2178                 set_clksrc(priv, CLK_AXI_HSI);
2179                 result = pll_set_rate(clk->dev,  _PLL2, _DIV_R, clk_rate);
2180                 set_clksrc(priv, CLK_AXI_PLL2P);
2181                 return result;
2182         }
2183 #endif
2184
2185         case _PLL4_Q:
2186                 /* for LTDC_PX and DSI_PX case */
2187                 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
2188         }
2189
2190         return -EINVAL;
2191 }
2192
2193 static void stm32mp1_osc_init(struct udevice *dev)
2194 {
2195         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2196         int i;
2197         const char *name[NB_OSC] = {
2198                 [_LSI] = "lsi",
2199                 [_LSE] = "lse",
2200                 [_HSI] = "hsi",
2201                 [_HSE] = "hse",
2202                 [_CSI] = "csi",
2203                 [_I2S_CKIN] = "i2s_ckin",
2204         };
2205
2206         for (i = 0; i < NB_OSC; i++) {
2207                 if (clk_get_by_name(dev, name[i], &priv->osc_clk[i]))
2208                         dev_dbg(dev, "No source clock \"%s\"\n", name[i]);
2209                 else
2210                         dev_dbg(dev, "%s clock rate: %luHz\n",
2211                                 name[i], clk_get_rate(&priv->osc_clk[i]));
2212         }
2213 }
2214
2215 static void  __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
2216 {
2217         char buf[32];
2218         int i, s, p;
2219
2220         printf("Clocks:\n");
2221         for (i = 0; i < _PARENT_NB; i++) {
2222                 printf("- %s : %s MHz\n",
2223                        stm32mp1_clk_parent_name[i],
2224                        strmhz(buf, stm32mp1_clk_get(priv, i)));
2225         }
2226         printf("Source Clocks:\n");
2227         for (i = 0; i < _PARENT_SEL_NB; i++) {
2228                 p = (readl(priv->base + priv->data->sel[i].offset) >>
2229                      priv->data->sel[i].src) & priv->data->sel[i].msk;
2230                 if (p < priv->data->sel[i].nb_parent) {
2231                         s = priv->data->sel[i].parent[p];
2232                         printf("- %s(%d) => parent %s(%d)\n",
2233                                stm32mp1_clk_parent_sel_name[i], i,
2234                                stm32mp1_clk_parent_name[s], s);
2235                 } else {
2236                         printf("- %s(%d) => parent index %d is invalid\n",
2237                                stm32mp1_clk_parent_sel_name[i], i, p);
2238                 }
2239         }
2240 }
2241
2242 #ifdef CONFIG_CMD_CLK
2243 int soc_clk_dump(void)
2244 {
2245         struct udevice *dev;
2246         struct stm32mp1_clk_priv *priv;
2247         int ret;
2248
2249         ret = uclass_get_device_by_driver(UCLASS_CLK,
2250                                           DM_DRIVER_GET(stm32mp1_clock),
2251                                           &dev);
2252         if (ret)
2253                 return ret;
2254
2255         priv = dev_get_priv(dev);
2256
2257         stm32mp1_clk_dump(priv);
2258
2259         return 0;
2260 }
2261 #endif
2262
2263 static int stm32mp1_clk_probe(struct udevice *dev)
2264 {
2265         int result = 0;
2266         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2267
2268         priv->base = dev_read_addr(dev->parent);
2269         if (priv->base == FDT_ADDR_T_NONE)
2270                 return -EINVAL;
2271
2272         priv->data = (void *)&stm32mp1_data;
2273
2274         if (!priv->data->gate || !priv->data->sel ||
2275             !priv->data->pll)
2276                 return -EINVAL;
2277
2278         stm32mp1_osc_init(dev);
2279
2280 #ifdef STM32MP1_CLOCK_TREE_INIT
2281         /* clock tree init is done only one time, before relocation */
2282         if (!(gd->flags & GD_FLG_RELOC))
2283                 result = stm32mp1_clktree(dev);
2284         if (result)
2285                 dev_err(dev, "clock tree initialization failed (%d)\n", result);
2286 #endif
2287
2288 #ifndef CONFIG_SPL_BUILD
2289 #if defined(VERBOSE_DEBUG)
2290         /* display debug information for probe after relocation */
2291         if (gd->flags & GD_FLG_RELOC)
2292                 stm32mp1_clk_dump(priv);
2293 #endif
2294
2295         gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU);
2296         gd->bus_clk = stm32mp1_clk_get(priv, _ACLK);
2297         /* DDRPHYC father */
2298         gd->mem_clk = stm32mp1_clk_get(priv, _PLL2_R);
2299 #if defined(CONFIG_DISPLAY_CPUINFO)
2300         if (gd->flags & GD_FLG_RELOC) {
2301                 char buf[32];
2302
2303                 log_info("Clocks:\n");
2304                 log_info("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
2305                 log_info("- MCU : %s MHz\n",
2306                          strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
2307                 log_info("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
2308                 log_info("- PER : %s MHz\n",
2309                          strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
2310                 log_info("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
2311         }
2312 #endif /* CONFIG_DISPLAY_CPUINFO */
2313 #endif
2314
2315         return result;
2316 }
2317
2318 static const struct clk_ops stm32mp1_clk_ops = {
2319         .enable = stm32mp1_clk_enable,
2320         .disable = stm32mp1_clk_disable,
2321         .get_rate = stm32mp1_clk_get_rate,
2322         .set_rate = stm32mp1_clk_set_rate,
2323 };
2324
2325 U_BOOT_DRIVER(stm32mp1_clock) = {
2326         .name = "stm32mp1_clk",
2327         .id = UCLASS_CLK,
2328         .ops = &stm32mp1_clk_ops,
2329         .priv_auto      = sizeof(struct stm32mp1_clk_priv),
2330         .probe = stm32mp1_clk_probe,
2331 };