drivers/clk/clk_stm32h7.c

   1 /*
   2  * Copyright (C) STMicroelectronics SA 2017
   3  * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk-uclass.h>
  10 #include <dm.h>
  11 #include <regmap.h>
  12 #include <syscon.h>
  13 #include <asm/io.h>
  14 #include <dm/root.h>
  15
  16 #include <dt-bindings/clock/stm32h7-clks.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 /* RCC CR specific definitions */
  21 #define RCC_CR_HSION                    BIT(0)
  22 #define RCC_CR_HSIRDY                   BIT(2)
  23
  24 #define RCC_CR_HSEON                    BIT(16)
  25 #define RCC_CR_HSERDY                   BIT(17)
  26 #define RCC_CR_HSEBYP                   BIT(18)
  27 #define RCC_CR_PLL1ON                   BIT(24)
  28 #define RCC_CR_PLL1RDY                  BIT(25)
  29
  30 #define RCC_CR_HSIDIV_MASK              GENMASK(4, 3)
  31 #define RCC_CR_HSIDIV_SHIFT             3
  32
  33 #define RCC_CFGR_SW_MASK                GENMASK(2, 0)
  34 #define RCC_CFGR_SW_HSI                 0
  35 #define RCC_CFGR_SW_CSI                 1
  36 #define RCC_CFGR_SW_HSE                 2
  37 #define RCC_CFGR_SW_PLL1                3
  38
  39 #define RCC_PLLCKSELR_PLLSRC_HSI        0
  40 #define RCC_PLLCKSELR_PLLSRC_CSI        1
  41 #define RCC_PLLCKSELR_PLLSRC_HSE        2
  42 #define RCC_PLLCKSELR_PLLSRC_NO_CLK     3
  43
  44 #define RCC_PLLCKSELR_PLLSRC_MASK       GENMASK(1, 0)
  45
  46 #define RCC_PLLCKSELR_DIVM1_SHIFT       4
  47 #define RCC_PLLCKSELR_DIVM1_MASK        GENMASK(9, 4)
  48
  49 #define RCC_PLL1DIVR_DIVN1_MASK         GENMASK(8, 0)
  50
  51 #define RCC_PLL1DIVR_DIVP1_SHIFT        9
  52 #define RCC_PLL1DIVR_DIVP1_MASK         GENMASK(15, 9)
  53
  54 #define RCC_PLL1DIVR_DIVQ1_SHIFT        16
  55 #define RCC_PLL1DIVR_DIVQ1_MASK         GENMASK(22, 16)
  56
  57 #define RCC_PLL1DIVR_DIVR1_SHIFT        24
  58 #define RCC_PLL1DIVR_DIVR1_MASK         GENMASK(30, 24)
  59
  60 #define RCC_PLL1FRACR_FRACN1_SHIFT      3
  61 #define RCC_PLL1FRACR_FRACN1_MASK       GENMASK(15, 3)
  62
  63 #define RCC_PLLCFGR_PLL1RGE_SHIFT       2
  64 #define         PLL1RGE_1_2_MHZ         0
  65 #define         PLL1RGE_2_4_MHZ         1
  66 #define         PLL1RGE_4_8_MHZ         2
  67 #define         PLL1RGE_8_16_MHZ        3
  68 #define RCC_PLLCFGR_DIVP1EN             BIT(16)
  69 #define RCC_PLLCFGR_DIVQ1EN             BIT(17)
  70 #define RCC_PLLCFGR_DIVR1EN             BIT(18)
  71
  72 #define RCC_D1CFGR_HPRE_MASK            GENMASK(3, 0)
  73 #define RCC_D1CFGR_HPRE_DIVIDED         BIT(3)
  74 #define RCC_D1CFGR_HPRE_DIVIDER         GENMASK(2, 0)
  75
  76 #define RCC_D1CFGR_HPRE_DIV2            8
  77
  78 #define RCC_D1CFGR_D1PPRE_SHIFT         4
  79 #define RCC_D1CFGR_D1PPRE_DIVIDED       BIT(6)
  80 #define RCC_D1CFGR_D1PPRE_DIVIDER       GENMASK(5, 4)
  81
  82 #define RCC_D1CFGR_D1CPRE_SHIFT         8
  83 #define RCC_D1CFGR_D1CPRE_DIVIDER       GENMASK(10, 8)
  84 #define RCC_D1CFGR_D1CPRE_DIVIDED       BIT(11)
  85
  86 #define RCC_D2CFGR_D2PPRE1_SHIFT        4
  87 #define RCC_D2CFGR_D2PPRE1_DIVIDED      BIT(6)
  88 #define RCC_D2CFGR_D2PPRE1_DIVIDER      GENMASK(5, 4)
  89
  90 #define RCC_D2CFGR_D2PPRE2_SHIFT        8
  91 #define RCC_D2CFGR_D2PPRE2_DIVIDED      BIT(10)
  92 #define RCC_D2CFGR_D2PPRE2_DIVIDER      GENMASK(9, 8)
  93
  94 #define RCC_D3CFGR_D3PPRE_SHIFT         4
  95 #define RCC_D3CFGR_D3PPRE_DIVIDED       BIT(6)
  96 #define RCC_D3CFGR_D3PPRE_DIVIDER       GENMASK(5, 4)
  97
  98 #define RCC_D1CCIPR_FMCSRC_MASK         GENMASK(1, 0)
  99 #define         FMCSRC_HCLKD1           0
 100 #define         FMCSRC_PLL1_Q_CK        1
 101 #define         FMCSRC_PLL2_R_CK        2
 102 #define         FMCSRC_PER_CK           3
 103
 104 #define RCC_D1CCIPR_QSPISRC_MASK        GENMASK(5, 4)
 105 #define RCC_D1CCIPR_QSPISRC_SHIFT       4
 106 #define         QSPISRC_HCLKD1          0
 107 #define         QSPISRC_PLL1_Q_CK       1
 108 #define         QSPISRC_PLL2_R_CK       2
 109 #define         QSPISRC_PER_CK          3
 110
 111 #define PWR_CR3                         0x0c
 112 #define PWR_CR3_SDEN                    BIT(2)
 113 #define PWR_D3CR                        0x18
 114 #define PWR_D3CR_VOS_MASK               GENMASK(15, 14)
 115 #define PWR_D3CR_VOS_SHIFT              14
 116 #define         VOS_SCALE_3             1
 117 #define         VOS_SCALE_2             2
 118 #define         VOS_SCALE_1             3
 119 #define PWR_D3CR_VOSREADY               BIT(13)
 120
 121 struct stm32_rcc_regs {
 122         u32 cr;         /* 0x00 Source Control Register */
 123         u32 icscr;      /* 0x04 Internal Clock Source Calibration Register */
 124         u32 crrcr;      /* 0x08 Clock Recovery RC Register */
 125         u32 reserved1;  /* 0x0c reserved */
 126         u32 cfgr;       /* 0x10 Clock Configuration Register */
 127         u32 reserved2;  /* 0x14 reserved */
 128         u32 d1cfgr;     /* 0x18 Domain 1 Clock Configuration Register */
 129         u32 d2cfgr;     /* 0x1c Domain 2 Clock Configuration Register */
 130         u32 d3cfgr;     /* 0x20 Domain 3 Clock Configuration Register */
 131         u32 reserved3;  /* 0x24 reserved */
 132         u32 pllckselr;  /* 0x28 PLLs Clock Source Selection Register */
 133         u32 pllcfgr;    /* 0x2c PLLs Configuration Register */
 134         u32 pll1divr;   /* 0x30 PLL1 Dividers Configuration Register */
 135         u32 pll1fracr;  /* 0x34 PLL1 Fractional Divider Register */
 136         u32 pll2divr;   /* 0x38 PLL2 Dividers Configuration Register */
 137         u32 pll2fracr;  /* 0x3c PLL2 Fractional Divider Register */
 138         u32 pll3divr;   /* 0x40 PLL3 Dividers Configuration Register */
 139         u32 pll3fracr;  /* 0x44 PLL3 Fractional Divider Register */
 140         u32 reserved4;  /* 0x48 reserved */
 141         u32 d1ccipr;    /* 0x4c Domain 1 Kernel Clock Configuration Register */
 142         u32 d2ccip1r;   /* 0x50 Domain 2 Kernel Clock Configuration Register */
 143         u32 d2ccip2r;   /* 0x54 Domain 2 Kernel Clock Configuration Register */
 144         u32 d3ccipr;    /* 0x58 Domain 3 Kernel Clock Configuration Register */
 145         u32 reserved5;  /* 0x5c reserved */
 146         u32 cier;       /* 0x60 Clock Source Interrupt Enable Register */
 147         u32 cifr;       /* 0x64 Clock Source Interrupt Flag Register */
 148         u32 cicr;       /* 0x68 Clock Source Interrupt Clear Register */
 149         u32 reserved6;  /* 0x6c reserved */
 150         u32 bdcr;       /* 0x70 Backup Domain Control Register */
 151         u32 csr;        /* 0x74 Clock Control and Status Register */
 152         u32 reserved7;  /* 0x78 reserved */
 153
 154         u32 ahb3rstr;   /* 0x7c AHB3 Peripheral Reset Register */
 155         u32 ahb1rstr;   /* 0x80 AHB1 Peripheral Reset Register */
 156         u32 ahb2rstr;   /* 0x84 AHB2 Peripheral Reset Register */
 157         u32 ahb4rstr;   /* 0x88 AHB4 Peripheral Reset Register */
 158
 159         u32 apb3rstr;   /* 0x8c APB3 Peripheral Reset Register */
 160         u32 apb1lrstr;  /* 0x90 APB1 low Peripheral Reset Register */
 161         u32 apb1hrstr;  /* 0x94 APB1 high Peripheral Reset Register */
 162         u32 apb2rstr;   /* 0x98 APB2 Clock Register */
 163         u32 apb4rstr;   /* 0x9c APB4 Clock Register */
 164
 165         u32 gcr;        /* 0xa0 Global Control Register */
 166         u32 reserved8;  /* 0xa4 reserved */
 167         u32 d3amr;      /* 0xa8 D3 Autonomous mode Register */
 168         u32 reserved9[9];/* 0xac to 0xcc reserved */
 169         u32 rsr;        /* 0xd0 Reset Status Register */
 170         u32 ahb3enr;    /* 0xd4 AHB3 Clock Register */
 171         u32 ahb1enr;    /* 0xd8 AHB1 Clock Register */
 172         u32 ahb2enr;    /* 0xdc AHB2 Clock Register */
 173         u32 ahb4enr;    /* 0xe0 AHB4 Clock Register */
 174
 175         u32 apb3enr;    /* 0xe4 APB3 Clock Register */
 176         u32 apb1lenr;   /* 0xe8 APB1 low Clock Register */
 177         u32 apb1henr;   /* 0xec APB1 high Clock Register */
 178         u32 apb2enr;    /* 0xf0 APB2 Clock Register */
 179         u32 apb4enr;    /* 0xf4 APB4 Clock Register */
 180 };
 181
 182 #define RCC_AHB3ENR     offsetof(struct stm32_rcc_regs, ahb3enr)
 183 #define RCC_AHB1ENR     offsetof(struct stm32_rcc_regs, ahb1enr)
 184 #define RCC_AHB2ENR     offsetof(struct stm32_rcc_regs, ahb2enr)
 185 #define RCC_AHB4ENR     offsetof(struct stm32_rcc_regs, ahb4enr)
 186 #define RCC_APB3ENR     offsetof(struct stm32_rcc_regs, apb3enr)
 187 #define RCC_APB1LENR    offsetof(struct stm32_rcc_regs, apb1lenr)
 188 #define RCC_APB1HENR    offsetof(struct stm32_rcc_regs, apb1henr)
 189 #define RCC_APB2ENR     offsetof(struct stm32_rcc_regs, apb2enr)
 190 #define RCC_APB4ENR     offsetof(struct stm32_rcc_regs, apb4enr)
 191
 192 struct clk_cfg {
 193         u32 gate_offset;
 194         u8  gate_bit_idx;
 195         const char *name;
 196 };
 197
 198 #define CLK(_gate_offset, _bit_idx, _name) \
 199 { \
 200         .gate_offset = _gate_offset,\
 201         .gate_bit_idx = _bit_idx,\
 202         .name = _name,\
 203 }
 204
 205 /*
 206  * the way all these entries are sorted in this array could seem
 207  * unlogical, but we are dependant of kernel DT_bindings,
 208  * where clocks are separate in 2 banks, peripheral clocks and
 209  * kernel clocks.
 210  */
 211
 212 static const struct clk_cfg clk_map[] = {
 213         CLK(RCC_AHB3ENR,  31, "d1sram1"),       /* peripheral clocks */
 214         CLK(RCC_AHB3ENR,  30, "itcm"),
 215         CLK(RCC_AHB3ENR,  29, "dtcm2"),
 216         CLK(RCC_AHB3ENR,  28, "dtcm1"),
 217         CLK(RCC_AHB3ENR,   8, "flitf"),
 218         CLK(RCC_AHB3ENR,   5, "jpgdec"),
 219         CLK(RCC_AHB3ENR,   4, "dma2d"),
 220         CLK(RCC_AHB3ENR,   0, "mdma"),
 221         CLK(RCC_AHB1ENR,  28, "usb2ulpi"),
 222         CLK(RCC_AHB1ENR,  17, "eth1rx"),
 223         CLK(RCC_AHB1ENR,  16, "eth1tx"),
 224         CLK(RCC_AHB1ENR,  15, "eth1mac"),
 225         CLK(RCC_AHB1ENR,  14, "art"),
 226         CLK(RCC_AHB1ENR,  26, "usb1ulpi"),
 227         CLK(RCC_AHB1ENR,   1, "dma2"),
 228         CLK(RCC_AHB1ENR,   0, "dma1"),
 229         CLK(RCC_AHB2ENR,  31, "d2sram3"),
 230         CLK(RCC_AHB2ENR,  30, "d2sram2"),
 231         CLK(RCC_AHB2ENR,  29, "d2sram1"),
 232         CLK(RCC_AHB2ENR,   5, "hash"),
 233         CLK(RCC_AHB2ENR,   4, "crypt"),
 234         CLK(RCC_AHB2ENR,   0, "camitf"),
 235         CLK(RCC_AHB4ENR,  28, "bkpram"),
 236         CLK(RCC_AHB4ENR,  25, "hsem"),
 237         CLK(RCC_AHB4ENR,  21, "bdma"),
 238         CLK(RCC_AHB4ENR,  19, "crc"),
 239         CLK(RCC_AHB4ENR,  10, "gpiok"),
 240         CLK(RCC_AHB4ENR,   9, "gpioj"),
 241         CLK(RCC_AHB4ENR,   8, "gpioi"),
 242         CLK(RCC_AHB4ENR,   7, "gpioh"),
 243         CLK(RCC_AHB4ENR,   6, "gpiog"),
 244         CLK(RCC_AHB4ENR,   5, "gpiof"),
 245         CLK(RCC_AHB4ENR,   4, "gpioe"),
 246         CLK(RCC_AHB4ENR,   3, "gpiod"),
 247         CLK(RCC_AHB4ENR,   2, "gpioc"),
 248         CLK(RCC_AHB4ENR,   1, "gpiob"),
 249         CLK(RCC_AHB4ENR,   0, "gpioa"),
 250         CLK(RCC_APB3ENR,   6, "wwdg1"),
 251         CLK(RCC_APB1LENR, 29, "dac12"),
 252         CLK(RCC_APB1LENR, 11, "wwdg2"),
 253         CLK(RCC_APB1LENR,  8, "tim14"),
 254         CLK(RCC_APB1LENR,  7, "tim13"),
 255         CLK(RCC_APB1LENR,  6, "tim12"),
 256         CLK(RCC_APB1LENR,  5, "tim7"),
 257         CLK(RCC_APB1LENR,  4, "tim6"),
 258         CLK(RCC_APB1LENR,  3, "tim5"),
 259         CLK(RCC_APB1LENR,  2, "tim4"),
 260         CLK(RCC_APB1LENR,  1, "tim3"),
 261         CLK(RCC_APB1LENR,  0, "tim2"),
 262         CLK(RCC_APB1HENR,  5, "mdios"),
 263         CLK(RCC_APB1HENR,  4, "opamp"),
 264         CLK(RCC_APB1HENR,  1, "crs"),
 265         CLK(RCC_APB2ENR,  18, "tim17"),
 266         CLK(RCC_APB2ENR,  17, "tim16"),
 267         CLK(RCC_APB2ENR,  16, "tim15"),
 268         CLK(RCC_APB2ENR,   1, "tim8"),
 269         CLK(RCC_APB2ENR,   0, "tim1"),
 270         CLK(RCC_APB4ENR,  26, "tmpsens"),
 271         CLK(RCC_APB4ENR,  16, "rtcapb"),
 272         CLK(RCC_APB4ENR,  15, "vref"),
 273         CLK(RCC_APB4ENR,  14, "comp12"),
 274         CLK(RCC_APB4ENR,   1, "syscfg"),
 275         CLK(RCC_AHB3ENR,  16, "sdmmc1"),        /* kernel clocks */
 276         CLK(RCC_AHB3ENR,  14, "quadspi"),
 277         CLK(RCC_AHB3ENR,  12, "fmc"),
 278         CLK(RCC_AHB1ENR,  27, "usb2otg"),
 279         CLK(RCC_AHB1ENR,  25, "usb1otg"),
 280         CLK(RCC_AHB1ENR,   5, "adc12"),
 281         CLK(RCC_AHB2ENR,   9, "sdmmc2"),
 282         CLK(RCC_AHB2ENR,   6, "rng"),
 283         CLK(RCC_AHB4ENR,  24, "adc3"),
 284         CLK(RCC_APB3ENR,   4, "dsi"),
 285         CLK(RCC_APB3ENR,   3, "ltdc"),
 286         CLK(RCC_APB1LENR, 31, "usart8"),
 287         CLK(RCC_APB1LENR, 30, "usart7"),
 288         CLK(RCC_APB1LENR, 27, "hdmicec"),
 289         CLK(RCC_APB1LENR, 23, "i2c3"),
 290         CLK(RCC_APB1LENR, 22, "i2c2"),
 291         CLK(RCC_APB1LENR, 21, "i2c1"),
 292         CLK(RCC_APB1LENR, 20, "uart5"),
 293         CLK(RCC_APB1LENR, 19, "uart4"),
 294         CLK(RCC_APB1LENR, 18, "usart3"),
 295         CLK(RCC_APB1LENR, 17, "usart2"),
 296         CLK(RCC_APB1LENR, 16, "spdifrx"),
 297         CLK(RCC_APB1LENR, 15, "spi3"),
 298         CLK(RCC_APB1LENR, 14, "spi2"),
 299         CLK(RCC_APB1LENR,  9, "lptim1"),
 300         CLK(RCC_APB1HENR,  8, "fdcan"),
 301         CLK(RCC_APB1HENR,  2, "swp"),
 302         CLK(RCC_APB2ENR,  29, "hrtim"),
 303         CLK(RCC_APB2ENR,  28, "dfsdm1"),
 304         CLK(RCC_APB2ENR,  24, "sai3"),
 305         CLK(RCC_APB2ENR,  23, "sai2"),
 306         CLK(RCC_APB2ENR,  22, "sai1"),
 307         CLK(RCC_APB2ENR,  20, "spi5"),
 308         CLK(RCC_APB2ENR,  13, "spi4"),
 309         CLK(RCC_APB2ENR,  12, "spi1"),
 310         CLK(RCC_APB2ENR,   5, "usart6"),
 311         CLK(RCC_APB2ENR,   4, "usart1"),
 312         CLK(RCC_APB4ENR,  21, "sai4a"),
 313         CLK(RCC_APB4ENR,  21, "sai4b"),
 314         CLK(RCC_APB4ENR,  12, "lptim5"),
 315         CLK(RCC_APB4ENR,  11, "lptim4"),
 316         CLK(RCC_APB4ENR,  10, "lptim3"),
 317         CLK(RCC_APB4ENR,   9, "lptim2"),
 318         CLK(RCC_APB4ENR,   7, "i2c4"),
 319         CLK(RCC_APB4ENR,   5,  "spi6"),
 320         CLK(RCC_APB4ENR,   3, "lpuart1"),
 321 };
 322
 323 struct stm32_clk {
 324         struct stm32_rcc_regs *rcc_base;
 325         struct regmap *pwr_regmap;
 326 };
 327
 328 struct pll_psc {
 329         u8      divm;
 330         u16     divn;
 331         u8      divp;
 332         u8      divq;
 333         u8      divr;
 334 };
 335
 336 /*
 337  * OSC_HSE = 25 MHz
 338  * VCO = 500MHz
 339  * pll1_p = 250MHz / pll1_q = 250MHz pll1_r = 250Mhz
 340  */
 341 struct pll_psc sys_pll_psc = {
 342         .divm = 4,
 343         .divn = 80,
 344         .divp = 2,
 345         .divq = 2,
 346         .divr = 2,
 347 };
 348
 349 int configure_clocks(struct udevice *dev)
 350 {
 351         struct stm32_clk *priv = dev_get_priv(dev);
 352         struct stm32_rcc_regs *regs = priv->rcc_base;
 353         uint8_t *pwr_base = (uint8_t *)regmap_get_range(priv->pwr_regmap, 0);
 354         uint32_t pllckselr = 0;
 355         uint32_t pll1divr = 0;
 356         uint32_t pllcfgr = 0;
 357
 358         /* Switch on HSI */
 359         setbits_le32(&regs->cr, RCC_CR_HSION);
 360         while (!(readl(&regs->cr) & RCC_CR_HSIRDY))
 361                 ;
 362
 363         /* Reset CFGR, now HSI is the default system clock */
 364         writel(0, &regs->cfgr);
 365
 366         /* Set all kernel domain clock registers to reset value*/
 367         writel(0x0, &regs->d1ccipr);
 368         writel(0x0, &regs->d2ccip1r);
 369         writel(0x0, &regs->d2ccip2r);
 370
 371         /* Set voltage scaling at scale 1 */
 372         clrsetbits_le32(pwr_base + PWR_D3CR, PWR_D3CR_VOS_MASK,
 373                         VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT);
 374         /* disable step down converter */
 375         clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SDEN);
 376         while (!(readl(pwr_base + PWR_D3CR) & PWR_D3CR_VOSREADY))
 377                 ;
 378
 379         /* disable HSE to configure it  */
 380         clrbits_le32(&regs->cr, RCC_CR_HSEON);
 381         while ((readl(&regs->cr) & RCC_CR_HSERDY))
 382                 ;
 383
 384         /* clear HSE bypass and set it ON */
 385         clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
 386         /* Switch on HSE */
 387         setbits_le32(&regs->cr, RCC_CR_HSEON);
 388         while (!(readl(&regs->cr) & RCC_CR_HSERDY))
 389                 ;
 390
 391         /* pll setup, disable it */
 392         clrbits_le32(&regs->cr, RCC_CR_PLL1ON);
 393         while ((readl(&regs->cr) & RCC_CR_PLL1RDY))
 394                 ;
 395
 396         /* Select HSE as PLL clock source */
 397         pllckselr |= RCC_PLLCKSELR_PLLSRC_HSE;
 398         pllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT;
 399         writel(pllckselr, &regs->pllckselr);
 400
 401         pll1divr |= (sys_pll_psc.divr - 1) << RCC_PLL1DIVR_DIVR1_SHIFT;
 402         pll1divr |= (sys_pll_psc.divq - 1) << RCC_PLL1DIVR_DIVQ1_SHIFT;
 403         pll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT;
 404         pll1divr |= (sys_pll_psc.divn - 1);
 405         writel(pll1divr, &regs->pll1divr);
 406
 407         pllcfgr |= PLL1RGE_4_8_MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT;
 408         pllcfgr |= RCC_PLLCFGR_DIVP1EN;
 409         pllcfgr |= RCC_PLLCFGR_DIVQ1EN;
 410         pllcfgr |= RCC_PLLCFGR_DIVR1EN;
 411         writel(pllcfgr, &regs->pllcfgr);
 412
 413         /* pll setup, enable it */
 414         setbits_le32(&regs->cr, RCC_CR_PLL1ON);
 415
 416         /* set HPRE (/2) DI clk --> 125MHz */
 417         clrsetbits_le32(&regs->d1cfgr, RCC_D1CFGR_HPRE_MASK,
 418                         RCC_D1CFGR_HPRE_DIV2);
 419
 420         /*  select PLL1 as system clock source (sys_ck)*/
 421         clrsetbits_le32(&regs->cfgr, RCC_CFGR_SW_MASK, RCC_CFGR_SW_PLL1);
 422         while ((readl(&regs->cfgr) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL1)
 423                 ;
 424
 425         /* sdram: use pll1_q as fmc_k clk */
 426         clrsetbits_le32(&regs->d1ccipr, RCC_D1CCIPR_FMCSRC_MASK,
 427                         FMCSRC_PLL1_Q_CK);
 428
 429         return 0;
 430 }
 431
 432 static u32 stm32_get_HSI_divider(struct stm32_rcc_regs *regs)
 433 {
 434         u32 divider;
 435
 436         /* get HSI divider value */
 437         divider = readl(&regs->cr) & RCC_CR_HSIDIV_MASK;
 438         divider = divider >> RCC_CR_HSIDIV_SHIFT;
 439
 440         return divider;
 441 };
 442
 443 enum pllsrc {
 444         HSE,
 445         LSE,
 446         HSI,
 447         CSI,
 448         I2S,
 449         TIMER,
 450         PLLSRC_NB,
 451 };
 452
 453 static const char * const pllsrc_name[PLLSRC_NB] = {
 454         [HSE] = "clk-hse",
 455         [LSE] = "clk-lse",
 456         [HSI] = "clk-hsi",
 457         [CSI] = "clk-csi",
 458         [I2S] = "clk-i2s",
 459         [TIMER] = "timer-clk"
 460 };
 461
 462 static ulong stm32_get_rate(struct stm32_rcc_regs *regs, enum pllsrc pllsrc)
 463 {
 464         struct clk clk;
 465         struct udevice *fixed_clock_dev = NULL;
 466         u32 divider;
 467         int ret;
 468         const char *name = pllsrc_name[pllsrc];
 469
 470         debug("%s name %s\n", __func__, name);
 471
 472         clk.id = 0;
 473         ret = uclass_get_device_by_name(UCLASS_CLK, name, &fixed_clock_dev);
 474         if (ret) {
 475                 error("Can't find clk %s (%d)", name, ret);
 476                 return 0;
 477         }
 478
 479         ret = clk_request(fixed_clock_dev, &clk);
 480         if (ret) {
 481                 error("Can't request %s clk (%d)", name, ret);
 482                 return 0;
 483         }
 484
 485         divider = 0;
 486         if (pllsrc == HSI)
 487                 divider = stm32_get_HSI_divider(regs);
 488
 489         debug("%s divider %d rate %ld\n", __func__,
 490               divider, clk_get_rate(&clk));
 491
 492         return clk_get_rate(&clk) >> divider;
 493 };
 494
 495 enum pll1_output {
 496         PLL1_P_CK,
 497         PLL1_Q_CK,
 498         PLL1_R_CK,
 499 };
 500
 501 static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs,
 502                                enum pll1_output output)
 503 {
 504         ulong pllsrc = 0;
 505         u32 divm1, divn1, divp1, divq1, divr1, fracn1;
 506         ulong vco, rate;
 507
 508         /* get the PLLSRC */
 509         switch (readl(&regs->pllckselr) & RCC_PLLCKSELR_PLLSRC_MASK) {
 510         case RCC_PLLCKSELR_PLLSRC_HSI:
 511                 pllsrc = stm32_get_rate(regs, HSI);
 512                 break;
 513         case RCC_PLLCKSELR_PLLSRC_CSI:
 514                 pllsrc = stm32_get_rate(regs, CSI);
 515                 break;
 516         case RCC_PLLCKSELR_PLLSRC_HSE:
 517                 pllsrc = stm32_get_rate(regs, HSE);
 518                 break;
 519         case RCC_PLLCKSELR_PLLSRC_NO_CLK:
 520                 /* shouldn't happen */
 521                 error("wrong value for RCC_PLLCKSELR register\n");
 522                 pllsrc = 0;
 523                 break;
 524         }
 525
 526         /* pllsrc = 0 ? no need to go ahead */
 527         if (!pllsrc)
 528                 return pllsrc;
 529
 530         /* get divm1, divp1, divn1 and divr1 */
 531         divm1 = readl(&regs->pllckselr) & RCC_PLLCKSELR_DIVM1_MASK;
 532         divm1 = divm1 >> RCC_PLLCKSELR_DIVM1_SHIFT;
 533
 534         divn1 = (readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVN1_MASK) + 1;
 535
 536         divp1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVP1_MASK;
 537         divp1 = (divp1 >> RCC_PLL1DIVR_DIVP1_SHIFT) + 1;
 538
 539         divq1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVQ1_MASK;
 540         divq1 = (divq1 >> RCC_PLL1DIVR_DIVQ1_SHIFT) + 1;
 541
 542         divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK;
 543         divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1;
 544
 545         fracn1 = readl(&regs->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK;
 546         fracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT;
 547
 548         vco = (pllsrc / divm1) * divn1;
 549         rate = (pllsrc * fracn1) / (divm1 * 8192);
 550
 551         debug("%s divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\n",
 552               __func__, divm1, divn1, divp1, divq1, divr1);
 553         debug("%s fracn1 = %d vco = %ld rate = %ld\n",
 554               __func__, fracn1, vco, rate);
 555
 556         switch (output) {
 557         case PLL1_P_CK:
 558                 return (vco + rate) / divp1;
 559                 break;
 560         case PLL1_Q_CK:
 561                 return (vco + rate) / divq1;
 562                 break;
 563
 564         case PLL1_R_CK:
 565                 return (vco + rate) / divr1;
 566                 break;
 567         }
 568
 569         return -EINVAL;
 570 }
 571
 572 static ulong stm32_clk_get_rate(struct clk *clk)
 573 {
 574         struct stm32_clk *priv = dev_get_priv(clk->dev);
 575         struct stm32_rcc_regs *regs = priv->rcc_base;
 576         ulong sysclk = 0;
 577         u32 gate_offset;
 578         u32 d1cfgr;
 579         /* prescaler table lookups for clock computation */
 580         u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
 581         u8 source, idx;
 582
 583         /*
 584          * get system clock (sys_ck) source
 585          * can be HSI_CK, CSI_CK, HSE_CK or pll1_p_ck
 586          */
 587         source = readl(&regs->cfgr) & RCC_CFGR_SW_MASK;
 588         switch (source) {
 589         case RCC_CFGR_SW_PLL1:
 590                 sysclk = stm32_get_PLL1_rate(regs, PLL1_P_CK);
 591                 break;
 592         case RCC_CFGR_SW_HSE:
 593                 sysclk = stm32_get_rate(regs, HSE);
 594                 break;
 595
 596         case RCC_CFGR_SW_CSI:
 597                 sysclk = stm32_get_rate(regs, CSI);
 598                 break;
 599
 600         case RCC_CFGR_SW_HSI:
 601                 sysclk = stm32_get_rate(regs, HSI);
 602                 break;
 603         }
 604
 605         /* sysclk = 0 ? no need to go ahead */
 606         if (!sysclk)
 607                 return sysclk;
 608
 609         debug("%s system clock: source = %d freq = %ld\n",
 610               __func__, source, sysclk);
 611
 612         d1cfgr = readl(&regs->d1cfgr);
 613
 614         if (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDED) {
 615                 /* get D1 domain Core prescaler */
 616                 idx = (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDER) >>
 617                       RCC_D1CFGR_D1CPRE_SHIFT;
 618                 sysclk = sysclk / prescaler_table[idx];
 619         }
 620
 621         if (d1cfgr & RCC_D1CFGR_HPRE_DIVIDED) {
 622                 /* get D1 domain AHB prescaler */
 623                 idx = d1cfgr & RCC_D1CFGR_HPRE_DIVIDER;
 624                 sysclk = sysclk / prescaler_table[idx];
 625         }
 626
 627         gate_offset = clk_map[clk->id].gate_offset;
 628
 629         debug("%s clk->id=%ld gate_offset=0x%x sysclk=%ld\n",
 630               __func__, clk->id, gate_offset, sysclk);
 631
 632         switch (gate_offset) {
 633         case RCC_AHB3ENR:
 634         case RCC_AHB1ENR:
 635         case RCC_AHB2ENR:
 636         case RCC_AHB4ENR:
 637                 return sysclk;
 638                 break;
 639
 640         case RCC_APB3ENR:
 641                 if (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDED) {
 642                         /* get D1 domain APB3 prescaler */
 643                         idx = (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDER) >>
 644                               RCC_D1CFGR_D1PPRE_SHIFT;
 645                         sysclk = sysclk / prescaler_table[idx];
 646                 }
 647
 648                 debug("%s system clock: freq after APB3 prescaler = %ld\n",
 649                       __func__, sysclk);
 650
 651                 return sysclk;
 652                 break;
 653
 654         case RCC_APB4ENR:
 655                 if (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
 656                         /* get D3 domain APB4 prescaler */
 657                         idx = (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
 658                               RCC_D3CFGR_D3PPRE_SHIFT;
 659                         sysclk = sysclk / prescaler_table[idx];
 660                 }
 661
 662                 debug("%s system clock: freq after APB4 prescaler = %ld\n",
 663                       __func__, sysclk);
 664
 665                 return sysclk;
 666                 break;
 667
 668         case RCC_APB1LENR:
 669         case RCC_APB1HENR:
 670                 if (d1cfgr & RCC_D2CFGR_D2PPRE1_DIVIDED) {
 671                         /* get D2 domain APB1 prescaler */
 672                         idx = (d1cfgr & RCC_D2CFGR_D2PPRE1_DIVIDER) >>
 673                               RCC_D2CFGR_D2PPRE1_SHIFT;
 674                         sysclk = sysclk / prescaler_table[idx];
 675                 }
 676
 677                 debug("%s system clock: freq after APB1 prescaler = %ld\n",
 678                       __func__, sysclk);
 679
 680                 return sysclk;
 681                 break;
 682
 683         case RCC_APB2ENR:
 684                 if (d1cfgr & RCC_D2CFGR_D2PPRE2_DIVIDED) {
 685                         /* get D2 domain APB1 prescaler */
 686                         idx = (d1cfgr & RCC_D2CFGR_D2PPRE2_DIVIDER) >>
 687                               RCC_D2CFGR_D2PPRE2_SHIFT;
 688                         sysclk = sysclk / prescaler_table[idx];
 689                 }
 690
 691                 debug("%s system clock: freq after APB2 prescaler = %ld\n",
 692                       __func__, sysclk);
 693
 694                 return sysclk;
 695                 break;
 696
 697         default:
 698                 error("unexpected gate_offset value (0x%x)\n", gate_offset);
 699                 return -EINVAL;
 700                 break;
 701         }
 702 }
 703
 704 static int stm32_clk_enable(struct clk *clk)
 705 {
 706         struct stm32_clk *priv = dev_get_priv(clk->dev);
 707         struct stm32_rcc_regs *regs = priv->rcc_base;
 708         u32 gate_offset;
 709         u32 gate_bit_index;
 710         unsigned long clk_id = clk->id;
 711
 712         gate_offset = clk_map[clk_id].gate_offset;
 713         gate_bit_index = clk_map[clk_id].gate_bit_idx;
 714
 715         debug("%s: clkid=%ld gate offset=0x%x bit_index=%d name=%s\n",
 716               __func__, clk->id, gate_offset, gate_bit_index,
 717               clk_map[clk_id].name);
 718
 719         setbits_le32(&regs->cr + (gate_offset / 4), BIT(gate_bit_index));
 720
 721         return 0;
 722 }
 723
 724 static int stm32_clk_probe(struct udevice *dev)
 725 {
 726         struct stm32_clk *priv = dev_get_priv(dev);
 727         struct udevice *syscon;
 728         fdt_addr_t addr;
 729         int err;
 730
 731         addr = dev_read_addr(dev);
 732         if (addr == FDT_ADDR_T_NONE)
 733                 return -EINVAL;
 734
 735         priv->rcc_base = (struct stm32_rcc_regs *)addr;
 736
 737         /* get corresponding syscon phandle */
 738         err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
 739                                            "st,syscfg", &syscon);
 740
 741         if (err) {
 742                 error("unable to find syscon device\n");
 743                 return err;
 744         }
 745
 746         priv->pwr_regmap = syscon_get_regmap(syscon);
 747         if (!priv->pwr_regmap) {
 748                 error("unable to find regmap\n");
 749                 return -ENODEV;
 750         }
 751
 752         configure_clocks(dev);
 753
 754         return 0;
 755 }
 756
 757 static int stm32_clk_of_xlate(struct clk *clk,
 758                         struct ofnode_phandle_args *args)
 759 {
 760         if (args->args_count != 1) {
 761                 debug("Invaild args_count: %d\n", args->args_count);
 762                 return -EINVAL;
 763         }
 764
 765         if (args->args_count) {
 766                 clk->id = args->args[0];
 767                 /*
 768                  * this computation convert DT clock index which is used to
 769                  * point into 2 separate clock arrays (peripheral and kernel
 770                  * clocks bank) (see include/dt-bindings/clock/stm32h7-clks.h)
 771                  * into index to point into only one array where peripheral
 772                  * and kernel clocks are consecutive
 773                  */
 774                 if (clk->id >= KERN_BANK) {
 775                         clk->id -= KERN_BANK;
 776                         clk->id += LAST_PERIF_BANK - PERIF_BANK + 1;
 777                 } else {
 778                         clk->id -= PERIF_BANK;
 779                 }
 780         } else {
 781                 clk->id = 0;
 782         }
 783
 784         debug("%s clk->id %ld\n", __func__, clk->id);
 785
 786         return 0;
 787 }
 788
 789 static struct clk_ops stm32_clk_ops = {
 790         .of_xlate       = stm32_clk_of_xlate,
 791         .enable         = stm32_clk_enable,
 792         .get_rate       = stm32_clk_get_rate,
 793 };
 794
 795 U_BOOT_DRIVER(stm32h7_clk) = {
 796         .name                   = "stm32h7_rcc_clock",
 797         .id                     = UCLASS_CLK,
 798         .ops                    = &stm32_clk_ops,
 799         .probe                  = stm32_clk_probe,
 800         .priv_auto_alloc_size   = sizeof(struct stm32_clk),
 801         .flags                  = DM_FLAG_PRE_RELOC,
 802 };