3 * Vikas Manocha, <vikas.manocha@st.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <clk-uclass.h>
11 #include <asm/arch/rcc.h>
12 #include <asm/arch/stm32.h>
13 #include <asm/arch/stm32_periph.h>
15 #include <dt-bindings/mfd/stm32f7-rcc.h>
17 #define RCC_CR_HSION BIT(0)
18 #define RCC_CR_HSEON BIT(16)
19 #define RCC_CR_HSERDY BIT(17)
20 #define RCC_CR_HSEBYP BIT(18)
21 #define RCC_CR_CSSON BIT(19)
22 #define RCC_CR_PLLON BIT(24)
23 #define RCC_CR_PLLRDY BIT(25)
25 #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
26 #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
27 #define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
28 #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
29 #define RCC_PLLCFGR_PLLSRC BIT(22)
30 #define RCC_PLLCFGR_PLLM_SHIFT 0
31 #define RCC_PLLCFGR_PLLN_SHIFT 6
32 #define RCC_PLLCFGR_PLLP_SHIFT 16
33 #define RCC_PLLCFGR_PLLQ_SHIFT 24
35 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
36 #define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
37 #define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
38 #define RCC_CFGR_SW0 BIT(0)
39 #define RCC_CFGR_SW1 BIT(1)
40 #define RCC_CFGR_SW_MASK GENMASK(1, 0)
41 #define RCC_CFGR_SW_HSI 0
42 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0
43 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1
44 #define RCC_CFGR_SWS0 BIT(2)
45 #define RCC_CFGR_SWS1 BIT(3)
46 #define RCC_CFGR_SWS_MASK GENMASK(3, 2)
47 #define RCC_CFGR_SWS_HSI 0
48 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
49 #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
50 #define RCC_CFGR_HPRE_SHIFT 4
51 #define RCC_CFGR_PPRE1_SHIFT 10
52 #define RCC_CFGR_PPRE2_SHIFT 13
55 * Offsets of some PWR registers
57 #define PWR_CR1_ODEN BIT(16)
58 #define PWR_CR1_ODSWEN BIT(17)
59 #define PWR_CSR1_ODRDY BIT(16)
60 #define PWR_CSR1_ODSWRDY BIT(17)
76 #define AHB_PSC_16 0xB
77 #define AHB_PSC_64 0xC
78 #define AHB_PSC_128 0xD
79 #define AHB_PSC_256 0xE
80 #define AHB_PSC_512 0xF
86 #define APB_PSC_16 0x7
89 struct stm32_rcc_regs *base;
92 #if !defined(CONFIG_STM32_HSE_HZ)
93 #error "CONFIG_STM32_HSE_HZ not defined!"
95 #if (CONFIG_STM32_HSE_HZ == 25000000)
96 #if (CONFIG_SYS_CLK_FREQ == 200000000)
98 struct pll_psc sys_pll_psc = {
103 .ahb_psc = AHB_PSC_1,
104 .apb1_psc = APB_PSC_4,
105 .apb2_psc = APB_PSC_2
109 #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
113 static int configure_clocks(struct udevice *dev)
115 struct stm32_clk *priv = dev_get_priv(dev);
116 struct stm32_rcc_regs *regs = priv->base;
118 /* Reset RCC configuration */
119 setbits_le32(®s->cr, RCC_CR_HSION);
120 writel(0, ®s->cfgr); /* Reset CFGR */
121 clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON
123 writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */
124 clrbits_le32(®s->cr, RCC_CR_HSEBYP);
125 writel(0, ®s->cir); /* Disable all interrupts */
127 /* Configure for HSE+PLL operation */
128 setbits_le32(®s->cr, RCC_CR_HSEON);
129 while (!(readl(®s->cr) & RCC_CR_HSERDY))
132 setbits_le32(®s->cfgr, ((
133 sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
134 | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
135 | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
137 /* Configure the main PLL */
138 uint32_t pllcfgr = 0;
139 pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */
140 pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT;
141 pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT;
142 pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT;
143 pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT;
144 writel(pllcfgr, ®s->pllcfgr);
146 /* Enable the main PLL */
147 setbits_le32(®s->cr, RCC_CR_PLLON);
148 while (!(readl(®s->cr) & RCC_CR_PLLRDY))
151 /* Enable high performance mode, System frequency up to 200 MHz */
152 setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
153 setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
155 while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
157 /* Enable the Over-drive switch */
158 setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
160 while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
163 stm32_flash_latency_cfg(5);
164 clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
165 setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL);
167 while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) !=
174 unsigned long clock_get(enum clock clck)
178 /* Prescaler table lookups for clock computation */
179 u8 ahb_psc_table[16] = {
180 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
182 u8 apb_psc_table[8] = {
183 0, 0, 0, 0, 1, 2, 3, 4
186 if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
188 u16 pllm, plln, pllp;
189 pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
190 plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
191 >> RCC_PLLCFGR_PLLN_SHIFT);
192 pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
193 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
194 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
202 shift = ahb_psc_table[(
203 (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
204 >> RCC_CFGR_HPRE_SHIFT)];
205 return sysclk >>= shift;
208 shift = apb_psc_table[(
209 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
210 >> RCC_CFGR_PPRE1_SHIFT)];
211 return sysclk >>= shift;
214 shift = apb_psc_table[(
215 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
216 >> RCC_CFGR_PPRE2_SHIFT)];
217 return sysclk >>= shift;
225 static unsigned long stm32_clk_get_rate(struct clk *clk)
227 struct stm32_clk *priv = dev_get_priv(clk->dev);
228 struct stm32_rcc_regs *regs = priv->base;
231 /* Prescaler table lookups for clock computation */
232 u8 ahb_psc_table[16] = {
233 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
235 u8 apb_psc_table[8] = {
236 0, 0, 0, 0, 1, 2, 3, 4
239 if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) ==
241 u16 pllm, plln, pllp;
242 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
243 plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
244 >> RCC_PLLCFGR_PLLN_SHIFT);
245 pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
246 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
247 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
254 * AHB CLOCK: 3 x 32 bits consecutive registers are used :
255 * AHB1, AHB2 and AHB3
257 case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
258 shift = ahb_psc_table[(
259 (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK)
260 >> RCC_CFGR_HPRE_SHIFT)];
261 return sysclk >>= shift;
264 case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
265 shift = apb_psc_table[(
266 (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK)
267 >> RCC_CFGR_PPRE1_SHIFT)];
268 return sysclk >>= shift;
271 case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
272 shift = apb_psc_table[(
273 (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK)
274 >> RCC_CFGR_PPRE2_SHIFT)];
275 return sysclk >>= shift;
278 error("clock index %ld out of range\n", clk->id);
284 static int stm32_clk_enable(struct clk *clk)
286 struct stm32_clk *priv = dev_get_priv(clk->dev);
287 struct stm32_rcc_regs *regs = priv->base;
288 u32 offset = clk->id / 32;
289 u32 bit_index = clk->id % 32;
291 debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
292 __func__, clk->id, offset, bit_index);
293 setbits_le32(®s->ahb1enr + offset, BIT(bit_index));
298 void clock_setup(int peripheral)
300 switch (peripheral) {
301 case SYSCFG_CLOCK_CFG:
302 setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
304 case TIMER2_CLOCK_CFG:
305 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
307 case STMMAC_CLOCK_CFG:
308 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN);
309 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN);
310 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN);
317 static int stm32_clk_probe(struct udevice *dev)
319 debug("%s: stm32_clk_probe\n", __func__);
321 struct stm32_clk *priv = dev_get_priv(dev);
324 addr = devfdt_get_addr(dev);
325 if (addr == FDT_ADDR_T_NONE)
328 priv->base = (struct stm32_rcc_regs *)addr;
330 configure_clocks(dev);
335 static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
337 debug("%s(clk=%p)\n", __func__, clk);
339 if (args->args_count != 2) {
340 debug("Invaild args_count: %d\n", args->args_count);
344 if (args->args_count)
345 clk->id = args->args[1];
352 static struct clk_ops stm32_clk_ops = {
353 .of_xlate = stm32_clk_of_xlate,
354 .enable = stm32_clk_enable,
355 .get_rate = stm32_clk_get_rate,
358 static const struct udevice_id stm32_clk_ids[] = {
359 { .compatible = "st,stm32f42xx-rcc"},
363 U_BOOT_DRIVER(stm32f7_clk) = {
364 .name = "stm32f7_clk",
366 .of_match = stm32_clk_ids,
367 .ops = &stm32_clk_ops,
368 .probe = stm32_clk_probe,
369 .flags = DM_FLAG_PRE_RELOC,