2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <clk-uclass.h>
11 #include <stm32_rcc.h>
14 #include <asm/arch/stm32.h>
15 #include <asm/arch/stm32_pwr.h>
17 #include <dt-bindings/mfd/stm32f7-rcc.h>
19 #define RCC_CR_HSION BIT(0)
20 #define RCC_CR_HSEON BIT(16)
21 #define RCC_CR_HSERDY BIT(17)
22 #define RCC_CR_HSEBYP BIT(18)
23 #define RCC_CR_CSSON BIT(19)
24 #define RCC_CR_PLLON BIT(24)
25 #define RCC_CR_PLLRDY BIT(25)
26 #define RCC_CR_PLLSAION BIT(28)
27 #define RCC_CR_PLLSAIRDY BIT(29)
29 #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
30 #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
31 #define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
32 #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
33 #define RCC_PLLCFGR_PLLSRC BIT(22)
34 #define RCC_PLLCFGR_PLLM_SHIFT 0
35 #define RCC_PLLCFGR_PLLN_SHIFT 6
36 #define RCC_PLLCFGR_PLLP_SHIFT 16
37 #define RCC_PLLCFGR_PLLQ_SHIFT 24
39 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
40 #define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
41 #define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
42 #define RCC_CFGR_SW0 BIT(0)
43 #define RCC_CFGR_SW1 BIT(1)
44 #define RCC_CFGR_SW_MASK GENMASK(1, 0)
45 #define RCC_CFGR_SW_HSI 0
46 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0
47 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1
48 #define RCC_CFGR_SWS0 BIT(2)
49 #define RCC_CFGR_SWS1 BIT(3)
50 #define RCC_CFGR_SWS_MASK GENMASK(3, 2)
51 #define RCC_CFGR_SWS_HSI 0
52 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
53 #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
54 #define RCC_CFGR_HPRE_SHIFT 4
55 #define RCC_CFGR_PPRE1_SHIFT 10
56 #define RCC_CFGR_PPRE2_SHIFT 13
58 #define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6)
59 #define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16)
60 #define RCC_PLLSAICFGR_PLLSAIQ_MASK GENMASK(27, 24)
61 #define RCC_PLLSAICFGR_PLLSAIR_MASK GENMASK(30, 28)
62 #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
63 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
64 #define RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24
65 #define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28
66 #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16)
67 #define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
68 #define RCC_PLLSAICFGR_PLLSAIR_3 BIT(29) | BIT(28)
70 #define RCC_DCKCFGRX_TIMPRE BIT(24)
71 #define RCC_DCKCFGRX_CK48MSEL BIT(27)
72 #define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
73 #define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
75 #define RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16
76 #define RCC_DCKCFGR_PLLSAIDIVR_MASK GENMASK(17, 16)
77 #define RCC_DCKCFGR_PLLSAIDIVR_2 0
80 * RCC AHB1ENR specific definitions
82 #define RCC_AHB1ENR_ETHMAC_EN BIT(25)
83 #define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
84 #define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
87 * RCC APB1ENR specific definitions
89 #define RCC_APB1ENR_TIM2EN BIT(0)
90 #define RCC_APB1ENR_PWREN BIT(28)
93 * RCC APB2ENR specific definitions
95 #define RCC_APB2ENR_SYSCFGEN BIT(14)
96 #define RCC_APB2ENR_SAI1EN BIT(22)
104 static const struct stm32_clk_info stm32f4_clk_info = {
110 .ahb_psc = AHB_PSC_1,
111 .apb1_psc = APB_PSC_4,
112 .apb2_psc = APB_PSC_2,
114 .has_overdrive = false,
118 static const struct stm32_clk_info stm32f7_clk_info = {
124 .ahb_psc = AHB_PSC_1,
125 .apb1_psc = APB_PSC_4,
126 .apb2_psc = APB_PSC_2,
128 .has_overdrive = true,
133 struct stm32_rcc_regs *base;
134 struct stm32_pwr_regs *pwr_regs;
135 struct stm32_clk_info info;
136 unsigned long hse_rate;
139 #ifdef CONFIG_VIDEO_STM32
140 static const u8 plldivr_table[] = { 0, 0, 2, 3, 4, 5, 6, 7 };
142 static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 };
144 static int configure_clocks(struct udevice *dev)
146 struct stm32_clk *priv = dev_get_priv(dev);
147 struct stm32_rcc_regs *regs = priv->base;
148 struct stm32_pwr_regs *pwr = priv->pwr_regs;
149 struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
151 /* Reset RCC configuration */
152 setbits_le32(®s->cr, RCC_CR_HSION);
153 writel(0, ®s->cfgr); /* Reset CFGR */
154 clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON
155 | RCC_CR_PLLON | RCC_CR_PLLSAION));
156 writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */
157 clrbits_le32(®s->cr, RCC_CR_HSEBYP);
158 writel(0, ®s->cir); /* Disable all interrupts */
160 /* Configure for HSE+PLL operation */
161 setbits_le32(®s->cr, RCC_CR_HSEON);
162 while (!(readl(®s->cr) & RCC_CR_HSERDY))
165 setbits_le32(®s->cfgr, ((
166 sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT)
167 | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT)
168 | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
170 /* Configure the main PLL */
171 setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
172 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
173 sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT);
174 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
175 sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT);
176 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
177 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
178 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
179 sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
181 /* configure SDMMC clock */
182 if (priv->info.v2) { /*stm32f7 case */
183 /* select PLLQ as 48MHz clock source */
184 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
186 /* select 48MHz as SDMMC1 clock source */
187 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
189 /* select 48MHz as SDMMC2 clock source */
190 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
191 } else { /* stm32f4 case */
192 /* select PLLQ as 48MHz clock source */
193 clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
195 /* select 48MHz as SDMMC1 clock source */
196 clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
199 #ifdef CONFIG_VIDEO_STM32
201 * Configure the SAI PLL to generate LTDC pixel clock
203 clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
204 RCC_PLLSAICFGR_PLLSAIR_3);
205 clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIN_MASK,
206 195 << RCC_PLLSAICFGR_PLLSAIN_SHIFT);
208 clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
209 RCC_DCKCFGR_PLLSAIDIVR_2 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
211 /* Enable the main PLL */
212 setbits_le32(®s->cr, RCC_CR_PLLON);
213 while (!(readl(®s->cr) & RCC_CR_PLLRDY))
216 #ifdef CONFIG_VIDEO_STM32
217 /* Enable the SAI PLL */
218 setbits_le32(®s->cr, RCC_CR_PLLSAION);
219 while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY))
222 setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
224 if (priv->info.has_overdrive) {
226 * Enable high performance mode
227 * System frequency up to 200 MHz
229 setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
231 while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
233 /* Enable the Over-drive switch */
234 setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
236 while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
240 stm32_flash_latency_cfg(5);
241 clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
242 setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL);
244 while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) !=
248 #ifdef CONFIG_ETH_DESIGNWARE
249 /* gate the SYSCFG clock, needed to set RMII ethernet interface */
250 setbits_le32(®s->apb2enr, RCC_APB2ENR_SYSCFGEN);
256 static bool stm32_clk_get_ck48msel(struct stm32_clk *priv)
258 struct stm32_rcc_regs *regs = priv->base;
260 if (priv->info.v2) /*stm32f7 case */
261 return readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
264 return readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
267 static unsigned long stm32_clk_get_pllsai_vco_rate(struct stm32_clk *priv)
269 struct stm32_rcc_regs *regs = priv->base;
272 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
273 pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK)
274 >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
276 return ((priv->hse_rate / pllm) * pllsain);
279 static unsigned long stm32_clk_get_pllsai_rate(struct stm32_clk *priv,
280 enum pllsai_div output)
282 struct stm32_rcc_regs *regs = priv->base;
287 pll_div_output = ((((readl(®s->pllsaicfgr)
288 & RCC_PLLSAICFGR_PLLSAIP_MASK)
289 >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
292 pll_div_output = (readl(®s->pllsaicfgr)
293 & RCC_PLLSAICFGR_PLLSAIQ_MASK)
294 >> RCC_PLLSAICFGR_PLLSAIQ_SHIFT;
297 pll_div_output = (readl(®s->pllsaicfgr)
298 & RCC_PLLSAICFGR_PLLSAIR_MASK)
299 >> RCC_PLLSAICFGR_PLLSAIR_SHIFT;
302 pr_err("incorrect PLLSAI output %d\n", output);
306 return (stm32_clk_get_pllsai_vco_rate(priv) / pll_div_output);
309 static bool stm32_get_timpre(struct stm32_clk *priv)
311 struct stm32_rcc_regs *regs = priv->base;
314 if (priv->info.v2) /*stm32f7 case */
315 val = readl(®s->dckcfgr2);
317 val = readl(®s->dckcfgr);
318 /* get timer prescaler */
319 return !!(val & RCC_DCKCFGRX_TIMPRE);
322 static u32 stm32_get_hclk_rate(struct stm32_rcc_regs *regs, u32 sysclk)
325 /* Prescaler table lookups for clock computation */
326 u8 ahb_psc_table[16] = {
327 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
330 shift = ahb_psc_table[(
331 (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK)
332 >> RCC_CFGR_HPRE_SHIFT)];
334 return sysclk >> shift;
337 static u8 stm32_get_apb_shift(struct stm32_rcc_regs *regs, enum apb apb)
339 /* Prescaler table lookups for clock computation */
340 u8 apb_psc_table[8] = {
341 0, 0, 0, 0, 1, 2, 3, 4
345 return apb_psc_table[(
346 (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK)
347 >> RCC_CFGR_PPRE1_SHIFT)];
349 return apb_psc_table[(
350 (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK)
351 >> RCC_CFGR_PPRE2_SHIFT)];
354 static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
357 struct stm32_rcc_regs *regs = priv->base;
358 u8 shift = stm32_get_apb_shift(regs, apb);
360 if (stm32_get_timpre(priv))
362 * if APB prescaler is configured to a
363 * division factor of 1, 2 or 4
369 return stm32_get_hclk_rate(regs, sysclk);
371 return (sysclk >> shift) * 4;
375 * if APB prescaler is configured to a
376 * division factor of 1
381 return (sysclk >> shift) * 2;
384 static ulong stm32_clk_get_rate(struct clk *clk)
386 struct stm32_clk *priv = dev_get_priv(clk->dev);
387 struct stm32_rcc_regs *regs = priv->base;
393 u16 pllm, plln, pllp, pllq;
395 if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) ==
397 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
398 plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
399 >> RCC_PLLCFGR_PLLN_SHIFT);
400 pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
401 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
402 pllq = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
403 >> RCC_PLLCFGR_PLLQ_SHIFT);
404 vco = (priv->hse_rate / pllm) * plln;
412 * AHB CLOCK: 3 x 32 bits consecutive registers are used :
413 * AHB1, AHB2 and AHB3
415 case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
416 return stm32_get_hclk_rate(regs, sysclk);
418 case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
419 /* For timer clock, an additionnal prescaler is used*/
421 case STM32F7_APB1_CLOCK(TIM2):
422 case STM32F7_APB1_CLOCK(TIM3):
423 case STM32F7_APB1_CLOCK(TIM4):
424 case STM32F7_APB1_CLOCK(TIM5):
425 case STM32F7_APB1_CLOCK(TIM6):
426 case STM32F7_APB1_CLOCK(TIM7):
427 case STM32F7_APB1_CLOCK(TIM12):
428 case STM32F7_APB1_CLOCK(TIM13):
429 case STM32F7_APB1_CLOCK(TIM14):
430 return stm32_get_timer_rate(priv, sysclk, APB1);
432 return (sysclk >> stm32_get_apb_shift(regs, APB1));
435 case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(DSI):
438 * particular case for SDMMC1 and SDMMC2 :
439 * 48Mhz source clock can be from main PLL or from
442 case STM32F7_APB2_CLOCK(SDMMC1):
443 case STM32F7_APB2_CLOCK(SDMMC2):
444 if (clk->id == STM32F7_APB2_CLOCK(SDMMC1))
445 sdmmcxsel_bit = RCC_DCKCFGRX_SDMMC1SEL;
447 sdmmcxsel_bit = RCC_DCKCFGR2_SDMMC2SEL;
449 if (readl(®s->dckcfgr2) & sdmmcxsel_bit)
450 /* System clock is selected as SDMMC1 clock */
453 * 48 MHz can be generated by either PLLSAIP
454 * or by PLLQ depending of CK48MSEL bit of RCC_DCKCFGR
456 if (stm32_clk_get_ck48msel(priv))
457 return stm32_clk_get_pllsai_rate(priv, PLLSAIP);
462 /* For timer clock, an additionnal prescaler is used*/
463 case STM32F7_APB2_CLOCK(TIM1):
464 case STM32F7_APB2_CLOCK(TIM8):
465 case STM32F7_APB2_CLOCK(TIM9):
466 case STM32F7_APB2_CLOCK(TIM10):
467 case STM32F7_APB2_CLOCK(TIM11):
468 return stm32_get_timer_rate(priv, sysclk, APB2);
471 /* particular case for LTDC clock */
472 case STM32F7_APB2_CLOCK(LTDC):
473 saidivr = readl(®s->dckcfgr);
474 saidivr = (saidivr & RCC_DCKCFGR_PLLSAIDIVR_MASK)
475 >> RCC_DCKCFGR_PLLSAIDIVR_SHIFT;
476 pllsai_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
478 return pllsai_rate / pllsaidivr_table[saidivr];
480 return (sysclk >> stm32_get_apb_shift(regs, APB2));
483 pr_err("clock index %ld out of range\n", clk->id);
488 static ulong stm32_set_rate(struct clk *clk, ulong rate)
490 #ifdef CONFIG_VIDEO_STM32
491 struct stm32_clk *priv = dev_get_priv(clk->dev);
492 struct stm32_rcc_regs *regs = priv->base;
493 u32 pllsair_rate, pllsai_vco_rate, current_rate;
494 u32 best_div, best_diff, diff;
496 u8 best_plldivr, best_pllsaidivr;
500 /* Only set_rate for LTDC clock is implemented */
501 if (clk->id != STM32F7_APB2_CLOCK(LTDC)) {
502 pr_err("set_rate not implemented for clock index %ld\n",
507 if (rate == stm32_clk_get_rate(clk))
508 /* already set to requested rate */
511 /* get the current PLLSAIR output freq */
512 pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
513 best_div = pllsair_rate / rate;
515 /* look into pllsaidivr_table if this divider is available*/
516 for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
517 if (best_div == pllsaidivr_table[i]) {
518 /* set pll_saidivr with found value */
519 clrsetbits_le32(®s->dckcfgr,
520 RCC_DCKCFGR_PLLSAIDIVR_MASK,
521 pllsaidivr_table[i]);
526 * As no pllsaidivr value is suitable to obtain requested freq,
527 * test all combination of pllsaidivr * pllsair and find the one
528 * which give freq closest to requested rate.
531 pllsai_vco_rate = stm32_clk_get_pllsai_vco_rate(priv);
532 best_diff = ULONG_MAX;
536 * start at index 2 of plldivr_table as divider value at index 0
539 for (i = 2; i < sizeof(plldivr_table); i++) {
540 for (j = 0; j < sizeof(pllsaidivr_table); j++) {
541 div = plldivr_table[i] * pllsaidivr_table[j];
542 current_rate = pllsai_vco_rate / div;
543 /* perfect combination is found ? */
544 if (current_rate == rate) {
551 diff = (current_rate > rate) ?
552 current_rate - rate : rate - current_rate;
554 /* found a better combination ? */
555 if (diff < best_diff) {
566 /* Disable the SAI PLL */
567 clrbits_le32(®s->cr, RCC_CR_PLLSAION);
569 /* set pll_saidivr with found value */
570 clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
571 best_pllsaidivr << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
573 /* set pllsair with found value */
574 clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
575 plldivr_table[best_plldivr]
576 << RCC_PLLSAICFGR_PLLSAIR_SHIFT);
578 /* Enable the SAI PLL */
579 setbits_le32(®s->cr, RCC_CR_PLLSAION);
580 while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY))
583 div = plldivr_table[best_plldivr] * pllsaidivr_table[best_pllsaidivr];
584 return pllsai_vco_rate / div;
590 static int stm32_clk_enable(struct clk *clk)
592 struct stm32_clk *priv = dev_get_priv(clk->dev);
593 struct stm32_rcc_regs *regs = priv->base;
594 u32 offset = clk->id / 32;
595 u32 bit_index = clk->id % 32;
597 debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
598 __func__, clk->id, offset, bit_index);
599 setbits_le32(®s->ahb1enr + offset, BIT(bit_index));
604 static int stm32_clk_probe(struct udevice *dev)
606 struct ofnode_phandle_args args;
607 struct udevice *fixed_clock_dev = NULL;
611 debug("%s\n", __func__);
613 struct stm32_clk *priv = dev_get_priv(dev);
616 addr = dev_read_addr(dev);
617 if (addr == FDT_ADDR_T_NONE)
620 priv->base = (struct stm32_rcc_regs *)addr;
622 switch (dev_get_driver_data(dev)) {
624 memcpy(&priv->info, &stm32f4_clk_info,
625 sizeof(struct stm32_clk_info));
628 memcpy(&priv->info, &stm32f7_clk_info,
629 sizeof(struct stm32_clk_info));
635 /* retrieve HSE frequency (external oscillator) */
636 err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse",
640 pr_err("Can't find fixed clock (%d)", err);
644 err = clk_request(fixed_clock_dev, &clk);
646 pr_err("Can't request %s clk (%d)", fixed_clock_dev->name,
652 * set pllm factor accordingly to the external oscillator
653 * frequency (HSE). For STM32F4 and STM32F7, we want VCO
655 * if input PLL frequency is 25Mhz, divide it by 25
658 priv->hse_rate = clk_get_rate(&clk);
660 if (priv->hse_rate < 1000000) {
661 pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__,
666 priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000;
668 if (priv->info.has_overdrive) {
669 err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
672 debug("%s: can't find syscon device (%d)\n", __func__,
677 priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
680 configure_clocks(dev);
685 static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
687 debug("%s(clk=%p)\n", __func__, clk);
689 if (args->args_count != 2) {
690 debug("Invaild args_count: %d\n", args->args_count);
694 if (args->args_count)
695 clk->id = args->args[1];
702 static struct clk_ops stm32_clk_ops = {
703 .of_xlate = stm32_clk_of_xlate,
704 .enable = stm32_clk_enable,
705 .get_rate = stm32_clk_get_rate,
706 .set_rate = stm32_set_rate,
709 U_BOOT_DRIVER(stm32fx_clk) = {
710 .name = "stm32fx_rcc_clock",
712 .ops = &stm32_clk_ops,
713 .probe = stm32_clk_probe,
714 .priv_auto_alloc_size = sizeof(struct stm32_clk),
715 .flags = DM_FLAG_PRE_RELOC,