1 // SPDX-License-Identifier: GPL-2.0+
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
6 * Common Clock Framework [CCF] driver for Sandbox
14 #include <clk-uclass.h>
15 #include <dm/devres.h>
16 #include <linux/bitops.h>
17 #include <linux/clk-provider.h>
18 #include <sandbox-clk.h>
19 #include <linux/err.h>
22 * Sandbox implementation of CCF primitives necessary for clk-uclass testing
24 * --- Sandbox PLLv3 ---
32 int sandbox_clk_enable_count(struct clk *clk)
34 struct clk *clkp = NULL;
37 ret = clk_get_by_id(clk->id, &clkp);
41 return clkp->enable_count;
44 static ulong clk_pllv3_get_rate(struct clk *clk)
46 unsigned long parent_rate = clk_get_parent_rate(clk);
48 return parent_rate * 24;
51 static const struct clk_ops clk_pllv3_generic_ops = {
52 .get_rate = clk_pllv3_get_rate,
55 struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
56 const char *parent_name, void __iomem *base,
59 struct clk_pllv3 *pll;
61 char *drv_name = "sandbox_clk_pllv3";
64 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
66 return ERR_PTR(-ENOMEM);
68 pll->div_mask = div_mask;
71 ret = clk_register(clk, drv_name, name, parent_name);
80 U_BOOT_DRIVER(sandbox_clk_pll_generic) = {
81 .name = "sandbox_clk_pllv3",
83 .ops = &clk_pllv3_generic_ops,
86 /* --- Sandbox PLLv3 --- */
87 /* --- Sandbox Gate --- */
93 #define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
95 static int clk_gate2_enable(struct clk *clk)
97 struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
103 static int clk_gate2_disable(struct clk *clk)
105 struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
111 static const struct clk_ops clk_gate2_ops = {
112 .enable = clk_gate2_enable,
113 .disable = clk_gate2_disable,
114 .get_rate = clk_generic_get_rate,
117 struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
118 const char *parent_name,
119 unsigned long flags, void __iomem *reg,
120 u8 bit_idx, u8 cgr_val,
123 struct clk_gate2 *gate;
127 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
129 return ERR_PTR(-ENOMEM);
135 ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name);
144 U_BOOT_DRIVER(sandbox_clk_gate2) = {
145 .name = "sandbox_clk_gate2",
147 .ops = &clk_gate2_ops,
150 static unsigned long sandbox_clk_composite_divider_recalc_rate(struct clk *clk)
152 struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
153 struct clk_composite *composite = (struct clk_composite *)clk->data;
154 ulong parent_rate = clk_get_parent_rate(&composite->clk);
157 val = divider->io_divider_val;
158 val >>= divider->shift;
159 val &= clk_div_mask(divider->width);
161 return divider_recalc_rate(clk, parent_rate, val, divider->table,
162 divider->flags, divider->width);
165 static const struct clk_ops sandbox_clk_composite_divider_ops = {
166 .get_rate = sandbox_clk_composite_divider_recalc_rate,
169 struct clk *sandbox_clk_composite(const char *name,
170 const char * const *parent_names,
171 int num_parents, void __iomem *reg,
174 struct clk *clk = ERR_PTR(-ENOMEM);
175 struct clk_divider *div = NULL;
176 struct clk_gate *gate = NULL;
177 struct clk_mux *mux = NULL;
179 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
186 mux->num_parents = num_parents;
188 mux->parent_names = parent_names;
190 div = kzalloc(sizeof(*div), GFP_KERNEL);
197 div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
199 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
207 clk = clk_register_composite(NULL, name,
208 parent_names, num_parents,
209 &mux->clk, &clk_mux_ops, &div->clk,
210 &sandbox_clk_composite_divider_ops,
211 &gate->clk, &clk_gate_ops, flags);
221 return ERR_CAST(clk);
224 /* --- Sandbox Gate --- */
225 /* The CCF core driver itself */
226 static const struct udevice_id sandbox_clk_ccf_test_ids[] = {
227 { .compatible = "sandbox,clk-ccf" },
231 static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", };
232 static const char *const i2c_sels[] = { "pll3_60m", "pll3_80m", };
234 static int sandbox_clk_ccf_probe(struct udevice *dev)
239 clk_dm(SANDBOX_CLK_PLL3,
240 sandbox_clk_pllv3(SANDBOX_PLLV3_USB, "pll3_usb_otg", "osc",
243 clk_dm(SANDBOX_CLK_PLL3_60M,
244 sandbox_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
246 clk_dm(SANDBOX_CLK_PLL3_80M,
247 sandbox_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
249 /* The HW adds +1 to the divider value (2+1) is the divider */
251 clk_dm(SANDBOX_CLK_ECSPI_ROOT,
252 sandbox_clk_divider("ecspi_root", "pll3_60m", ®, 19, 6));
255 clk_dm(SANDBOX_CLK_ECSPI0,
256 sandbox_clk_gate("ecspi0", "ecspi_root", ®, 0, 0));
258 clk_dm(SANDBOX_CLK_ECSPI1,
259 sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
261 /* Select 'pll3_60m' */
263 clk_dm(SANDBOX_CLK_USDHC1_SEL,
264 sandbox_clk_mux("usdhc1_sel", ®, 16, 1, usdhc_sels,
265 ARRAY_SIZE(usdhc_sels)));
267 /* Select 'pll3_80m' */
269 clk_dm(SANDBOX_CLK_USDHC2_SEL,
270 sandbox_clk_mux("usdhc2_sel", ®, 17, 1, usdhc_sels,
271 ARRAY_SIZE(usdhc_sels)));
273 reg = BIT(28) | BIT(24) | BIT(16);
274 clk_dm(SANDBOX_CLK_I2C,
275 sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels),
276 ®, CLK_SET_RATE_UNGATE));
278 clk_dm(SANDBOX_CLK_I2C_ROOT,
279 sandbox_clk_gate2("i2c_root", "i2c", base + 0x7c, 0));
284 U_BOOT_DRIVER(sandbox_clk_ccf) = {
285 .name = "sandbox_clk_ccf",
287 .probe = sandbox_clk_ccf_probe,
288 .of_match = sandbox_clk_ccf_test_ids,