1 // SPDX-License-Identifier: GPL-2.0+
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
6 * Common Clock Framework [CCF] driver for Sandbox
13 #include <clk-uclass.h>
14 #include <dm/devres.h>
15 #include <linux/clk-provider.h>
16 #include <sandbox-clk.h>
17 #include <linux/err.h>
20 * Sandbox implementation of CCF primitives necessary for clk-uclass testing
22 * --- Sandbox PLLv3 ---
30 int sandbox_clk_enable_count(struct clk *clk)
32 struct clk *clkp = NULL;
35 ret = clk_get_by_id(clk->id, &clkp);
39 return clkp->enable_count;
42 static ulong clk_pllv3_get_rate(struct clk *clk)
44 unsigned long parent_rate = clk_get_parent_rate(clk);
46 return parent_rate * 24;
49 static const struct clk_ops clk_pllv3_generic_ops = {
50 .get_rate = clk_pllv3_get_rate,
53 struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
54 const char *parent_name, void __iomem *base,
57 struct clk_pllv3 *pll;
59 char *drv_name = "sandbox_clk_pllv3";
62 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
64 return ERR_PTR(-ENOMEM);
66 pll->div_mask = div_mask;
69 ret = clk_register(clk, drv_name, name, parent_name);
78 U_BOOT_DRIVER(sandbox_clk_pll_generic) = {
79 .name = "sandbox_clk_pllv3",
81 .ops = &clk_pllv3_generic_ops,
84 /* --- Sandbox PLLv3 --- */
85 /* --- Sandbox Gate --- */
91 #define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
93 static int clk_gate2_enable(struct clk *clk)
95 struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
101 static int clk_gate2_disable(struct clk *clk)
103 struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
109 static const struct clk_ops clk_gate2_ops = {
110 .enable = clk_gate2_enable,
111 .disable = clk_gate2_disable,
112 .get_rate = clk_generic_get_rate,
115 struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
116 const char *parent_name,
117 unsigned long flags, void __iomem *reg,
118 u8 bit_idx, u8 cgr_val,
121 struct clk_gate2 *gate;
125 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
127 return ERR_PTR(-ENOMEM);
132 ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name);
141 U_BOOT_DRIVER(sandbox_clk_gate2) = {
142 .name = "sandbox_clk_gate2",
144 .ops = &clk_gate2_ops,
147 static unsigned long sandbox_clk_composite_divider_recalc_rate(struct clk *clk)
149 struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
150 struct clk_composite *composite = (struct clk_composite *)clk->data;
151 ulong parent_rate = clk_get_parent_rate(&composite->clk);
154 val = divider->io_divider_val;
155 val >>= divider->shift;
156 val &= clk_div_mask(divider->width);
158 return divider_recalc_rate(clk, parent_rate, val, divider->table,
159 divider->flags, divider->width);
162 static const struct clk_ops sandbox_clk_composite_divider_ops = {
163 .get_rate = sandbox_clk_composite_divider_recalc_rate,
166 struct clk *sandbox_clk_composite(const char *name,
167 const char * const *parent_names,
168 int num_parents, void __iomem *reg,
171 struct clk *clk = ERR_PTR(-ENOMEM);
172 struct clk_divider *div = NULL;
173 struct clk_gate *gate = NULL;
174 struct clk_mux *mux = NULL;
176 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
183 mux->num_parents = num_parents;
185 mux->parent_names = parent_names;
187 div = kzalloc(sizeof(*div), GFP_KERNEL);
194 div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
196 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
204 clk = clk_register_composite(NULL, name,
205 parent_names, num_parents,
206 &mux->clk, &clk_mux_ops, &div->clk,
207 &sandbox_clk_composite_divider_ops,
208 &gate->clk, &clk_gate_ops, flags);
218 return ERR_CAST(clk);
221 /* --- Sandbox Gate --- */
222 /* The CCF core driver itself */
223 static const struct udevice_id sandbox_clk_ccf_test_ids[] = {
224 { .compatible = "sandbox,clk-ccf" },
228 static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", };
229 static const char *const i2c_sels[] = { "pll3_60m", "pll3_80m", };
231 static int sandbox_clk_ccf_probe(struct udevice *dev)
236 clk_dm(SANDBOX_CLK_PLL3,
237 sandbox_clk_pllv3(SANDBOX_PLLV3_USB, "pll3_usb_otg", "osc",
240 clk_dm(SANDBOX_CLK_PLL3_60M,
241 sandbox_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
243 clk_dm(SANDBOX_CLK_PLL3_80M,
244 sandbox_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
246 /* The HW adds +1 to the divider value (2+1) is the divider */
248 clk_dm(SANDBOX_CLK_ECSPI_ROOT,
249 sandbox_clk_divider("ecspi_root", "pll3_60m", ®, 19, 6));
251 clk_dm(SANDBOX_CLK_ECSPI1,
252 sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
254 /* Select 'pll3_60m' */
256 clk_dm(SANDBOX_CLK_USDHC1_SEL,
257 sandbox_clk_mux("usdhc1_sel", ®, 16, 1, usdhc_sels,
258 ARRAY_SIZE(usdhc_sels)));
260 /* Select 'pll3_80m' */
262 clk_dm(SANDBOX_CLK_USDHC2_SEL,
263 sandbox_clk_mux("usdhc2_sel", ®, 17, 1, usdhc_sels,
264 ARRAY_SIZE(usdhc_sels)));
266 reg = BIT(28) | BIT(24) | BIT(16);
267 clk_dm(SANDBOX_CLK_I2C,
268 sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels),
271 clk_dm(SANDBOX_CLK_I2C_ROOT,
272 sandbox_clk_gate2("i2c_root", "i2c", base + 0x7c, 0));
277 U_BOOT_DRIVER(sandbox_clk_ccf) = {
278 .name = "sandbox_clk_ccf",
280 .probe = sandbox_clk_ccf_probe,
281 .of_match = sandbox_clk_ccf_test_ids,