drivers/clk/clk_sandbox_ccf.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  *
   6  * Common Clock Framework [CCF] driver for Sandbox
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <clk.h>
  12 #include <malloc.h>
  13 #include <asm/clk.h>
  14 #include <clk-uclass.h>
  15 #include <dm/devres.h>
  16 #include <linux/bitops.h>
  17 #include <linux/clk-provider.h>
  18 #include <sandbox-clk.h>
  19 #include <linux/err.h>
  20
  21 /*
  22  * Sandbox implementation of CCF primitives necessary for clk-uclass testing
  23  *
  24  * --- Sandbox PLLv3 ---
  25  */
  26 struct clk_pllv3 {
  27         struct clk      clk;
  28         u32             div_mask;
  29         u32             div_shift;
  30 };
  31
  32 int sandbox_clk_enable_count(struct clk *clk)
  33 {
  34         struct clk *clkp = NULL;
  35         int ret;
  36
  37         ret = clk_get_by_id(clk->id, &clkp);
  38         if (ret)
  39                 return 0;
  40
  41         return clkp->enable_count;
  42 }
  43
  44 static ulong clk_pllv3_get_rate(struct clk *clk)
  45 {
  46         unsigned long parent_rate = clk_get_parent_rate(clk);
  47
  48         return parent_rate * 24;
  49 }
  50
  51 static const struct clk_ops clk_pllv3_generic_ops = {
  52         .get_rate       = clk_pllv3_get_rate,
  53 };
  54
  55 struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
  56                               const char *parent_name, void __iomem *base,
  57                               u32 div_mask)
  58 {
  59         struct clk_pllv3 *pll;
  60         struct clk *clk;
  61         char *drv_name = "sandbox_clk_pllv3";
  62         int ret;
  63
  64         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  65         if (!pll)
  66                 return ERR_PTR(-ENOMEM);
  67
  68         pll->div_mask = div_mask;
  69         clk = &pll->clk;
  70
  71         ret = clk_register(clk, drv_name, name, parent_name);
  72         if (ret) {
  73                 kfree(pll);
  74                 return ERR_PTR(ret);
  75         }
  76
  77         return clk;
  78 }
  79
  80 U_BOOT_DRIVER(sandbox_clk_pll_generic) = {
  81         .name   = "sandbox_clk_pllv3",
  82         .id     = UCLASS_CLK,
  83         .ops    = &clk_pllv3_generic_ops,
  84 };
  85
  86 /* --- Sandbox PLLv3 --- */
  87 /* --- Sandbox Gate  --- */
  88 struct clk_gate2 {
  89         struct clk clk;
  90         bool    state;
  91 };
  92
  93 #define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
  94
  95 static int clk_gate2_enable(struct clk *clk)
  96 {
  97         struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
  98
  99         gate->state = 1;
 100         return 0;
 101 }
 102
 103 static int clk_gate2_disable(struct clk *clk)
 104 {
 105         struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
 106
 107         gate->state = 0;
 108         return 0;
 109 }
 110
 111 static const struct clk_ops clk_gate2_ops = {
 112         .enable = clk_gate2_enable,
 113         .disable = clk_gate2_disable,
 114         .get_rate = clk_generic_get_rate,
 115 };
 116
 117 struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
 118                                        const char *parent_name,
 119                                        unsigned long flags, void __iomem *reg,
 120                                        u8 bit_idx, u8 cgr_val,
 121                                        u8 clk_gate2_flags)
 122 {
 123         struct clk_gate2 *gate;
 124         struct clk *clk;
 125         int ret;
 126
 127         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 128         if (!gate)
 129                 return ERR_PTR(-ENOMEM);
 130
 131         gate->state = 0;
 132         clk = &gate->clk;
 133
 134         ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name);
 135         if (ret) {
 136                 kfree(gate);
 137                 return ERR_PTR(ret);
 138         }
 139
 140         return clk;
 141 }
 142
 143 U_BOOT_DRIVER(sandbox_clk_gate2) = {
 144         .name   = "sandbox_clk_gate2",
 145         .id     = UCLASS_CLK,
 146         .ops    = &clk_gate2_ops,
 147 };
 148
 149 static unsigned long sandbox_clk_composite_divider_recalc_rate(struct clk *clk)
 150 {
 151         struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
 152         struct clk_composite *composite = (struct clk_composite *)clk->data;
 153         ulong parent_rate = clk_get_parent_rate(&composite->clk);
 154         unsigned int val;
 155
 156         val = divider->io_divider_val;
 157         val >>= divider->shift;
 158         val &= clk_div_mask(divider->width);
 159
 160         return divider_recalc_rate(clk, parent_rate, val, divider->table,
 161                                    divider->flags, divider->width);
 162 }
 163
 164 static const struct clk_ops sandbox_clk_composite_divider_ops = {
 165         .get_rate = sandbox_clk_composite_divider_recalc_rate,
 166 };
 167
 168 struct clk *sandbox_clk_composite(const char *name,
 169                                   const char * const *parent_names,
 170                                   int num_parents, void __iomem *reg,
 171                                   unsigned long flags)
 172 {
 173         struct clk *clk = ERR_PTR(-ENOMEM);
 174         struct clk_divider *div = NULL;
 175         struct clk_gate *gate = NULL;
 176         struct clk_mux *mux = NULL;
 177
 178         mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 179         if (!mux)
 180                 goto fail;
 181
 182         mux->reg = reg;
 183         mux->shift = 24;
 184         mux->mask = 0x7;
 185         mux->num_parents = num_parents;
 186         mux->flags = flags;
 187         mux->parent_names = parent_names;
 188
 189         div = kzalloc(sizeof(*div), GFP_KERNEL);
 190         if (!div)
 191                 goto fail;
 192
 193         div->reg = reg;
 194         div->shift = 16;
 195         div->width = 3;
 196         div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
 197
 198         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 199         if (!gate)
 200                 goto fail;
 201
 202         gate->reg = reg;
 203         gate->bit_idx = 28;
 204         gate->flags = flags;
 205
 206         clk = clk_register_composite(NULL, name,
 207                                      parent_names, num_parents,
 208                                      &mux->clk, &clk_mux_ops, &div->clk,
 209                                      &sandbox_clk_composite_divider_ops,
 210                                      &gate->clk, &clk_gate_ops, flags);
 211         if (IS_ERR(clk))
 212                 goto fail;
 213
 214         return clk;
 215
 216 fail:
 217         kfree(gate);
 218         kfree(div);
 219         kfree(mux);
 220         return ERR_CAST(clk);
 221 }
 222
 223 /* --- Sandbox Gate --- */
 224 /* The CCF core driver itself */
 225 static const struct udevice_id sandbox_clk_ccf_test_ids[] = {
 226         { .compatible = "sandbox,clk-ccf" },
 227         { }
 228 };
 229
 230 static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", };
 231 static const char *const i2c_sels[] = { "pll3_60m", "pll3_80m", };
 232
 233 static int sandbox_clk_ccf_probe(struct udevice *dev)
 234 {
 235         void *base = NULL;
 236         u32 reg;
 237
 238         clk_dm(SANDBOX_CLK_PLL3,
 239                sandbox_clk_pllv3(SANDBOX_PLLV3_USB, "pll3_usb_otg", "osc",
 240                                  base + 0x10, 0x3));
 241
 242         clk_dm(SANDBOX_CLK_PLL3_60M,
 243                sandbox_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8));
 244
 245         clk_dm(SANDBOX_CLK_PLL3_80M,
 246                sandbox_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6));
 247
 248         /* The HW adds +1 to the divider value (2+1) is the divider */
 249         reg = (2 << 19);
 250         clk_dm(SANDBOX_CLK_ECSPI_ROOT,
 251                sandbox_clk_divider("ecspi_root", "pll3_60m", &reg, 19, 6));
 252
 253         clk_dm(SANDBOX_CLK_ECSPI1,
 254                sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
 255
 256         /* Select 'pll3_60m' */
 257         reg = 0;
 258         clk_dm(SANDBOX_CLK_USDHC1_SEL,
 259                sandbox_clk_mux("usdhc1_sel", &reg, 16, 1, usdhc_sels,
 260                                ARRAY_SIZE(usdhc_sels)));
 261
 262         /* Select 'pll3_80m' */
 263         reg = BIT(17);
 264         clk_dm(SANDBOX_CLK_USDHC2_SEL,
 265                sandbox_clk_mux("usdhc2_sel", &reg, 17, 1, usdhc_sels,
 266                                ARRAY_SIZE(usdhc_sels)));
 267
 268         reg = BIT(28) | BIT(24) | BIT(16);
 269         clk_dm(SANDBOX_CLK_I2C,
 270                sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels),
 271                                      &reg, 0));
 272
 273         clk_dm(SANDBOX_CLK_I2C_ROOT,
 274                sandbox_clk_gate2("i2c_root", "i2c", base + 0x7c, 0));
 275
 276         return 0;
 277 }
 278
 279 U_BOOT_DRIVER(sandbox_clk_ccf) = {
 280         .name = "sandbox_clk_ccf",
 281         .id = UCLASS_CLK,
 282         .probe = sandbox_clk_ccf_probe,
 283         .of_match = sandbox_clk_ccf_test_ids,
 284 };