2 * clk-xgene.c - AppliedMicro X-Gene Clock Interface
4 * Copyright (c) 2013, Applied Micro Circuits Corporation
5 * Author: Loc Ho <lho@apm.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <linux/module.h>
24 #include <linux/spinlock.h>
27 #include <linux/clkdev.h>
28 #include <linux/clk-provider.h>
29 #include <linux/of_address.h>
31 /* Register SCU_PCPPLL bit fields */
32 #define N_DIV_RD(src) (((src) & 0x000001ff))
34 /* Register SCU_SOCPLL bit fields */
35 #define CLKR_RD(src) (((src) & 0x07000000)>>24)
36 #define CLKOD_RD(src) (((src) & 0x00300000)>>20)
37 #define REGSPEC_RESET_F1_MASK 0x00010000
38 #define CLKF_RD(src) (((src) & 0x000001ff))
40 #define XGENE_CLK_DRIVER_VER "0.1"
42 static DEFINE_SPINLOCK(clk_lock);
44 static inline u32 xgene_clk_read(void __iomem *csr)
46 return readl_relaxed(csr);
49 static inline void xgene_clk_write(u32 data, void __iomem *csr)
51 return writel_relaxed(data, csr);
60 struct xgene_clk_pll {
65 enum xgene_pll_type type;
68 #define to_xgene_clk_pll(_hw) container_of(_hw, struct xgene_clk_pll, hw)
70 static int xgene_clk_pll_is_enabled(struct clk_hw *hw)
72 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw);
75 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
76 pr_debug("%s pll %s\n", clk_hw_get_name(hw),
77 data & REGSPEC_RESET_F1_MASK ? "disabled" : "enabled");
79 return data & REGSPEC_RESET_F1_MASK ? 0 : 1;
82 static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw,
83 unsigned long parent_rate)
85 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw);
93 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
95 if (pllclk->type == PLL_TYPE_PCP) {
97 * PLL VCO = Reference clock * NF
98 * PCP PLL = PLL_VCO / 2
101 fvco = parent_rate * (N_DIV_RD(pll) + 4);
104 * Fref = Reference Clock / NREF;
106 * Fout = Fvco / NOUT;
108 nref = CLKR_RD(pll) + 1;
109 nout = CLKOD_RD(pll) + 1;
111 fref = parent_rate / nref;
114 pr_debug("%s pll recalc rate %ld parent %ld\n", clk_hw_get_name(hw),
115 fvco / nout, parent_rate);
120 static const struct clk_ops xgene_clk_pll_ops = {
121 .is_enabled = xgene_clk_pll_is_enabled,
122 .recalc_rate = xgene_clk_pll_recalc_rate,
125 static struct clk *xgene_register_clk_pll(struct device *dev,
126 const char *name, const char *parent_name,
127 unsigned long flags, void __iomem *reg, u32 pll_offset,
128 u32 type, spinlock_t *lock)
130 struct xgene_clk_pll *apmclk;
132 struct clk_init_data init;
134 /* allocate the APM clock structure */
135 apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL);
137 pr_err("%s: could not allocate APM clk\n", __func__);
138 return ERR_PTR(-ENOMEM);
142 init.ops = &xgene_clk_pll_ops;
144 init.parent_names = parent_name ? &parent_name : NULL;
145 init.num_parents = parent_name ? 1 : 0;
149 apmclk->pll_offset = pll_offset;
151 apmclk->hw.init = &init;
153 /* Register the clock */
154 clk = clk_register(dev, &apmclk->hw);
156 pr_err("%s: could not register clk %s\n", __func__, name);
163 static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type)
165 const char *clk_name = np->full_name;
169 reg = of_iomap(np, 0);
171 pr_err("Unable to map CSR register for %s\n", np->full_name);
174 of_property_read_string(np, "clock-output-names", &clk_name);
175 clk = xgene_register_clk_pll(NULL,
176 clk_name, of_clk_get_parent_name(np, 0),
177 CLK_IS_ROOT, reg, 0, pll_type, &clk_lock);
179 of_clk_add_provider(np, of_clk_src_simple_get, clk);
180 clk_register_clkdev(clk, clk_name, NULL);
181 pr_debug("Add %s clock PLL\n", clk_name);
185 static void xgene_socpllclk_init(struct device_node *np)
187 xgene_pllclk_init(np, PLL_TYPE_SOC);
190 static void xgene_pcppllclk_init(struct device_node *np)
192 xgene_pllclk_init(np, PLL_TYPE_PCP);
196 struct xgene_dev_parameters {
197 void __iomem *csr_reg; /* CSR for IP clock */
198 u32 reg_clk_offset; /* Offset to clock enable CSR */
199 u32 reg_clk_mask; /* Mask bit for clock enable */
200 u32 reg_csr_offset; /* Offset to CSR reset */
201 u32 reg_csr_mask; /* Mask bit for disable CSR reset */
202 void __iomem *divider_reg; /* CSR for divider */
203 u32 reg_divider_offset; /* Offset to divider register */
204 u32 reg_divider_shift; /* Bit shift to divider field */
205 u32 reg_divider_width; /* Width of the bit to divider field */
211 struct xgene_dev_parameters param;
214 #define to_xgene_clk(_hw) container_of(_hw, struct xgene_clk, hw)
216 static int xgene_clk_enable(struct clk_hw *hw)
218 struct xgene_clk *pclk = to_xgene_clk(hw);
219 unsigned long flags = 0;
224 spin_lock_irqsave(pclk->lock, flags);
226 if (pclk->param.csr_reg != NULL) {
227 pr_debug("%s clock enabled\n", clk_hw_get_name(hw));
228 reg = __pa(pclk->param.csr_reg);
229 /* First enable the clock */
230 data = xgene_clk_read(pclk->param.csr_reg +
231 pclk->param.reg_clk_offset);
232 data |= pclk->param.reg_clk_mask;
233 xgene_clk_write(data, pclk->param.csr_reg +
234 pclk->param.reg_clk_offset);
235 pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X value 0x%08X\n",
236 clk_hw_get_name(hw), ®,
237 pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,
240 /* Second enable the CSR */
241 data = xgene_clk_read(pclk->param.csr_reg +
242 pclk->param.reg_csr_offset);
243 data &= ~pclk->param.reg_csr_mask;
244 xgene_clk_write(data, pclk->param.csr_reg +
245 pclk->param.reg_csr_offset);
246 pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 0x%08X value 0x%08X\n",
247 clk_hw_get_name(hw), ®,
248 pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,
253 spin_unlock_irqrestore(pclk->lock, flags);
258 static void xgene_clk_disable(struct clk_hw *hw)
260 struct xgene_clk *pclk = to_xgene_clk(hw);
261 unsigned long flags = 0;
265 spin_lock_irqsave(pclk->lock, flags);
267 if (pclk->param.csr_reg != NULL) {
268 pr_debug("%s clock disabled\n", clk_hw_get_name(hw));
269 /* First put the CSR in reset */
270 data = xgene_clk_read(pclk->param.csr_reg +
271 pclk->param.reg_csr_offset);
272 data |= pclk->param.reg_csr_mask;
273 xgene_clk_write(data, pclk->param.csr_reg +
274 pclk->param.reg_csr_offset);
276 /* Second disable the clock */
277 data = xgene_clk_read(pclk->param.csr_reg +
278 pclk->param.reg_clk_offset);
279 data &= ~pclk->param.reg_clk_mask;
280 xgene_clk_write(data, pclk->param.csr_reg +
281 pclk->param.reg_clk_offset);
285 spin_unlock_irqrestore(pclk->lock, flags);
288 static int xgene_clk_is_enabled(struct clk_hw *hw)
290 struct xgene_clk *pclk = to_xgene_clk(hw);
293 if (pclk->param.csr_reg != NULL) {
294 pr_debug("%s clock checking\n", clk_hw_get_name(hw));
295 data = xgene_clk_read(pclk->param.csr_reg +
296 pclk->param.reg_clk_offset);
297 pr_debug("%s clock is %s\n", clk_hw_get_name(hw),
298 data & pclk->param.reg_clk_mask ? "enabled" :
302 if (pclk->param.csr_reg == NULL)
304 return data & pclk->param.reg_clk_mask ? 1 : 0;
307 static unsigned long xgene_clk_recalc_rate(struct clk_hw *hw,
308 unsigned long parent_rate)
310 struct xgene_clk *pclk = to_xgene_clk(hw);
313 if (pclk->param.divider_reg) {
314 data = xgene_clk_read(pclk->param.divider_reg +
315 pclk->param.reg_divider_offset);
316 data >>= pclk->param.reg_divider_shift;
317 data &= (1 << pclk->param.reg_divider_width) - 1;
319 pr_debug("%s clock recalc rate %ld parent %ld\n",
321 parent_rate / data, parent_rate);
323 return parent_rate / data;
325 pr_debug("%s clock recalc rate %ld parent %ld\n",
326 clk_hw_get_name(hw), parent_rate, parent_rate);
331 static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
332 unsigned long parent_rate)
334 struct xgene_clk *pclk = to_xgene_clk(hw);
335 unsigned long flags = 0;
341 spin_lock_irqsave(pclk->lock, flags);
343 if (pclk->param.divider_reg) {
344 /* Let's compute the divider */
345 if (rate > parent_rate)
347 divider_save = divider = parent_rate / rate; /* Rounded down */
348 divider &= (1 << pclk->param.reg_divider_width) - 1;
349 divider <<= pclk->param.reg_divider_shift;
351 /* Set new divider */
352 data = xgene_clk_read(pclk->param.divider_reg +
353 pclk->param.reg_divider_offset);
354 data &= ~((1 << pclk->param.reg_divider_width) - 1);
356 xgene_clk_write(data, pclk->param.divider_reg +
357 pclk->param.reg_divider_offset);
358 pr_debug("%s clock set rate %ld\n", clk_hw_get_name(hw),
359 parent_rate / divider_save);
365 spin_unlock_irqrestore(pclk->lock, flags);
367 return parent_rate / divider_save;
370 static long xgene_clk_round_rate(struct clk_hw *hw, unsigned long rate,
371 unsigned long *prate)
373 struct xgene_clk *pclk = to_xgene_clk(hw);
374 unsigned long parent_rate = *prate;
377 if (pclk->param.divider_reg) {
378 /* Let's compute the divider */
379 if (rate > parent_rate)
381 divider = parent_rate / rate; /* Rounded down */
386 return parent_rate / divider;
389 static const struct clk_ops xgene_clk_ops = {
390 .enable = xgene_clk_enable,
391 .disable = xgene_clk_disable,
392 .is_enabled = xgene_clk_is_enabled,
393 .recalc_rate = xgene_clk_recalc_rate,
394 .set_rate = xgene_clk_set_rate,
395 .round_rate = xgene_clk_round_rate,
398 static struct clk *xgene_register_clk(struct device *dev,
399 const char *name, const char *parent_name,
400 struct xgene_dev_parameters *parameters, spinlock_t *lock)
402 struct xgene_clk *apmclk;
404 struct clk_init_data init;
407 /* allocate the APM clock structure */
408 apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL);
410 pr_err("%s: could not allocate APM clk\n", __func__);
411 return ERR_PTR(-ENOMEM);
415 init.ops = &xgene_clk_ops;
417 init.parent_names = parent_name ? &parent_name : NULL;
418 init.num_parents = parent_name ? 1 : 0;
421 apmclk->hw.init = &init;
422 apmclk->param = *parameters;
424 /* Register the clock */
425 clk = clk_register(dev, &apmclk->hw);
427 pr_err("%s: could not register clk %s\n", __func__, name);
432 /* Register the clock for lookup */
433 rc = clk_register_clkdev(clk, name, NULL);
435 pr_err("%s: could not register lookup clk %s\n",
441 static void __init xgene_devclk_init(struct device_node *np)
443 const char *clk_name = np->full_name;
447 struct xgene_dev_parameters parameters;
450 /* Check if the entry is disabled */
451 if (!of_device_is_available(np))
454 /* Parse the DTS register for resource */
455 parameters.csr_reg = NULL;
456 parameters.divider_reg = NULL;
457 for (i = 0; i < 2; i++) {
458 void __iomem *map_res;
459 rc = of_address_to_resource(np, i, &res);
462 pr_err("no DTS register for %s\n",
468 map_res = of_iomap(np, i);
469 if (map_res == NULL) {
470 pr_err("Unable to map resource %d for %s\n",
474 if (strcmp(res.name, "div-reg") == 0)
475 parameters.divider_reg = map_res;
476 else /* if (strcmp(res->name, "csr-reg") == 0) */
477 parameters.csr_reg = map_res;
479 if (of_property_read_u32(np, "csr-offset", ¶meters.reg_csr_offset))
480 parameters.reg_csr_offset = 0;
481 if (of_property_read_u32(np, "csr-mask", ¶meters.reg_csr_mask))
482 parameters.reg_csr_mask = 0xF;
483 if (of_property_read_u32(np, "enable-offset",
484 ¶meters.reg_clk_offset))
485 parameters.reg_clk_offset = 0x8;
486 if (of_property_read_u32(np, "enable-mask", ¶meters.reg_clk_mask))
487 parameters.reg_clk_mask = 0xF;
488 if (of_property_read_u32(np, "divider-offset",
489 ¶meters.reg_divider_offset))
490 parameters.reg_divider_offset = 0;
491 if (of_property_read_u32(np, "divider-width",
492 ¶meters.reg_divider_width))
493 parameters.reg_divider_width = 0;
494 if (of_property_read_u32(np, "divider-shift",
495 ¶meters.reg_divider_shift))
496 parameters.reg_divider_shift = 0;
497 of_property_read_string(np, "clock-output-names", &clk_name);
499 clk = xgene_register_clk(NULL, clk_name,
500 of_clk_get_parent_name(np, 0), ¶meters, &clk_lock);
503 pr_debug("Add %s clock\n", clk_name);
504 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
506 pr_err("%s: could register provider clk %s\n", __func__,
512 if (parameters.csr_reg)
513 iounmap(parameters.csr_reg);
514 if (parameters.divider_reg)
515 iounmap(parameters.divider_reg);
518 CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init);
519 CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init);
520 CLK_OF_DECLARE(xgene_dev_clock, "apm,xgene-device-clock", xgene_devclk_init);