1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
5 * Copyright (c) 2016, NVIDIA CORPORATION.
6 * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
11 #include <clk-uclass.h>
13 #include <dt-structs.h>
17 #include <dm/device-internal.h>
18 #include <dm/devres.h>
20 #include <linux/bug.h>
21 #include <linux/clk-provider.h>
22 #include <linux/err.h>
24 static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
26 return (const struct clk_ops *)dev->driver->ops;
29 struct clk *dev_get_clk_ptr(struct udevice *dev)
31 return (struct clk *)dev_get_uclass_priv(dev);
34 #if CONFIG_IS_ENABLED(OF_CONTROL)
35 # if CONFIG_IS_ENABLED(OF_PLATDATA)
36 int clk_get_by_driver_info(struct udevice *dev, struct phandle_1_arg *cells,
41 ret = device_get_by_driver_info_idx(cells->idx, &clk->dev);
44 clk->id = cells->arg[0];
49 static int clk_of_xlate_default(struct clk *clk,
50 struct ofnode_phandle_args *args)
52 debug("%s(clk=%p)\n", __func__, clk);
54 if (args->args_count > 1) {
55 debug("Invaild args_count: %d\n", args->args_count);
60 clk->id = args->args[0];
69 static int clk_get_by_index_tail(int ret, ofnode node,
70 struct ofnode_phandle_args *args,
71 const char *list_name, int index,
74 struct udevice *dev_clk;
75 const struct clk_ops *ops;
82 ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk);
84 debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
91 ops = clk_dev_ops(dev_clk);
94 ret = ops->of_xlate(clk, args);
96 ret = clk_of_xlate_default(clk, args);
98 debug("of_xlate() failed: %d\n", ret);
102 return clk_request(dev_clk, clk);
104 debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n",
105 __func__, ofnode_get_name(node), list_name, index, ret);
109 static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
110 int index, struct clk *clk)
113 struct ofnode_phandle_args args;
115 debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
120 ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
123 debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
129 return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
133 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
135 struct ofnode_phandle_args args;
138 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
141 return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
145 int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
147 struct ofnode_phandle_args args;
150 ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
153 return clk_get_by_index_tail(ret, node, &args, "clocks",
157 int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
159 int i, ret, err, count;
163 count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells", 0);
167 bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
171 for (i = 0; i < count; i++) {
172 ret = clk_get_by_index(dev, i, &bulk->clks[i]);
182 err = clk_release_all(bulk->clks, bulk->count);
184 debug("%s: could release all clocks for %p\n",
190 static struct clk *clk_set_default_get_by_id(struct clk *clk)
194 if (CONFIG_IS_ENABLED(CLK_CCF)) {
195 int ret = clk_get_by_id(clk->id, &c);
198 debug("%s(): could not get parent clock pointer, id %lu\n",
207 static int clk_set_default_parents(struct udevice *dev, int stage)
209 struct clk clk, parent_clk, *c, *p;
214 num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
216 if (num_parents < 0) {
217 debug("%s: could not read assigned-clock-parents for %p\n",
222 for (index = 0; index < num_parents; index++) {
223 ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
225 /* If -ENOENT, this is a no-op entry */
230 debug("%s: could not get parent clock %d for %s\n",
231 __func__, index, dev_read_name(dev));
235 p = clk_set_default_get_by_id(&parent_clk);
239 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
242 debug("%s: could not get assigned clock %d for %s\n",
243 __func__, index, dev_read_name(dev));
247 /* This is clk provider device trying to reparent itself
248 * It cannot be done right now but need to wait after the
251 if (stage == 0 && clk.dev == dev)
254 if (stage > 0 && clk.dev != dev)
255 /* do not setup twice the parent clocks */
258 c = clk_set_default_get_by_id(&clk);
262 ret = clk_set_parent(c, p);
264 * Not all drivers may support clock-reparenting (as of now).
265 * Ignore errors due to this.
271 debug("%s: failed to reparent clock %d for %s\n",
272 __func__, index, dev_read_name(dev));
280 static int clk_set_default_rates(struct udevice *dev, int stage)
289 size = dev_read_size(dev, "assigned-clock-rates");
293 num_rates = size / sizeof(u32);
294 rates = calloc(num_rates, sizeof(u32));
298 ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
302 for (index = 0; index < num_rates; index++) {
303 /* If 0 is passed, this is a no-op */
307 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
310 debug("%s: could not get assigned clock %d for %s\n",
311 __func__, index, dev_read_name(dev));
315 /* This is clk provider device trying to program itself
316 * It cannot be done right now but need to wait after the
319 if (stage == 0 && clk.dev == dev)
322 if (stage > 0 && clk.dev != dev)
323 /* do not setup twice the parent clocks */
326 c = clk_set_default_get_by_id(&clk);
330 ret = clk_set_rate(c, rates[index]);
333 debug("%s: failed to set rate on clock index %d (%ld) for %s\n",
334 __func__, index, clk.id, dev_read_name(dev));
344 int clk_set_defaults(struct udevice *dev, int stage)
348 if (!dev_has_ofnode(dev))
351 /* If this not in SPL and pre-reloc state, don't take any action. */
352 if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
355 debug("%s(%s)\n", __func__, dev_read_name(dev));
357 ret = clk_set_default_parents(dev, stage);
361 ret = clk_set_default_rates(dev, stage);
368 int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
372 debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
375 index = dev_read_stringlist_search(dev, "clock-names", name);
377 debug("fdt_stringlist_search() failed: %d\n", index);
381 return clk_get_by_index(dev, index, clk);
383 # endif /* OF_PLATDATA */
385 int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk)
389 debug("%s(node=%p, name=%s, clk=%p)\n", __func__,
390 ofnode_get_name(node), name, clk);
393 index = ofnode_stringlist_search(node, "clock-names", name);
395 debug("fdt_stringlist_search() failed: %d\n", index);
399 return clk_get_by_index_nodev(node, index, clk);
402 int clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk)
406 ret = clk_get_by_name_nodev(node, name, clk);
413 int clk_release_all(struct clk *clk, int count)
417 for (i = 0; i < count; i++) {
418 debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
420 /* check if clock has been previously requested */
424 ret = clk_disable(&clk[i]);
425 if (ret && ret != -ENOSYS)
428 ret = clk_free(&clk[i]);
429 if (ret && ret != -ENOSYS)
436 #endif /* OF_CONTROL */
438 int clk_request(struct udevice *dev, struct clk *clk)
440 const struct clk_ops *ops;
442 debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
445 ops = clk_dev_ops(dev);
452 return ops->request(clk);
455 int clk_free(struct clk *clk)
457 const struct clk_ops *ops;
459 debug("%s(clk=%p)\n", __func__, clk);
462 ops = clk_dev_ops(clk->dev);
467 return ops->rfree(clk);
470 ulong clk_get_rate(struct clk *clk)
472 const struct clk_ops *ops;
474 debug("%s(clk=%p)\n", __func__, clk);
477 ops = clk_dev_ops(clk->dev);
482 return ops->get_rate(clk);
485 struct clk *clk_get_parent(struct clk *clk)
487 struct udevice *pdev;
490 debug("%s(clk=%p)\n", __func__, clk);
494 pdev = dev_get_parent(clk->dev);
495 pclk = dev_get_clk_ptr(pdev);
497 return ERR_PTR(-ENODEV);
502 long long clk_get_parent_rate(struct clk *clk)
504 const struct clk_ops *ops;
507 debug("%s(clk=%p)\n", __func__, clk);
511 pclk = clk_get_parent(clk);
515 ops = clk_dev_ops(pclk->dev);
519 /* Read the 'rate' if not already set or if proper flag set*/
520 if (!pclk->rate || pclk->flags & CLK_GET_RATE_NOCACHE)
521 pclk->rate = clk_get_rate(pclk);
526 ulong clk_set_rate(struct clk *clk, ulong rate)
528 const struct clk_ops *ops;
530 debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
533 ops = clk_dev_ops(clk->dev);
538 return ops->set_rate(clk, rate);
541 int clk_set_parent(struct clk *clk, struct clk *parent)
543 const struct clk_ops *ops;
546 debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
549 ops = clk_dev_ops(clk->dev);
551 if (!ops->set_parent)
554 ret = ops->set_parent(clk, parent);
558 if (CONFIG_IS_ENABLED(CLK_CCF))
559 ret = device_reparent(clk->dev, parent->dev);
564 int clk_enable(struct clk *clk)
566 const struct clk_ops *ops;
567 struct clk *clkp = NULL;
570 debug("%s(clk=%p)\n", __func__, clk);
573 ops = clk_dev_ops(clk->dev);
575 if (CONFIG_IS_ENABLED(CLK_CCF)) {
576 /* Take id 0 as a non-valid clk, such as dummy */
577 if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
578 if (clkp->enable_count) {
579 clkp->enable_count++;
582 if (clkp->dev->parent &&
583 device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
584 ret = clk_enable(dev_get_clk_ptr(clkp->dev->parent));
586 printf("Enable %s failed\n",
587 clkp->dev->parent->name);
594 ret = ops->enable(clk);
596 printf("Enable %s failed\n", clk->dev->name);
601 clkp->enable_count++;
605 return ops->enable(clk);
611 int clk_enable_bulk(struct clk_bulk *bulk)
615 for (i = 0; i < bulk->count; i++) {
616 ret = clk_enable(&bulk->clks[i]);
617 if (ret < 0 && ret != -ENOSYS)
624 int clk_disable(struct clk *clk)
626 const struct clk_ops *ops;
627 struct clk *clkp = NULL;
630 debug("%s(clk=%p)\n", __func__, clk);
633 ops = clk_dev_ops(clk->dev);
635 if (CONFIG_IS_ENABLED(CLK_CCF)) {
636 if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
637 if (clkp->flags & CLK_IS_CRITICAL)
640 if (clkp->enable_count == 0) {
641 printf("clk %s already disabled\n",
646 if (--clkp->enable_count > 0)
651 ret = ops->disable(clk);
656 if (clkp && clkp->dev->parent &&
657 device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
658 ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent));
660 printf("Disable %s failed\n",
661 clkp->dev->parent->name);
669 return ops->disable(clk);
675 int clk_disable_bulk(struct clk_bulk *bulk)
679 for (i = 0; i < bulk->count; i++) {
680 ret = clk_disable(&bulk->clks[i]);
681 if (ret < 0 && ret != -ENOSYS)
688 int clk_get_by_id(ulong id, struct clk **clkp)
694 ret = uclass_get(UCLASS_CLK, &uc);
698 uclass_foreach_dev(dev, uc) {
699 struct clk *clk = dev_get_clk_ptr(dev);
701 if (clk && clk->id == id) {
710 bool clk_is_match(const struct clk *p, const struct clk *q)
712 /* trivial case: identical struct clk's or both NULL */
716 /* trivial case #2: on the clk pointer is NULL */
720 /* same device, id and data */
721 if (p->dev == q->dev && p->id == q->id && p->data == q->data)
727 static void devm_clk_release(struct udevice *dev, void *res)
732 static int devm_clk_match(struct udevice *dev, void *res, void *data)
737 struct clk *devm_clk_get(struct udevice *dev, const char *id)
742 clk = devres_alloc(devm_clk_release, sizeof(struct clk), __GFP_ZERO);
744 return ERR_PTR(-ENOMEM);
746 rc = clk_get_by_name(dev, id, clk);
750 devres_add(dev, clk);
754 struct clk *devm_clk_get_optional(struct udevice *dev, const char *id)
756 struct clk *clk = devm_clk_get(dev, id);
758 if (PTR_ERR(clk) == -ENODATA)
764 void devm_clk_put(struct udevice *dev, struct clk *clk)
771 rc = devres_release(dev, devm_clk_release, devm_clk_match, clk);
775 int clk_uclass_post_probe(struct udevice *dev)
778 * when a clock provider is probed. Call clk_set_defaults()
779 * also after the device is probed. This takes care of cases
780 * where the DT is used to setup default parents and rates
781 * using assigned-clocks
783 clk_set_defaults(dev, 1);
788 UCLASS_DRIVER(clk) = {
791 .post_probe = clk_uclass_post_probe,