1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
5 * Copyright (c) 2016, NVIDIA CORPORATION.
6 * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
11 #include <clk-uclass.h>
14 #include <dt-structs.h>
17 static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
19 return (const struct clk_ops *)dev->driver->ops;
22 #if CONFIG_IS_ENABLED(OF_CONTROL)
23 # if CONFIG_IS_ENABLED(OF_PLATDATA)
24 int clk_get_by_index_platdata(struct udevice *dev, int index,
25 struct phandle_1_arg *cells, struct clk *clk)
31 ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
34 clk->id = cells[0].arg[0];
39 static int clk_of_xlate_default(struct clk *clk,
40 struct ofnode_phandle_args *args)
42 debug("%s(clk=%p)\n", __func__, clk);
44 if (args->args_count > 1) {
45 debug("Invaild args_count: %d\n", args->args_count);
50 clk->id = args->args[0];
57 static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
58 int index, struct clk *clk)
61 struct ofnode_phandle_args args;
62 struct udevice *dev_clk;
63 const struct clk_ops *ops;
65 debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
70 ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
73 debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
78 ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk);
80 debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
87 ops = clk_dev_ops(dev_clk);
90 ret = ops->of_xlate(clk, &args);
92 ret = clk_of_xlate_default(clk, &args);
94 debug("of_xlate() failed: %d\n", ret);
98 return clk_request(dev_clk, clk);
101 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
103 return clk_get_by_indexed_prop(dev, "clocks", index, clk);
106 int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
108 int i, ret, err, count;
112 count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
116 bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
120 for (i = 0; i < count; i++) {
121 ret = clk_get_by_index(dev, i, &bulk->clks[i]);
131 err = clk_release_all(bulk->clks, bulk->count);
133 debug("%s: could release all clocks for %p\n",
139 static int clk_set_default_parents(struct udevice *dev)
141 struct clk clk, parent_clk;
146 num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
148 if (num_parents < 0) {
149 debug("%s: could not read assigned-clock-parents for %p\n",
154 for (index = 0; index < num_parents; index++) {
155 ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
157 /* If -ENOENT, this is a no-op entry */
162 debug("%s: could not get parent clock %d for %s\n",
163 __func__, index, dev_read_name(dev));
167 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
170 debug("%s: could not get assigned clock %d for %s\n",
171 __func__, index, dev_read_name(dev));
175 ret = clk_set_parent(&clk, &parent_clk);
178 * Not all drivers may support clock-reparenting (as of now).
179 * Ignore errors due to this.
185 debug("%s: failed to reparent clock %d for %s\n",
186 __func__, index, dev_read_name(dev));
194 static int clk_set_default_rates(struct udevice *dev)
203 size = dev_read_size(dev, "assigned-clock-rates");
207 num_rates = size / sizeof(u32);
208 rates = calloc(num_rates, sizeof(u32));
212 ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
216 for (index = 0; index < num_rates; index++) {
217 /* If 0 is passed, this is a no-op */
221 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
224 debug("%s: could not get assigned clock %d for %s\n",
225 __func__, index, dev_read_name(dev));
229 ret = clk_set_rate(&clk, rates[index]);
231 debug("%s: failed to set rate on clock %d for %s\n",
232 __func__, index, dev_read_name(dev));
242 int clk_set_defaults(struct udevice *dev)
246 /* If this not in SPL and pre-reloc state, don't take any action. */
247 if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
250 debug("%s(%s)\n", __func__, dev_read_name(dev));
252 ret = clk_set_default_parents(dev);
256 ret = clk_set_default_rates(dev);
262 # endif /* OF_PLATDATA */
264 int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
268 debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
271 index = dev_read_stringlist_search(dev, "clock-names", name);
273 debug("fdt_stringlist_search() failed: %d\n", index);
277 return clk_get_by_index(dev, index, clk);
280 int clk_release_all(struct clk *clk, int count)
284 for (i = 0; i < count; i++) {
285 debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
287 /* check if clock has been previously requested */
291 ret = clk_disable(&clk[i]);
292 if (ret && ret != -ENOSYS)
295 ret = clk_free(&clk[i]);
296 if (ret && ret != -ENOSYS)
303 #endif /* OF_CONTROL */
305 int clk_request(struct udevice *dev, struct clk *clk)
307 const struct clk_ops *ops = clk_dev_ops(dev);
309 debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
316 return ops->request(clk);
319 int clk_free(struct clk *clk)
321 const struct clk_ops *ops = clk_dev_ops(clk->dev);
323 debug("%s(clk=%p)\n", __func__, clk);
328 return ops->free(clk);
331 ulong clk_get_rate(struct clk *clk)
333 const struct clk_ops *ops = clk_dev_ops(clk->dev);
335 debug("%s(clk=%p)\n", __func__, clk);
340 return ops->get_rate(clk);
343 ulong clk_set_rate(struct clk *clk, ulong rate)
345 const struct clk_ops *ops = clk_dev_ops(clk->dev);
347 debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
352 return ops->set_rate(clk, rate);
355 int clk_set_parent(struct clk *clk, struct clk *parent)
357 const struct clk_ops *ops = clk_dev_ops(clk->dev);
359 debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
361 if (!ops->set_parent)
364 return ops->set_parent(clk, parent);
367 int clk_enable(struct clk *clk)
369 const struct clk_ops *ops = clk_dev_ops(clk->dev);
371 debug("%s(clk=%p)\n", __func__, clk);
376 return ops->enable(clk);
379 int clk_enable_bulk(struct clk_bulk *bulk)
383 for (i = 0; i < bulk->count; i++) {
384 ret = clk_enable(&bulk->clks[i]);
385 if (ret < 0 && ret != -ENOSYS)
392 int clk_disable(struct clk *clk)
394 const struct clk_ops *ops = clk_dev_ops(clk->dev);
396 debug("%s(clk=%p)\n", __func__, clk);
401 return ops->disable(clk);
404 int clk_disable_bulk(struct clk_bulk *bulk)
408 for (i = 0; i < bulk->count; i++) {
409 ret = clk_disable(&bulk->clks[i]);
410 if (ret < 0 && ret != -ENOSYS)
417 UCLASS_DRIVER(clk) = {